NonStop S-Series Server Description Manual (G06.24+)

TNS Instruction Set
HP NonStop S-Series Server Description Manual—520331-003
11-20
Definitions of TNS Instructions
DCMP (000225). Double Compare DC With BA. The Condition Code in the ENV
register is set as a result of the doubleword integer comparison of DC and BA. Both
operands are then deleted from the stack.
DDIV (000223). Double Divide DC by BA. The doubleword integer contained in DC is
divided in doubleword integer form by the doubleword integer in BA. Both operands
are then deleted, and the result is pushed onto the stack. Overflow is set if the result is
greater than 2
31
–1 or less than –2
31
, or if the divisor (BA) is zero. Carry can be set,
and Condition Code is set on the result.
DDUP (000006). Double Duplicate BA in DC. The doubleword in the top two registers
of the stack is duplicated by pushing a copy of it onto the register stack. Condition
Code is set.
DFG (000367). Deposit Field in Memory. Using the mask bits in register B, this
instruction deposits the bits in register C into the location specified by the 16-bit
address in A. A, B, and C are then deleted. (See the DPF description for further
details on this operation.) DFG accesses the current data segment. Condition Code is
set.
DFS (000357). Deposit Field Into System Data. Using the mask bits in register B, this
instruction deposits the bits in register C into the location specified by the 16-bit
address in A. A, B, and C are then deleted. (See the DPF description for further
details on this operation.) The destination is in the system data segment. A, B, and C
are then deleted. Condition Code is set.
DFX (000416). Deposit Field Extended. Using the mask bits in register C, this
instruction deposits the bits in register D into the memory location specified by the
32-bit even-byte address in registers B and A. All four words are then deleted from the
register stack. (See the DPF description for further details on this operation.)
Condition Code is set.
DISP (000073). Dispatch. This instruction sets bit 15 of INTA and also sets Vi.<15> in
the system interrupt vector (SIV) table entry for the Dispatcher interrupt. If bit 15 of
MASK is set, a Dispatcher interrupt occurs immediately following this instruction
(provided there are no interrupts of higher priority pending). Control is then transferred
to the operating system Dispatcher whose location is pointed to by the SIV table entry.
This is a privileged instruction.
DLLS (1300--). Double Logical Left Shift. If the shift count field is zero, the
doubleword contained in CB is shifted left by the dynamic count contained in A. A is
then deleted from the stack. However, if the shift count field is not zero, BA is shifted
left by that number. On doubleword shifts, dynamic shift counts greater than 255 or
less than 0 give undefined results. Condition Code is set. Refer to Figure 11-4 on
page 11-5 for a comparison of logical (unsigned) shifts and arithmetic (signed) shifts.
DLRS (1301--). Double Logical Right Shift. If the shift count field is zero, the
doubleword contained in CB is shifted right by the dynamic count contained in A. A is
then deleted from the stack. However, if the shift count field is not zero, BA is shifted
right by that number. On doubleword shifts, dynamic shift counts greater than 255 or