NonStop S-Series Server Description Manual (G06.24+)

TNS Instruction Binary Coding
HP NonStop S-Series Server Description Manual—520331-003
B-4
Table B-4. Binary Coding, Branch Instructions
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 vk cc
I1 00+/– P BIC
I1 04+/– P BUN
I 1 0 XX4+/– P BOX
I1 10+/– P BGTR
I1 20+/– P BEQL
I 1 3 0 +/– P BGEQ
I 1 4 0 +/– P BLSS
I1 44+/– P BAZ
I1 50+/– P BNEQ
I1 54+/– P BANZ
I 1 6 0 +/– P BLEQ
I1 64+/– P BNOV
I1 70+/– P BNOC
I1 74+/– P BSUB
I [0 : 1] indicates direct or indirect address.
XX [0 : 3] indicates index register selection.
+/– [0 : 1] implies two’s complement notation; the sign is extended through bit 0 at execution.
Note: Because the program counter register holds the address of the next instruction, a branch-self
instruction
(Branch *) would be coded BUN P-1.
v = Overflow
k = Carry
cc = Condition Codes:
a CCL (result < 0) or (opr1 < opr2)
CCE (result = 0) or (opr1 = opr2)
CCG (result > 0) or (opr1 > opr2)
Note: opr1 is first item pushed
on stack, opr2 is
second.
b CCL (ASCII numeric)
CCE (ASCII alphabetic)
CCG (ASCII special)