NonStop S-Series Server Description Manual (G06.24+)

TNS Instruction Set Definition
HP NonStop S-Series Server Description Manual—520331-003
C-49
Compatibility Notes
Compatibility Notes
The following list defines notes referred to in Table C-2 on page C-11. These notes
identify significant differences in the operation of an instruction in the NonStop (RISC-
based) processors as compared to the operation in earlier TNS (CISC-based)
processors.
1. CALLABLE PRIV
These are nonprivileged instructions that require access to privileged state or
memory. The implementation temporarily becomes privileged (and back) if
necessary.
2. PRIV ONLY
Nonprivileged accesses to SG in the NonStop processor terminate with an
INSTRUCTION FAILURE. On TNS processors, such accesses simply modified
short address space 0 instead.
3. CLOCK ADDR
The TNS clock address of sysstack[ %103 : %106 ] is sysstack[ %350 : 353 ] in the
NonStop processor.
4. OVERFLOW RESULTS UNDEFINED
Results left after an overflow in the NonStop processor are not compatible with
TNS overflow results on this instruction. They are undefined at the time of the
exception and also after the instruction is finished.
5. OVFL TRAP RESULTS UNDEFINED
Register state at the time of the overflow exception is undefined and will vary
depending on the execution mode.
6. OVERFLOW TNS COMPATIBLE
Overflow results after the instruction is finished are defined to be compatible with
TNS processors.
7. NOT ATOMIC
These instructions do not load or store all of their data without intervening
interrupts. This is different from the operation in TNS processors, which
sometimes were able to load or store atomically, and sometimes not, depending on
the memory alignment of the data.
8. (Not used.)
9. CME HANDLING
CME handling requires that INT32s be written into memory as aligned INT32s
instead of as INT16s or unaligned INT32s.
10. TNS INSTRUCTION FAILURE
These instructions are pseudoinstructions for the NonStop processor. TNS
processors do not use these instructions and attempts to do so will cause an
INSTRUCTION FAILURE interrupt.