NonStop S-Series Server Description Manual (G06.24+)

TNS Data Formats and Number Representations
HP NonStop S-Series Server Description Manual—520331-003
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TNS Words and RISC Words
TNS Words and RISC Words
A RISC word is four bytes (32 bits) wide and always begins at a four-byte memory
boundary. Native execution mode and most hardware subsystems in the NonStop
S-series servers use this notion of word size and word alignment.
However, the TNS instruction set, as originally used in the earliest NonStop systems, is
defined in terms of a two-byte (16-bit) word size. Upward compatibility with that
original instruction set is preserved in all NonStop servers, including the NonStop
S-series servers.
As shown in Figure 3-1, two TNS words fit into each RISC word. The TNS word is two
bytes wide and is placed in memory at a two-byte memory boundary. Any two
consecutive TNS words, aligned on any two-byte boundary, constitute a TNS
doubleword. Any four consecutive TNS words, aligned on any two-byte boundary,
constitute a TNS quadrupleword
To provide a distinction for the TNS definition of a word, references to a TNS word are
generally preceded by the TNS modifier where written or verbal ambiguity could occur.
Because this manual necessarily deals frequently with TNS instructions, such as in
Section 11, TNS Instruction Set, TNS terminology is used extensively and reader
comprehension is assumed.
In TNS or accelerated TNS programs, all nonbyte data must be placed on two-byte
memory boundaries to get consistent, correct results from TNS instructions. TNS
compilers automatically take care of this requirement for all normally declared data.
The application programmer must take care to follow this rule when doing dynamic
allocation of nonbyte data through address arithmetic and pointer conversions, or when
navigating a buffer containing nonbyte data. For details, see the data misalignment
information that is provided in the various language reference manuals.
TNS instructions using an extended address to access nonbyte data, such as LWX, all
require the extended byte address to be even. The behavior of the instruction is
undefined if the given address is odd. The instruction could behave in one of three
ways:
•
raising an instruction failure trap
•
implicitly rounding down the address to the next lower even address
Figure 3-1. Two TNS Words Are Equivalent to One RISC Word
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TNS word 0 TNS word 1
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