HP NonStop S-Series Server Description Manual Abstract This manual describes the principal architectural features of and the instruction set used by the HP NonStop™ S-series servers. It is written for system analysts and others who require a technical understanding of the server internals. Product Version N.A. Supported Release Version Updates (RVUs) This manual supports G06.27 and all subsequent G-series RVUs until otherwise indicated by its replacement publication.
Document History Part Number Product Version Published 425160-001 N.A. May 2000 520331-001 N.A. November 2001 520331-002 N.A. August 2002 520331-003 N.A. September 2003 520331-004 N.A.
HP NonStop S-Series Server Description Manual Index Figures What’s New in This Manual xiii Manual Information xiii New and Changed Information About This Manual xv What’s in This Manual xv Where to Get More Information Notation Conventions xvii Tables xiii xvi 1.
1. Introduction (continued) Contents 1. Introduction (continued) Physical Racking of IOAM Enclosures 1-40 Cluster Topologies for 6770 Switches 1-42 Star Topology 1-44 Split-Star Topology 1-46 Tri-Star Topology 1-48 Layered Topologies for 6780 Switches 1-50 Connections Between Zones in Layered Topology 1-52 2.
4. Memory Addressing and Access (continued) Contents 4. Memory Addressing and Access (continued) Kseg0 Usage 4-28 Kseg2 Usage 4-30 Kseg1 Memory Access 4-32 Kseg0 Memory Access 4-34 Kseg2 and Nonprivileged Space Memory Access The TLBPID Process Identifier 4-38 Nonglobal Address Translation 4-40 Address Translation of Global Elements 4-42 Address-Mapping Tables 4-44 Access of Special Pages 4-46 Defining Unallocated Space 4-48 Context-Bound Addresses 4-50 4-36 5.
. TNS Execution Modes (continued) Contents 6.
8. Interrupt System Contents 8. Interrupt System Interrupt Overview 8-2 Interrupt Sequence 8-4 Interrupt Stack Marker Format 8-6 Transferring Control to an Interrupt Handler Interrupt Masking 8-10 TNS Interrupts 8-12 8-8 9.
11. TNS Instruction Set (continued) Contents 11. TNS Instruction Set (continued) Additional Operating-System-Only Instructions Resource Management 11-42 Memory Management 11-42 List Management 11-42 Tracing 11-42 11-41 A. TNS Instruction Lists B. TNS Instruction Binary Coding C. TNS Instruction Set Definition Symbol Definitions C-1 Instruction Definitions C-10 Compatibility Notes C-49 Index Figures Figure 1-1. Figure 1-2. Figure 1-3. Figure 1-4. Figure 1-5. Figure 1-6. Figure 1-7. Figure 1-8.
Figures (continued) Contents Figures (continued) Figure 1-15. Figure 1-16. Figure 1-17. Figure 1-18. Figure 1-19. Figure 1-20. Figure 1-21. Figure 1-22. Figure 1-23. Figure 1-24. Figure 1-25. Figure 1-26. Figure 1-27. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 2-5. Figure 2-6. Figure 2-7. Figure 2-8. Figure 3-1. Figure 3-2. Figure 3-3. Figure 3-4. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4.
Figures (continued) Contents Figures (continued) Figure 4-5. Figure 4-6. Figure 4-7. Figure 4-8. Figure 4-9. Figure 4-10. Figure 4-11. Figure 4-12. Figure 4-13. Figure 4-14. Figure 4-15. Figure 4-16. Figure 4-17. Figure 4-18. Figure 4-19. Figure 4-20. Figure 4-21. Figure 4-22. Figure 4-23. Figure 4-24. Figure 5-1. Figure 5-2. Figure 5-3. Figure 5-4. Figure 5-5. Figure 6-1. Figure 6-2. Figure 6-3. Figure 6-4. Figure 6-5.
Figures (continued) Contents Figures (continued) Figure 6-6. Figure 6-7. Figure 6-8. Figure 6-9. Figure 6-10. Figure 6-11. Figure 6-12. Figure 6-13. Figure 6-14. Figure 6-15. Figure 6-16. Figure 6-17. Figure 6-18. Figure 6-19. Figure 6-20. Figure 6-21. Figure 6-22. Figure 6-23. Figure 6-24. Figure 6-25. Figure 6-26. Figure 6-27. Figure 6-28. Figure 6-29. Figure 6-30. Figure 6-31. Figure 6-32. Figure 6-33. Figure 6-34. Figure 6-35. Figure 6-36. Figure 6-37. Figure 6-38.
Figures (continued) Contents Figures (continued) Figure 6-39. Figure 6-40. Figure 6-41. Figure 6-42. Figure 6-43. Figure 6-44. Figure 6-45. Figure 7-1. Figure 7-2. Figure 7-3. Figure 7-4. Figure 7-5. Figure 7-6. Figure 7-7. Figure 7-8. Figure 8-1. Figure 8-2. Figure 8-3. Figure 8-4. Figure 8-5. Figure 9-1. Figure 9-2. Figure 9-3. Figure 9-4. Figure 9-5. Figure 9-6.
Figures (continued) Contents Figures (continued) Figure 9-7. Figure 9-8. Figure 9-9. Figure 10-1. Figure 10-2. Figure 10-3. Figure 10-4. Figure 10-5. Figure 10-6. Figure 10-7. Figure 10-8. Figure 10-9. Figure 10-10. Figure 10-11. Figure 10-12. Figure 10-13. Figure 11-1. Figure 11-2. Figure 11-3. Figure 11-4. Figure 11-5. Figure 11-6. Figure 11-7. Figure 11-8. Figure 11-9. Figure 11-10. Figure 11-11.
Tables Contents Tables Table 1. Table 3-1. Table 3-2. Table 4-1. Table 8-1. Table A-1. Table A-2. Table B-1. Table B-2. Table B-3. Table B-4. Table B-5. Table B-6. Table B-7. Table C-1. Table C-2.
What’s New in This Manual Manual Information HP NonStop S-Series Server Description Manual Abstract This manual describes the principal architectural features of and the instruction set used by the HP NonStop™ S-series servers. It is written for system analysts and others who require a technical understanding of the server internals. Product Version N.A. Supported Release Version Updates (RVUs) This manual supports G06.
What’s New in This Manual New and Changed Information HP NonStop S-Series Server Description Manual—520331-004 xiv
About This Manual This manual describes the principal architectural features of and the instruction set used by the NonStop S-series servers. It is written for system analysts and others who require a technical understanding of the server internals. This manual provides information for NonStop S-series servers on G06.27 and subsequent G-series release version updates. Note. “NonStop S-series” refers to the hardware that makes up the server. “G-series” refers to the software that runs on the server.
Where to Get More Information About This Manual Table 1. Summary of Contents (page 2 of 2) Section Title This section . . . 8 Interrupt System Describes interrupts that are handled by the NonStop operating system. 9 Interprocessor Communication Describes the protocols and transfer mechanisms used by processors to exchange messages through the ServerNet hardware.
Notation Conventions About This Manual This manual is part of the NonStop S-series server manual set. For more specific details and implementations of the concepts described in this manual, you might want to refer to the NonStop S-Series Planning and Configuration Guide. That guide describes how to plan and configure a NonStop S-series server and provides a case study documenting a sample system.
Change Bar Notation About This Manual HP NonStop S-Series Server Description Manual—520331-004 xviii
1 Introduction This section introduces the fundamental architecture of the NonStop S-Series Sxx000 and S7x00 servers, beginning with a physical overview and then proceeding to describe the components and how they are linked together.
Introduction Processor Enclosures and I/O Enclosures Processor Enclosures and I/O Enclosures A NonStop S-series server is a computer system that is structured around many parallel components, both physical and logical. For example, a single server can include up to 16 processors (CPUs). Processors are housed two in a processor enclosure. Thus a four-processor server would be contained in two processor enclosures, as illustrated in the left part of Figure 1-1.
Processor Enclosures and I/O Enclosures Introduction Figure 1-1. A Four-Processor Server Shown Without and With I/O Enclosures Processor Enclosure Processor Enclosure Processor Enclosure Processor Enclosure I/O Enclosure I/O Enclosure VST201.
Maximum Server Configuration Introduction Maximum Server Configuration Up to 16 processors can be supported in a single server. With two processors contained in a processor enclosure, a 16-processor system would have eight processor enclosures. Processor enclosures are shown unshaded in Figure 1-2. The shaded boxes represent I/O enclosures. One processor enclosure could support a theoretical maximum of nine I/O enclosures.
Maximum Server Configuration Introduction Figure 1-2. A Maximum Server Would Have 44 System Enclosures Processor Enclosure Processor Enclosure Processor Enclosure Processor Enclosure Processor Enclosure Processor Enclosure Processor Enclosure Processor Enclosure VST202.
Introduction Internal Arrangement of System Enclosures Internal Arrangement of System Enclosures Processor enclosures and I/O enclosures are very similar in their internal arrangement, and the generic term that describes both is system enclosure. The primary difference is that, for I/O enclosures, processors do not exist on the CRUs installed in locations 50 and 55. IOMF CRUs are installed in slots 50 and 55 instead.
Internal Arrangement of System Enclosures Introduction Figure 1-3.
Introduction Components of Processor Multifunction (PMF) CRU Components of Processor Multifunction (PMF) CRU The processor multifunction unit (PMF) CRU consists of two boards and (for NonStop S7000 servers) a power supply. The two boards are the processor and memory board (PMB) and the multifunction I/O board (MFIOB). PMF CRUs in NonStop S70000 servers and higher also have a power board. An approximate representation of the PMF CRU is shown in Figure 1-4.
Components of Processor Multifunction (PMF) CRU Introduction Figure 1-4.
Introduction Fault-Tolerant Process Communication Fault-Tolerant Process Communication Fault tolerance for processes is accomplished by providing a backup process in some other processor and providing two or more paths of communication between them, so that if one path or processor should fail, the other processor and paths will remain operable. This basic principle of fault-tolerant process communication is illustrated in Figure 1-5.
Fault-Tolerant Process Communication Introduction Figure 1-5. Processes in Different Processors Have Alternative Communication Paths Processor Enclosure Processor and Memory Board Processor 0 Processor and Memory Board Processor 1 Process A Process B Multifunction I/O Board Multifunction I/O Board X Router Router Y VST205.
Fault-Tolerant Disk Access Introduction Fault-Tolerant Disk Access Multiple disk drives are provided for within the processor enclosure. A single SCSI bus can support up to eight of these drives, and there are two such buses. Both processors in the enclosure have fault-tolerant access to all installed drives. That is, either processor can access the drives through either of the two multifunction I/O boards (MFIOBs). Figure 1-6 illustrates the basic I/O configuration for the two SCSI buses.
Fault-Tolerant Disk Access Introduction Figure 1-6. In Any Processor Enclosure, Both Processors Can Access All Disks Processor Enclosure Processor and Memory Board Processor 0 X Y Processor and Memory Board Processor 1 X Y Multifunction I/O Board Multifunction I/O Board X ServerNet Bus Interface (SBI) SCSI SAC Y ServerNet Bus Interface (SBI) SCSI SAC SCSI SAC SCSI SAC SCSI Bus SCSI Bus VST206.
Maximum Processor Enclosure I/O Introduction Maximum Processor Enclosure I/O A single processor enclosure can support 16 disk drives using the two SCSI buses, and in addition provides two differential SCSI ports, two Ethernet ports, and any I/O devices connected to two ServerNet adapters. Figure 1-8 shows this maximum configuration for one processor enclosure. There is a slight difference in the way this I/O capability is managed by different MFIOBs.
Maximum Processor Enclosure I/O Introduction Figure 1-8.
Introduction Expansion to Second Processor Enclosure Expansion to Second Processor Enclosure Most NonStop systems require that several processor enclosures be connected together. Such interconnections are provided through specialized, plug-in boards in processor enclosures that expand the ServerNet fabric from one enclosure to another. These boards, if present, are installed in pairs in slots 51 through 54 of a processor enclosures. See Figure 1-3 on page 1-7. There are two kinds of such boards.
Expansion to Second Processor Enclosure Introduction Figure 1-9.
Introduction Expansion to External I/O Enclosure Expansion to External I/O Enclosure ServerNet expansion boards (SEBs) provide router ports that can exand to I/O enclosures as well as to other processor enclosures (as in the preceding topic). There are two significantly different methods of providing external I/O. One method uses the I/O enclosures that have the standard system enclosure design, as shown in the first three figures of this section. This method of I/O expansion is described first.
Expansion to External I/O Enclosure Introduction Figure 1-10.
Introduction Components of I/O Multifunction (IOMF) CRU Components of I/O Multifunction (IOMF) CRU The I/O multifunction (IOMF) CRU is the component that determines that a system enclosure is an I/O enclosure rather than a processor enclosure. (Refer back to Figure 1-3 on page 1-7.) IOMF CRUs are installed in pairs in an I/O enclosure. The IOMF in slot 50 of the enclosure is for the X fabric, and the IOMF in slot 55 is for the Y fabric.
Components of I/O Multifunction (IOMF) CRU Introduction Figure 1-11.
Introduction Multiple I/O Enclosures Multiple I/O Enclosures When two processor enclosures are interconnected in a basic configuration (using a single pair of SEBs), they can each support two I/O enclosures. The resulting six system enclosures are connected as shown in Figure 1-12. In this case, the router ports from the SEBs serve two functions: they interconnect the ServerNet fabrics in the two processor enclosures, and they provide external I/O access to two I/O enclosures.
Introduction Multiple I/O Enclosures Figure 1-12. Any Processor Has Dual Access Paths to All I/O, External or Internal Processor Enclosure Processor Enclosure Processor 0 X Y X Processor 1 X Y Y ServerNet Adapter Processor 2 X Y X Processor 3 X Y Y ServerNet Adapter ServerNet Adapter ServerNet Adapter Internal SCSI Buses Internal SCSI Buses SACs SACs SEB SACs SEB X SEB Y I/O Enclosures SACs SEB X Y I/O Enclosures X Y X Y X Y X Y VST211.
Introduction Maximum I/O for a Single Processor Enclosure Maximum I/O for a Single Processor Enclosure If ServerNet adapters are excluded from the processor enclosures, two additional ServerNet expansion boards can be installed, one for the X fabric and one for the Y fabric. As shown in Figure 1-13, these additional SEBs increase the number of I/O enclosures that can be supported from two to five.
Introduction Maximum I/O for a Single Processor Enclosure Figure 1-13. Dual SEBs Permit Connection of More I/O Enclosures Processor Enclosure Processor 0 X Y Processor 1 X Y X Y SACs SEB SEB X Y SEB SEB X Y 5 I/O Enclosures X Y X Y X Y X Y X Y 5 VST212.
Introduction Tetrahedral Topology Tetrahedral Topology When more processor enclosures are added to a system, the core of the topology is designed as a tetrahedron, idealized in the upper part of Figure 1-14. This design, called tetrahedral topology, is used to minimize the number of router hops needed to get from the processors in one enclosure to those in another. The routers illustrated here are only those on the ServerNet expansion boards (SEBs).
Introduction Tetrahedral Topology Figure 1-14. Tetrahedral Topology Efficiently Connects Processor Enclosures Processors Ideal Case 0 1 2 3 Processors Processors 12 4 13 5 14 8 15 9 10 6 11 7 Processors 8 Actual Arrangement 9 0 1 2 3 10 15 5 14 7 4 11 6 13 12 HP NonStop S-Series Server Description Manual—520331-004 1-27 VST213.
Introduction First Triangle of Tetrahedron First Triangle of Tetrahedron Figure 1-15 illustrates the first step in constructing the tetrahedral topology. That first step is to complete a triangle of processor enclosures. For simplicity in Figure 1-15, only the relevant routers are shown. These routers are the ones on the ServerNet expansion boards (SEBs). The upward-pointing arrows from the routers are connections to the two internal processors in each processor enclosure.
Introduction First Triangle of Tetrahedron Figure 1-15.
Introduction Tetrahedral Topology With Four Processor Enclosures Tetrahedral Topology With Four Processor Enclosures For expansion to a fourth processor enclosure, the enclosures now require full connection as a tetrahedron. The tetrahedral topology maintains the requirement of each processor enclosure having direct access to any other processor enclosure in the configuration. The cabling depiction for tetrahedral topology is presented in a standard form in Figure 1-16.
Introduction Tetrahedral Topology With Four Processor Enclosures Figure 1-16. Adding Fourth Processor Enclosure Completes the Core Tetrahedron X Fabric Alone Processor Enclosures P/1 P/2 X Y X Y P/4 P/3 X Y X Y Both Fabrics Processor Enclosures P/1 P/2 X Y X Y P/4 P/3 X Y X Y VST215.
Introduction Maximum I/O for Four Processor Enclosures Maximum I/O for Four Processor Enclosures In tetrahedral topologies, two SEBs for each fabric are required in order to include the I/O enclosures. The arrangement is as shown in Figure 1-17. In this case, the four SEB routers that implement the tetrahedron are not available for connection to I/O enclosures. However, the added four SEBs each provide for connection of five I/O enclosures.
Introduction Maximum I/O for Four Processor Enclosures Figure 1-17. With Dual SEBs, Core Tetrahedron Supports 20 I/O Enclosures I/1 I/2 X X I/3 I/4 X X I/5 X I/O Enclosures I/6 X I/7 I/8 X I/9 X I/10 X X Processor Enclosures X Y X Y X Y X Y 5 5 P/1 X P/2 Y X Y 5 5 X Y X Y P/4 P/3 X X X X X I/15 I/14 I/13 I/12 I/11 X X X I/18 I/19 I/O Enclosures X I/16 X I/17 I/20 VST216.
Introduction Extending the Tetrahedral Topology Extending the Tetrahedral Topology As processor enclosures are added, the ultimate plan for the server as a whole is to grow toward the configuration shown in Figure 1-18. The first four processor enclosures would be configured as a tetrahedron, like the middle four enclosures shown in Figure 1-18. Expansion would then occur from any of the four corners. The actual sequence of adding processor enclosures can vary.
Introduction Extending the Tetrahedral Topology Figure 1-18. Processor Enclosures Exceeding Four Are Added to Corners P/5 P/6 X X P/1 P/2 X X X X P/4 X P/8 P/3 X P/7 VST217.
Introduction Maximum System With Single Server Maximum System With Single Server As shown previously in Figure 1-17 on page 1-33, five I/O enclosures can be connected to the routers in the core tetrahedron. When more processor enclosures are added to those of the core tetrahedron, those additional, outer processor enclosures can each have four I/O enclosures.
Introduction ServerNet Clusters Figure 1-19.
Introduction Modular I/O Modular I/O Up to this point, the I/O topologies have considered only configurations that use I/O enclosures of the same form factor as processor enclosures. One type of enclosure can be converted to the other type. However, an entirely different I/O topology is also available that differs significantly from that provided by connection through the multifunction boards (MFIOBs) in I/O enclosures, that of modular I/O. (For comparison, refer to Figure 1-10 on page 1-19.
Introduction Modular I/O Figure 1-20. I/O Modules Contain ServerNet Switches and ServerNet Adapters Y X Tetrahedral Interprocessor Connections Processor Enclosure ServerNet Expansion Boards (SEB) X Y IOP IOP Processors Backup Multifunction I/O Boards X Y Modular ServerNet Expansion Boards (MSEB) X Y I/O Module ServerNet Switches X I/O Module X Y Y Fibre Channel ServerNet Adapters (FCSA) SACs Disk Array Subsystem Logical Disk Logical Disk Logical Disk Disk Network VST366.
Introduction Modular I/O Connectivity Modular I/O Connectivity Anywhere an I/O enclosure can be connected in the ServerNet tetrahedron, an IOAM enclosure can be connected. Rules that govern mixed configurations (IOAM enclosures and I/O enclosures in the same server) are specified in the NonStop S-Series Planning and Configuration Guide.
Introduction Physical Racking of IOAM Enclosures Figure 1-21.
Introduction Cluster Topologies for 6770 Switches Cluster Topologies for 6770 Switches ServerNet clusters that use 6770 switches can have one of three topologies: star, splitstar, and tri-star. Figure 1-22, which illustrates only one fabric for simplicity, shows the basic concept of all three of these topologies. Each has its own maximum number of servers that can exist in a cluster: 8, 16, or 24, respectively.
Introduction Cluster Topologies for 6770 Switches Figure 1-22. ServerNet Cluster Star Topologies Cluster Switch 1 Cluster Switch 1 Cluster Switch 2 Star Topology Split-Star Topology Cluster Switch 1 Cluster Switch 2 Cluster Switch 3 Tri-Star Topology VST080.
Introduction Star Topology Star Topology The star topology, introduced with the G06.09 RVU, supports up to eight nodes and requires two 6770 cluster switches—one for the external X fabric and one for the external Y fabric. Note. You can configure a single system so that the software necessary for external ServerNet communication is running and ready to communicate with other nodes. However, if no other nodes are connected to the cluster switches, no communication occurs.
Introduction Star Topology Figure 1-23. Eight-Node ServerNet Cluster Using Star Topology 6770 Switch X1 6770 Switch Switch-to-Node Links (80 meters maximum) Y1 External ServerNet X Fabric \A External ServerNet Y Fabric \B \C \D \E \F \G \H Cluster Nodes VST039.
Introduction Split-Star Topology Split-Star Topology The split-star topology, introduced with the G06.12 RVU, supports up to 16 nodes and is required for clusters using 6770 switches that have more than eight nodes. Figure 1-24 shows both fabrics of a 16-node ServerNet cluster connected in a split-star topology. The split-star topology uses up to four cluster switches—two for the X fabric (referred to as X1 and X2) and two for the Y fabric (referred to as Y1 and Y2).
Introduction Split-Star Topology Figure 1-24. 16-Node ServerNet Cluster Using Split-Star Topology Cluster Nodes X1 External ServerNet X fabric consists of two cluster switches, four-lane links, and switch-to-node links Switch-to-Node Links (80 meters maximum) Y1 External ServerNet Y fabric consists of two cluster switches, four-lane links, and switch-to-node links Four-Lane Links (1 km maximum) X2 Switch-to-Node Links (80 meters maximum) Y2 Cluster Nodes VST069.
Introduction Tri-Star Topology Tri-Star Topology The tri-star topology, introduced with the G06.14 RVU, supports up to 24 nodes and is required for clusters using 6770 switches that have more than 16 nodes. Figure 1-25 shows both fabrics of a 24-node ServerNet cluster connected in a tri-star topology. The tri-star topology uses up to six cluster switches—three for the X fabric (referred to as X1, X2 and X3) and three for the Y fabric (referred to as Y1, Y2, and Y3).
Introduction Tri-Star Topology Figure 1-25.
Introduction Layered Topologies for 6780 Switches Layered Topologies for 6780 Switches ServerNet clusters that use 6780 switches provide more extensive clustering capability than that of the 6770 switches described in the preceding four topics. Instead of being configured in a star topology, the 6780 switches are configured in a layered topology, using one or more switch layers and one or more switch zones.
Introduction Layered Topologies for 6780 Switches Figure 1-26.
Introduction Connections Between Zones in Layered Topology Connections Between Zones in Layered Topology The layered topology described in the preceding topic can be extended to consist of two or three switch zones. Figure 1-27 illustrates these cases. A switch zone comprises a pair of X and Y cluster switch groups and the ServerNet nodes connected to them. For simplicity, Figure 1-27 does not show the nodes although the two-zone illustration does identify the numbering of the connected nodes.
Introduction Connections Between Zones in Layered Topology Figure 1-27.
Introduction Connections Between Zones in Layered Topology HP NonStop S-Series Server Description Manual—520331-004 1-54
2 Principles of System Operation This section describes the fundamental operations that implement the architecture described in Section 1, Introduction. The first few topics define the method of identifying ServerNet devices and the structure of ServerNet packets, which are the basic entity for communication between ServerNet devices. Following those discussions are several topics describing the way ServerNet transactions are handled by the processor logic.
Principles of System Operation ServerNet Devices ServerNet Devices Figure 2-1 illustrates the basis for ServerNet device identification, which in turn is the basis for communication between ServerNet devices. A ServerNet device is some kind of ServerNet hardware interface that connects a ServerNet link to a single processor or to an I/O entity that usually controls an array of I/O devices. In the case of a processor, that interface is a processor ServerNet interface.
Principles of System Operation ServerNet Devices Figure 2-1. A ServerNet Device Can Be a Processor, Controller, or Bus Interface ServerNet Devices Processor Processor Processor ServerNet Interface Processor ServerNet Interface I/O Devices SAC SAC SBI SBI X ServerNet Routers X X X X X Processor ServerNet Devices SBI Processor ServerNet Interface SAC SAC SAC I/O Devices SBI = ServerNet Bus Interface SAC = ServerNet Addressable Controller VST330.
Principles of System Operation ServerNet Device Identification ServerNet Device Identification When ServerNet devices communicate with each other, they provide a ServerNet identification (ID) for both the target and the originator of the transmission. The format of the ServerNet ID is shown in Figure 2-2. For current purposes, the entire 20-bit value can be considered as an undivided ServerNet ID. The reserved bits are not currently implemented.
Principles of System Operation ServerNet Device Identification Figure 2-2. ServerNet ID Identifies ServerNet Devices and Subdevices ServerNet ID First Byte Second Byte Third Byte 14 Bits 19 6 Bits 6 5 Reserved 0 ServerNet Device 00 01 10 11 Optional ServerNet Subdevices Use of Subdevice ID Subdevice 00 ServerNet Bus Interface ServerNet Addressable Controller Subdevice 01 Subdevice 10 ServerNet Addressable Controller (Disks: No ServerNet ID or Subdevice ID) VST331.
Principles of System Operation ServerNet Packets ServerNet Packets Communications between ServerNet devices at a fundamental level occurs in the form of variable-length ServerNet packets. Generally, packet transmissions occur in pairs called a ServerNet transaction. The device originating the transaction sends a request packet and the target device sends back a response packet. (exceptions to this one-for-one arrangement can happen for diagnostic and status transactions.
Principles of System Operation ServerNet Packets Figure 2-3.
Principles of System Operation Packet Transmission and Reception Packet Transmission and Reception ServerNet devices take different actions and use different logic based on whether the request part of a transaction originated within the local ServerNet device or in some other ServerNet device (called “remote ServerNet device” in Figure 2-4).
Principles of System Operation Packet Transmission and Reception The BTE and AVT both have direct-memory access (DMA) engines and perform their read and write operations without processor intervention, using buffer addresses that, by prior agreement, have been allocated individually to particular ServerNet devices. Figure 2-4.
Principles of System Operation Sequence for Outgoing Requests Sequence for Outgoing Requests This topic and the next one describe in more detail the BTE operations outlined in the preceding topic. (Then the final two topics describe the AVT.) Figure 2-5 illustrates the sequence of events for locally initiated read and write requests. The only difference for the read and write sequences is that data (D) is not included in read requests. The following steps correspond to the numbered callouts in the figure.
Principles of System Operation Sequence for Outgoing Requests Figure 2-5. Transfer Initiation Logic Uses BTE Descriptors for Outgoing Requests Transfer Initiation Logic Client’s Buffer Virtual Addresses Client Process Transfer Information Block (TIB) 1 2 * Physical Addresses 3 4 * Omitted for Read Request ServerNet Services 5 ServerNet Packet BTE Descriptors D DMA Transfer 7 A H 6 BTE AVT 8 X (Remote Access Logic) VST334.
Principles of System Operation Sequence for Responses to Outgoing Requests Sequence for Responses to Outgoing Requests After the target ServerNet device has received and taken action on the request described in the preceding topic, it sends a response packet back to the sending ServerNet device. Figure 2-6 illustrates the actions taken when the response packet is received back at the requesting device. 1. The incoming response packet is received by the processor ServerNet interface.
Principles of System Operation Sequence for Responses to Outgoing Requests Figure 2-6. BTE Hardware Handles Responses to Outgoing Requests Transfer Initiation Logic Client’s Buffer Client Process Transfer Information Block (TIB) * Omitted for Write Response * ServerNet Services 2 BTE Descriptors DMA Transfer 4 Create Next Outgoing Packet 3 Update or Get Next Descriptor BTE AVT 1 X (Remote Access Logic) VST335.
Principles of System Operation Sequence for Incoming Requests Sequence for Incoming Requests Figure 2-7 illustrates the sequence of operations for an incoming request, one that did not originate in this ServerNet device. In this case, the remote access logic is used instead of the transfer initiation logic (shaded out) that was used in Figure 2-5 and Figure 2-6. 1.
Principles of System Operation Sequence for Incoming Requests 9. The interrupt handler awakens the client process to the fact that an interrupt has occurred and the client process needs to take appropriate action. Figure 2-7.
Principles of System Operation Sequence for Responses to Incoming Requests Sequence for Responses to Incoming Requests Figure 2-8 shows the sequence for sending a response back to the sending ServerNet device after this ServerNet device has received and taken action on the received request. In the case of a write request, the action would have been to write the data to a buffer, as described in the preceding topic. In the case of a read request, the action is part of the response, as described here. 1.
Principles of System Operation Sequence for Responses to Incoming Requests Figure 2-8. AVT Hardware Handles Responses to Incoming Requests (Transfer Initiation Logic) BTE Remote Access Logic ServerNet Services AVT Access Validation and Translation Table (Device 3) 1 In-Request Buffers Interrupt Queue DMA Transfer Device 1 Device 2 Interrupt Handler Device 3 Device 4 * * Omitted for Write Response Device 5 Client Process Device 6 Client’s Buffer Device 7 VST337.
Principles of System Operation Sequence for Responses to Incoming Requests HP NonStop S-Series Server Description Manual—520331-004 2-18
3 TNS Data Formats and Number Representations This section provides heritage information relating to the compatibility issues involved in maintaining compatibility from the earliest Tandem (now HP) CISC-based systems to the current RISC-based systems. The distinction between these two major types of systems is usually denoted by the descriptors TNS and TNS/R.
TNS Data Formats and Number Representations TNS Words and RISC Words TNS Words and RISC Words A RISC word is four bytes (32 bits) wide and always begins at a four-byte memory boundary. Native execution mode and most hardware subsystems in the NonStop S-series servers use this notion of word size and word alignment. However, the TNS instruction set, as originally used in the earliest NonStop systems, is defined in terms of a two-byte (16-bit) word size.
TNS Data Formats and Number Representations • TNS Words and RISC Words completing the operation without rounding down the address On the original TNS CISC processors (NonStop Cyclone and earlier), invalid odd addresses always give the second behavior. On TNS/R processors, including the NonStop S-series servers, the TNS and accelerated TNS execution modes give a mix of these three behaviors for odd addresses.
TNS Data Formats and Number Representations TNS Data Formats TNS Data Formats The available TNS data element sizes are single bytes, two-byte words, four-byte doublewords, and eight-byte quadruplewords. Signed integer data formats are available as word, doubleword, and quadrupleword elements. Floating-point data formats are available as doubleword and quadrupleword elements. See Figure 3-2.
TNS Data Formats and Number Representations TNS Data Formats Figure 3-2.
TNS Data Formats and Number Representations TNS Byte Instructions TNS Byte Instructions Two bytes can be stored in a TNS 16-bit word. Bytes within a multibyte object or data area are addressed and numbered according to the big-endian convention—that is, the numbering is from left to right. Within a 16-bit word, the most significant byte occupies WORD.<0:7> (the left half); the least significant byte occupies WORD.<8:15>. This arrangement is shown in Figure 3-3.
TNS Data Formats and Number Representations TNS Byte Instructions current P register value is less than 32,768) or in TNS word 32,768 (if the current P register value is 32,768 or higher). Figure 3-3.
TNS Data Formats and Number Representations Instructions for Unsigned and Signed Arithmetic Instructions for Unsigned and Signed Arithmetic TNS instructions that perform logical and integer arithmetic operations are named according to TNS data lengths: TNS word, TNS doubleword, or TNS quadrupleword. Unsigned integer arithmetic is restricted mostly to TNS word operands. Signed integer arithmetic can be performed on all three formats.
TNS Data Formats and Number Representations Instructions for Unsigned and Signed Arithmetic Signed Arithmetic Signed numbers are represented in 16 bits (a TNS word), 32 bits (TNS doubleword), or 64 bits (TNS quadrupleword). Positive values are represented in true binary (base 2) notation. Negative values are represented in two’s-complement notation with the sign bit of the most significant word set to 1 (that is, WORD[0].<0>).
TNS Data Formats and Number Representations Instructions for Decimal and Floating-Point Arithmetic All three indicators (V, CC, and K) can be tested by associated test-and-branch instructions (branch-on-overflow, branch-on-condition-code, and branch-on-carry) and the program execution sequence can be altered accordingly. Instructions for Decimal and Floating-Point Arithmetic Decimal arithmetic can be performed only on quadrupleword operands.
TNS Data Formats and Number Representations Instructions for Decimal and Floating-Point Arithmetic The bit-level representations of TNS and IEEE floating-point values are incompatible. The two formats have different precisions and exponent ranges in their 32-bit sizes, and different precisions and exponent ranges in their 64-bit sizes. For a description of the IEEE representations as used on NonStop S-series servers, see Chapter 7, “FPU Overview,” in MIPS RISC Architecture by Gerry Kane and Joe Heinrich.
TNS Data Formats and Number Representations Instructions for Decimal and Floating-Point Arithmetic floating-point number affects only the high-order bit and not the fraction or exponent fields. The absolute-value range of 32-bit floating-point numbers is ± 2-256 through ± (1 – 2-23) * 2256. In decimal notation, this is approximately ± 8.64 * 10-78 through ± 1.15 * 1077.
4 Memory Addressing and Access This section describes how memory is addressed and accessed within the processors of the NonStop S-series servers. Note. Some very low-level detail is presented in this section. Be aware that specific address allocations, table formats, and many architectural details have changed in the past and will change in the future. Application software should never directly use or depend on the details presented in this section.
Memory Addressing and Access The Process Address Space The Process Address Space The virtual memory system of each processor in the NonStop S-series servers provides a 4-GB virtual address space, as illustrated in Figure 4-1. Virtual memory is arranged as multiple process address spaces. These address spaces are primarily assigned to the various processes executing in the processor. However, only one such space can be the current one.
Memory Addressing and Access The Process Address Space Figure 4-1. Nonprivileged and Privileged Spaces Include Global and Nonglobal Areas Most Recent 256 Process Address Spaces Current Process Address Space Nonglobal Nonprivileged Addresses Relative Address 0 Global Nonprivileged Addresses Nonprivileged Process Space (2 GB) Global Privileged Addresses Nonglobal Privileged Addresses Privileged Process Space (2 GB) VST231.
Memory Addressing and Access Organization of the Process Address Space Organization of the Process Address Space As Figure 4-2 indicates, all of the nonprivileged space and half of the privileged space are subdivided for addressing purposes into three substructures. (The first half of the privileged space, shaded dark, does not use this same organization, as explained further in the next two topics.
Memory Addressing and Access Organization of the Process Address Space Figure 4-2. Process Address Space Includes Regions, Unitary Segments, and Pages Process Data Space Region 0 Region ••• Unitary Segment 0 Unitary Segment Nonprivileged Space (2 GB) 255 Page 0 63 7 Page Byte 0 ••• Privileged Space (2 GB) Byte 16383 VST232.
Memory Addressing and Access Addressing in the Process Address Space Addressing in the Process Address Space All addressing is accomplished with 32-bit byte addresses, thus determining the 4-gigabyte addressing range of the process address space. That space, however, is not of uniform function. As already shown by the previous two topics, the process address space is divided into a nonprivileged space (the lower-address half) and a privileged space (the higher-address half).
Memory Addressing and Access Addressing in the Process Address Space Figure 4-3. Four Distinct Addressing Areas Exist in the Process Address Space %h 00000000 16384 Unitary Segments (2048 MB) Nonprivileged Space Relative Addressing %h 80000000 Kseg0 Kseg1 Privileged Space Kseg2 %h FFFFFFFF Cached Access to 512 MB Physical Memory Uncached Access to 512 MB Physical Memory 8192 Unitary Segments (1024 MB) Physical Addressing Absolute Addressing VST233.
Memory Addressing and Access Address Formats Address Formats The 32-bit address used for each of the four addressing spaces is identified by the bit pattern of the first one, two, or three bits. See Figure 4-4. The one-bit pattern of “0” specifies a nonprivileged space address (relative). The three-bit pattern of “100” or “101” specifies a Kseg0 or Kseg1 address, respectively (physical). The two-bit pattern of “11” specifies a Kseg2 address.
Memory Addressing and Access Address Formats Figure 4-4.
Memory Addressing and Access Selectable and Flat Logical Segments Selectable and Flat Logical Segments Data address space for a process is allocated in virtual memory by one or more SEGMENT_ALLOCATE_ procedure calls. Each call allocates a logical segment that is of a specifiable size. A logical segment can be either one of two kinds: a selectable segment or a flat segment. These are compared in Figure 4-5, and the choice is made by a parameter supplied to the SEGMENT_ALLOCATE_ call.
Memory Addressing and Access Selectable and Flat Logical Segments Figure 4-5. Selectable and Flat Logical Segments Differ in Allocation Method Selectable Segments Relative Segment 4 Nonprivileged Space Relative Segment 1023 Flat Segment Flat Segment Flat Segment VST235.
Memory Addressing and Access First Four Relative Segments First Four Relative Segments Figure 4-6 shows addressing details for the first four regions, particularly the first region. Hexadecimal starting addresses are indicated for the regions and the first five relative segments, 0 through 4. Relative segment 0 is the TNS user data segment, which, for TNS processes, provides relative addressing for process global variables and the TNS data stack. Relative segments 1, 2, and 3 are skipped.
Memory Addressing and Access First Four Relative Segments Figure 4-6.
Memory Addressing and Access Main Stack and SRL Data Main Stack and SRL Data Following the space allocations for the user-allocatable flat segments are several regions that provide relative addressing for the main stack of the process and instance data for shared run-time libraries (SRLs). See Figure 4-7. The 4E region (hexadecimal address 4E000000) is the beginning of this area, and the 5A region is the end of the area (address of the last byte is 5BFFFFFF).
Memory Addressing and Access Main Stack and SRL Data Figure 4-7. Main Stack and SRL Data for a Process Are in Nonprivileged Space 4E000000 Main Stack 50 Private SRL Instance Data Nonprivileged Space 52 54 56 58 5A Public SRL Instance Data 5C VST237.
Memory Addressing and Access Last Eight Regions Last Eight Regions All of the user code, and user library, and shared run-time library (SRL) allocations are accessed within the code regions, as illustrated in Figure 4-8. These are the last eight regions (256 megabytes) in the nonprivileged space. In addition, the system library is also included in the code regions of each process. With few exceptions (Debug, for example), writing is not permitted into any of the code regions.
Memory Addressing and Access Last Eight Regions Figure 4-8. The Last Eight Regions Are for Code Addressing Native Process TNS Process UCr User Code UC User Code Nonprivileged Space UL User Library Shared Run-Time Libraries (SRLs) SL System Library SLr System Library SLr System Library VST238.
Memory Addressing and Access Native Process Code Allocations Native Process Code Allocations For processes that have been compiled with a native mode compiler (a native process), the addressing for the user code file of that process starts at the beginning of the 70 region and can occupy all of the 70 and 72 regions. A native process may have procedures in a private shared run-time library (SRL). If so, the code for these is allocated from the start of the 74 region.
Memory Addressing and Access Native Process Code Allocations Figure 4-9. Native Process Has Two Regions for User Code, Four for Libraries Region Starting Address 70000000 UCr User Code Nonprivileged Space 72 74 76 78 Private Shared Run-Time Library Public Shared Run-Time Library 7A (SL System Library) 7C 7E SLr System Library Millicode End of Nonprivileged Space Start of Privileged Space VST239.
Memory Addressing and Access TNS Process Code Allocations TNS Process Code Allocations For TNS processes, including processes that have accelerated object code, addressing for the user code file of that process occupies the 70 region. The start of this region is hexadecimal address 70000000. See Figure 4-10. Up to the first 32 (of the 256) unitary segments of this region can be allocated for the TNS object code.
Memory Addressing and Access TNS Process Code Allocations Figure 4-10. TNS Process Has One Region for User Code, One for User Library Region Starting Address 70000000 72 UC User Code UL User Library Nonprivileged Space 74 76 78 7A SL System Library 7C SLr System Library 7E Millicode End of User Space Start of Kernel Space VST240.
Memory Addressing and Access Allocation for TNS and Accelerated Code Allocation for TNS and Accelerated Code Figure 4-11 shows an expansion of a code region for a process that uses accelerated object code. (This does not apply to native processes.) This could be a user code, user library, or system library region of any given nonprivileged space. The unitary segment numbers and starting addresses shown within the region are relative to the beginning of the region.
Memory Addressing and Access Allocation for TNS and Accelerated Code Figure 4-11. Both TNS and Accelerated Code Are Included in a Code Region UC, UL, or SL TNS Code Unitary Segment 32 or 7A000000 %h 000000 020000 ••• Unitary Segment 0 %h 70000000 72000000 %h 400000 Accelerated Code (UC, UL, or SL) Unitary Segment 255 %h FE0000 VST241.
Memory Addressing and Access Chart of Nonprivileged Space Allocation Chart of Nonprivileged Space Allocation The chart shown in Table 4-1 applies to the G05.00 and G06.00 RVUs. RVUs prior to G05.00 used different space allocations, and future releases can be expected to change again. For convenient reference, the nonprivileged space is shown divided into 64 regions, each identified with the hexadecimal starting address of the region, abbreviated to the first two digits.
Memory Addressing and Access Chart of Nonprivileged Space Allocation Table 4-1.
Memory Addressing and Access Physical Memory Addressing Physical Memory Addressing The preceding topics describe the nonprivileged space. This and the next two topics describe the privileged space. As indicated earlier, privileged space addresses are signified by a 1 in the most significant bit position of the 32-bit address word. For segment-numbering purposes, physical addresses can be considered to be a special form of absolute address.
Memory Addressing and Access Physical Memory Addressing Figure 4-12. Kseg0 and Kseg1 Both Map Permanently to Physical Memory (Nonprivileged Space) 0 Kseg0 Physical Memory 4096 Kseg1 Absolute Unitary Segments 8192 Kseg2 (Mapped) 16383 VST242.
Memory Addressing and Access Kseg0 Usage Kseg0 Usage Kseg0 allows cached access to the first 512 megabytes of installed physical memory. As indicated in Figure 4-13, some unitary segments of Kseg0 are allocated as dedicated, permanently resident parts of physical memory. The remaining space (shown shaded) is available for dynamic memory management. Dedicated allocations include the system data segment and the system code segments.
Memory Addressing and Access Kseg0 Usage Figure 4-13.
Memory Addressing and Access Kseg2 Usage Kseg2 Usage The Kseg2 portion of privileged space comprises absolute segments 8192 through 16383. Like nonprivileged space, Kseg2 is organized into regions. Being half the size of nonprivileged space, however, Kseg2 has 32 regions instead of 64. Most of the Kseg2 space, as shown in Figure 4-14, is used to address absolute memory and is therefore global in nature.
Memory Addressing and Access Kseg2 Usage RESIZESEGMENT. There can be up to 1024 absolute segments (or 128 megabytes) for each logical segment that might exist for the process. Figure 4-14.
Memory Addressing and Access Kseg1 Memory Access Kseg1 Memory Access The preceding topics in this section explain the concepts of virtual memory addressing. This and the remaining topics in this section consider how physical memory is actually accessed in the processor. Because access to memory through Kseg1 is the simplest, it is described first, illustrated in Figure 4-15. The memory caches are not used when memory is addressed through Kseg1.
Memory Addressing and Access Kseg1 Memory Access Figure 4-15. Access Through Kseg1 Is Direct: No Caching, No Address Translation Process Data Space 0 Memory Control 2 Physical Memory Kseg0 Physical Address Kseg1 Instructions Address 1 3 3 Data Instruction Processor VST245.
Memory Addressing and Access Kseg0 Memory Access Kseg0 Memory Access Kseg0 addressing is similar to Kseg1 addressing, providing access to exactly the same physical memory. However, memory information is transferred between memory and the memory caches in blocks and as individual four-byte words between the caches and the instruction processor. Thus the access is not direct, as in the case of Kseg1 addressing. There are two levels of caches, designated primary and secondary.
Memory Addressing and Access Kseg0 Memory Access Figure 4-16. Memory Access Through Kseg0 Uses Memory Caches 1 Kseg0 Virtual Address RISC Instruction Processor Physical Address Cache Logic 4 Secondary Cache Instruction (Read only) 5 Fill 2 Instruction Cache 8 Data (Read) 3 Primary Cache Hit? 2 6 Block Read Command if Secondary Cache Miss Secondary Cache Hit? Data (Write) Data Cache Store Buffer Main Memory Write Buffer 8 Line Fill 7 Or VST246.
Memory Addressing and Access Kseg2 and Nonprivileged Space Memory Access Kseg2 and Nonprivileged Space Memory Access For Kseg0 addressing (previous topic), the physical address needed for cache access is derived simply by stripping high-order bits from the virtual address. For Kseg2 and nonprivileged space addressing, virtual addresses must specifically be translated to physical.
Memory Addressing and Access Kseg2 and Nonprivileged Space Memory Access Figure 4-17. Memory Access Through Nonprivileged Space or Kseg2 Requires Address Translation 1 Virtual Address: Nonprivileged Space or Kseg2 RISC Instruction Processor Translation Lookaside Buffer (TLB) TLB Entry 1 TLB Hit? If TLB Miss, Access Memory Translation Tables Fill 4 ITLB Entry 3 ITLB 2 To Cache To Primary Caches Physical Address Main Memory Translation Tables Cache Logic (See Previous Topic) VST247.
Memory Addressing and Access The TLBPID Process Identifier The TLBPID Process Identifier One of the fields in a TLB entry is an 8-bit process identifier. This field makes it possible to distinguish translations that belong to one process from those that belong to another process. (Remember from the very first topic in this section that all processes use the same numerical range of virtual addresses.
Memory Addressing and Access The TLBPID Process Identifier Figure 4-18. The TLBPID Distinguishes the Address Space of a Process TLBPID Owner Array 237 161 63 0 1 2 3 4 5 6 7 8 9 6 180 128 44 19 211 250 251 252 253 254 255 TLBPID Pointer Process (#180) (251) Nonglobal Address 0 26 31 TLBPID 0 6 7 Region 14 15 17 18 Relative Segment Page 31 Byte VST248.
Memory Addressing and Access Nonglobal Address Translation Nonglobal Address Translation The entries in the translation lookaside buffer (TLB) are 128 bits wide, as shown in the lower part of Figure 4-19. The high-order 64 bits contain the fields used to identify the page address that is translated in one given slot of the TLB: a virtual page number (VPN) and a translation lookaside buffer’s process identifier (TLBPID).
Memory Addressing and Access Nonglobal Address Translation Figure 4-19. Nonglobal Address Translations Require Matching TLBPID Process-Specific Address 6 7 0 TLBPID Region 14 15 17 18 Rel.
Memory Addressing and Access Address Translation of Global Elements Address Translation of Global Elements As was shown in the first topic of this section, parts of the nonprivileged space and most of the privileged space of virtual memory are global among the currently defined processes. The entire range of virtual addresses constituting absolute virtual memory (most of Kseg2), for example, is global to all process address spaces.
Memory Addressing and Access Address Translation of Global Elements Figure 4-20. Address Translation of Global Elements Ignores TLBPID Process-Specific Address 0 TLBPID 14 15 17 18 6 7 Region Rel.
Memory Addressing and Access Address-Mapping Tables Address-Mapping Tables The translation lookaside buffer (TLB) is located on the RISC chip, and it is extremely fast in performing virtual-to-physical address translations—actually in half a machine cycle. However, any time a reference is made to a location in a page that does not currently have a translation in the TLB (a translation miss), the memory-management millicode must obtain the page translation from memory tables.
Memory Addressing and Access Address-Mapping Tables Figure 4-21. On TLB Miss, Nonprivileged Space and Kseg2 Space Translation Uses Address-Mapping Tables Nonprivileged or Kseg2 Space Address 0 6 7 Region 14 15 17 18 Relative Seg. Process Data Space Tables 0 Page 31 Byte Page Tables Vseg Tables Translation Lookaside Buffer (TLB) 0 0 63 7 96 127 255 VST251.
Memory Addressing and Access Access of Special Pages Access of Special Pages Some special processor features need to be implemented as reserved virtual memory spaces. Three specific features are described in this topic: (1) a memory-resident TNS register stack, located in a page called the RP wrap page, (2) a range of nil addresses, and (3) a scratchpad for millicode use, called the SPAD pages. The simulated register stack is allocated in the last unitary segment of the nonprivileged space.
Memory Addressing and Access Access of Special Pages Figure 4-22. Special Pages Are Accessed Through Fixed Addresses Process Address Space RP Wrap Segment RP Wrap Page MemoryResident Register Stack Absolute Segments SPAD Pages (24 through 27) 16381 Kseg2 16382 Nil Addresses 16383 Nil Addresses VST257.
Memory Addressing and Access Defining Unallocated Space Defining Unallocated Space Whereas translation misses in the translation lookaside buffer (TLB) are quite common, invalid addresses (those that point to nonexistent memory) are rare. It is reasonable therefore to eliminate explicit validity checking of addresses, such as checking against a limit, and instead handle invalid addresses as exceptional cases.
Memory Addressing and Access Defining Unallocated Space Figure 4-23. Unallocated Space Is Defined With a Few Null Tables Process Data Space Table Special Vseg Tables Special Page Tables Null Vseg (Nonglobal) Null PT (Nonglobal) Null Vseg (Global) Null PT (Global) VST258.
Memory Addressing and Access Context-Bound Addresses Context-Bound Addresses Because only one addressing space, Kseg2, is available for providing aliases for all the existing nonprivileged spaces (one or more per process), absolute addressing as an alias has a finite limitation. Therefore, an alternate means of aliasing is provided, called context-bound addressing. This is a software facility. It permits logical segments to be created without absolute-address aliases.
Memory Addressing and Access Context-Bound Addresses Figure 4-24. Context-Bound Addresses Substitute for Aliases in Unaliased Segments CONTEXT CRADDR Context-Relative Address Tables of Vsegs for Corresponding Nonprivileged Spaces Current Process Data Space Foreign Process Data Space VST259.
Memory Addressing and Access Context-Bound Addresses HP NonStop S-Series Server Description Manual—520331-004 4-52
5 Instruction Processing Environments This section describes the difference between native and TNS processes, their stacks and segment allocations, as well as mode transitions that occur during the execution of different types of processes.
Instruction Processing Environments Native and TNS Programs and Processes Native and TNS Programs and Processes The RISC processor that is the instruction processing unit (IPU) of each NonStop S-series processor executes only RISC instructions. However, to accommodate the large installed base of TNS programs, the processor has been designed to accept and execute TNS programs in addition to programs that are compiled directly to RISC instructions.
Instruction Processing Environments Native and TNS Programs and Processes Figure 5-1. Comparing Native and TNS Processes Native Process TNS Processes TNS Object Code TNS Program Accelerator Native Program RISC Instructions RISC Instructions TNS Instructions Memory Accelerated Program Memory Millicode Memory Native Process TNS Process TNS Process RISC Instructions RISC Instruction Processor VST260.
Instruction Processing Environments Stacks for Native and TNS Processes Stacks for Native and TNS Processes Data stacks are a principal resource of each process. They provide a historical record of procedure calls, as well as the local addressing environment of procedures, including some of the parameters passed between procedures. In the execution of a native process, two different stacks are used, depending on whether or not privileged mode is in effect.
Instruction Processing Environments Stacks for Native and TNS Processes Figure 5-2. A Native Process Uses Two Stacks; TNS Uses Three Process Data Space User Space (64 Regions) Hexadecimal Address 00000000 TNS User Data Stack 02000000 08000000 Global Data for Native Process 0A000000 4E000000 50000000 Main Stack 5E000000 Privileged Stack Kernel Space 60000000 VST261.
Instruction Processing Environments Code and Data Allocations Code and Data Allocations As explained in Section 4, Memory Addressing and Access, each process has its own separate allocation of user space in virtual memory. Within that allocation, segments for code are assigned in the last few regions, and segments for data are assigned in several lower address regions.
Instruction Processing Environments Code and Data Allocations Figure 5-3. Code and Data Allocations Are Separate and Treated Differently C Data Segments for Three Processes B Arithmetic Operations A Load Registers Store C B A C B Code Segments for Three Processes A Instructions Fetched for Process A VST263.
Instruction Processing Environments Sharing of Code and Data Segments Sharing of Code and Data Segments Code segments can be shared. That means that any number of processes can be fetching and executing instructions from the same object code segment. The operating system keeps track of which processes are using which segments. When the final process among several that are using a given code segment ceases to exist, that code segments can (and will) be deallocated by the operating system.
Instruction Processing Environments Sharing of Code and Data Segments Figure 5-4. Code Segments and Some Data Segments Can Be Shared C Data Stack Segments (Private) B Load Store A Registers Logical Segments (Private or Shared) Load Store Y X X C B A N N K K P J Code Segments for Three Processes (Always Shareable) K L M O VST264.
Instruction Processing Environments Restricting Mode Transitions Restricting Mode Transitions When a process begins execution, the mode of execution depends on the form of the program object code. If the program was compiled as a TNS program, execution begins in TNS mode, wherein a millicode interpreter program executes on behalf of the TNS instructions.
Instruction Processing Environments Restricting Mode Transitions Figure 5-5. Only Two Kinds of Mode Transitions Are Permitted UC UC UCr A B TNS Code TNS Code C SL TNS Code Native Code Accelerated Code SLr Accelerated Code Native Code Legend Calls Within Mode TNS to Accelerated Accelerated to Native HP NonStop S-Series Server Description Manual—520331-004 5-11 VST265.
Instruction Processing Environments Restricting Mode Transitions HP NonStop S-Series Server Description Manual—520331-004 5-12
6 TNS Execution Modes The following topics describe operations for the TNS compatibility modes.
TNS Execution Modes Execution Modes for TNS Compatibility Execution Modes for TNS Compatibility This topic describes the basic differences between the two execution modes that provide TNS compatibility. TNS mode means that the interpreter millicode (in resident memory) executes on behalf of the process, interpreting TNS instructions from the object code in memory during run time. The millicode updates process state information as if the process were executing on a TNS processor.
TNS Execution Modes Execution Modes for TNS Compatibility Figure 6-1. Two Execution Modes Provide TNS Compatibility TNS Instructions TNS Object Code TNS Object Code Accelerated Code TNS Instructions Accelerator RISC Instructions Memory Process A Interpreter Millicode RISC Instructions RISC Instructions TNS Mode Process B Accelerated Mode RISC Processor VST266.
TNS Execution Modes TNS Addressing Conventions TNS Addressing Conventions When TNS mode or accelerated mode is in effect in the processor, both code and data are located in different areas of virtual memory than when native mode is in effect (see Section 4, Memory Addressing and Access). In addition, these modes use addressing conventions that are specific to the TNS architecture. This and the remaining topics in this section describe these conventions.
TNS Execution Modes TNS Addressing Conventions Figure 6-2. TNS and Accelerated Modes Use TNS Addressing Conventions UC.3 C [0] UC.2 UC.1 G [0] UC.0 TNS User Data Stack User Data Segment G [32767] User Code Segment G [65535] HP NonStop S-Series Server Description Manual—520331-004 6-5 C [65535] VST267.
TNS Execution Modes The Environment Register The Environment Register The 16-bit ENV (Environment) register shows the state of the currently executing procedure. That is, the register indicates the code space in which the procedure is currently executing, the data segment that it is using, whether or not privileged mode is in use, whether or not arithmetic traps are enabled, and specific results of the most recent instruction (overflow, carry, and condition code).
TNS Execution Modes The Environment Register The carry bit, or K bit, (ENV.<9>), when equal to 1, generally indicates that a carry out of the high-order bit position occurred when an add or subtract instruction was executed on a 16-, 32-, or 64-bit operand. It reflects the result of the last such instruction executed. Other uses of the K bit exist, such as to specify the result of executing a scan instruction (SBW or SBU). The overflow bit, or V bit, (ENV.
TNS Execution Modes The Register Stack The Register Stack To maintain compatibility with other earlier systems, NonStop S-series processors provide a register stack that is used mostly in nonaccelerated (TNS) execution mode. The register stack consists of eight 16-bit registers, designated R[0] (register stack, element 0) through R[7]. See Figure 6-4. The register stack is where arithmetic computations are performed and where most comparisons are made.
TNS Execution Modes The Register Stack Figure 6-5. The Top-of-Stack Can Occupy Various Positions in the Register Stack D C B A H G F E G F E D C B A H 0 Top Top Top 1 RP Environment Register 1 1 0 R [6] 64-Bit Operands Operand 1 (B) Operand 2 (A) 32-Bit Operands D C B A 1 R [3] 16-Bit Operands B A RP Environment Register Top H G F E D C B A Operand 1 (HGFE) Operand 2 (DCBA) Operand 1 (DC) Operand 2 (BA) VST270.
TNS Execution Modes Register Stack Operations Register Stack Operations A typical operation to add two numbers in the register stack is illustrated in Figure 6-6. The operation proceeds as follows: the operands are first loaded from global data (G) into the register stack using LOAD instructions, then an IADD (integer add) instruction is executed to perform the desired arithmetic, and finally the result is stored back into memory using a STOR instruction.
TNS Execution Modes Register Stack Operations Figure 6-6. An Example of Register Stack Operations RP Empty State 1 R [7] LOAD G+002 5 R [0] 5 6 R [1] Top 11 6 R [0] R [1] 0 0 ENV Register 1 ENV Register 0 ENV Register 1 ENV Register RP Top Top 0 RP 0 STOR G+004 ENV Register RP 0 IADD 1 Empty 0 LOAD G+003 1 0 RP 11 6 1 R [7] 1 Empty VST271.
TNS Execution Modes The Register Stack in Memory The Register Stack in Memory As implemented in the NonStop S-series processor, the register stack (in TNS mode) consists of eight dedicated locations in virtual memory, rather than eight physical hardware registers. The location for this simulated register stack is found in the last segment of every user data space. (Region 63 is a shared region among all processes.
TNS Execution Modes The Register Stack in Memory Figure 6-7. The TNS Register Stack Is Implemented in the RP Wrap Page Byte Offset 0 Mode Segment 0 of Region 63 R [0] 512 R [1] 1024 R [2] %h 7FFE0000 Absent Page %h 7FFE1000 1536 R [3] RP Wrap Page 2048 R [4] 2560 R [5] 3072 R [6] 3584 R [7] %h 7FFE2000 Absent Page VST272.
TNS Execution Modes Basic P Register Operations Basic P Register Operations The P register (Program register) is the program counter of the TNS environment. It contains the 16-bit C[0]-relative address of the next instruction to be executed. Conventionally, the contents of the P register are incremented by 1 at the beginning of instruction execution so that, ordinarily, instructions are fetched (and executed) from ascending memory locations. This is shown in the upper part of Figure 6-8.
TNS Execution Modes Basic P Register Operations Figure 6-8.
TNS Execution Modes Branching, Direct and Indirect Branching, Direct and Indirect Addresses for branching (and for constants) in a code segment are calculated relative to the current setting of the P register. This is referred to as P-relative addressing. Instructions that reference a code segment have an eight-bit field (seven magnitude bits plus a sign) for specifying a relative displacement from the current P register setting. The range of the displacement is therefore –128:+127 words.
TNS Execution Modes Branching, Direct and Indirect Figure 6-10. Two Examples of Branching Code Area Direct Branch 0 0 0 0 0 1 1 0 BUN + 13 1 Displacement C[105] P Register 106 +13 + 119 C[119] P Register Indirect Branch 1 0 0 0 0 1 1 Displacement 1 BUN + 15, I 1 C[320] P Register 321 +15 + 207 336 336 + C[336] 207 543 C[543] P Register VST275.
TNS Execution Modes Indexed Addressing in a Code Segment Indexed Addressing in a Code Segment In addition to direct and indirect addressing, an offset value in one of three index registers can be added to the address of the direct or indirect location before the final address is calculated. This permits a code segment location to be referenced as an offset from a base location; this is called indexing.
TNS Execution Modes Indexed Addressing in a Code Segment Figure 6-11. An Example of Code Segment Indexing Code Area C [3433] C [3439] Indirect, Indexed 1 0 1 0 0 0 0 0 0 1 0 0 0 LWP 8,I,6 C [3728] -304 C [3737] Displacement Index Register P 3729 +8 + 3737 + -304 3433 Register Stack 3439 + 6 R [6] 6 VST276.
TNS Execution Modes Direct and Indirect Addressing in the Data Segment Direct and Indirect Addressing in the Data Segment A TNS process has only one segment for its global data, called the user data segment. It contains the process’s global variables and data stack. Various addressing modes are provided for addressing locations relative to the current stack frame; however, those modes will be covered in later topics, when procedure calls are described.
TNS Execution Modes Direct and Indirect Addressing in the Data Segment Figure 6-12. An Example of Indirect Addressing in the Data Segment G [0] Indirect 0 7 8 9 10 11 12 13 14 15 1 0 0 G-Relative Addressing Mode 0 0 0 1 0 1 1 G [11] 1037 Displacement G [1037] VST277.
TNS Execution Modes Byte Addressing in the Data Segment Byte Addressing in the Data Segment Two bytes can be stored in a 16-bit word. The most significant byte in a word occupies the left half (bits 0 through 7), and the least significant byte occupies the right half (bits 8 through 15). Memory reference instructions always specify a TNS-word displacement for direct addressing, including those used for byte addressing (LDB, STB, LBP).
TNS Execution Modes Byte Addressing in the Data Segment In the example shown in Figure 6-14, indirect addressing is used to get a byte address. The (word) displacement value is 2, which means that the address is in G[2]. In this case, G[2] contains the value 12345, which is a byte address. To convert that to a word address and byte specifier, the value is divided by 2, giving a word address of 6172 with a remainder of 1. The remainder of 1 specifies the right-hand byte, as indicated in the figure.
TNS Execution Modes Indexing in the Data Segment Indexing in the Data Segment Indexing is used to reference memory locations relative to a data element in memory. A typical use is the accessing of an element in an array. Generally, indexing is done as follows. An initial address is first calculated as described in the preceding two topics (any addressing mode as well as direct, indirect, and byte addressing is permitted). This initial address is then used as a base address for indexing.
TNS Execution Modes Indexing in the Data Segment Figure 6-15.
TNS Execution Modes Examples of Indexing in the Data Segment Examples of Indexing in the Data Segment Figure 6-16 illustrates three examples of indexing in the data segment. The first shows indexing with a direct address, the second shows indexing with an indirect address, and the third shows indexing with a byte address—with indirection.
TNS Execution Modes Examples of Indexing in the Data Segment Figure 6-16. Three Examples of Indexing in the Data Segment Word: G [0] Direct, Indexed 0 Direct 1 1 0 0 0 0 0 0 1 0 G [5] 1 Displacement Index Reg . Register Stack G-Relative Addressing Mode 5 G [17] + 12 R [7] 12 Indirect, Indexed 1 1 0 G [0] 0 0 0 0 0 1 0 1 0 1234 Indirect Index Reg .
TNS Execution Modes SG Addressing Mode SG Addressing Mode For memory-reference instructions, an additional addressing mode is provided, called the SG-relative mode. This mode is provided to permit access, from the user environment, to system global data in the system data segment. This mode directly addresses the first 64 locations of the system data segment (SG[0:63]), and indirectly can address the entire 64K-word segment. Refer to Figure 6-17.
TNS Execution Modes SG Addressing Mode Figure 6-17. Direct and Indirect Examples of SG Addressing SG [0] 0 0 5 6 x Direct 1 Indirect 7 8 9 10 11 12 13 14 15 1 1 0 0 SG-Relative Addressing Mode x 1 1 0 SG-Relative Addressing Mode 0 0 1 0 0 SG [4] 1 SG [13] System Data Displacement 0 0 1 1 0 42176 Displacement SG [42176] VST282.
TNS Execution Modes Basic Characteristics of Procedures Basic Characteristics of Procedures Procedures are the fundamental building blocks of programs. They are compiled in contiguous locations in a program file, and when the program is dispatched into execution as a process, the procedures appear in a code segment of virtual memory as shown in Figure 6-18. A procedure is a functional block of instructions that, when called into execution, performs a specific operation.
TNS Execution Modes Basic Characteristics of Procedures Figure 6-18. Layout of Procedure Code in a TNS Code Segment TNS Code Segment C [0] Address of A Address of B Address of C Address of D Procedure Entry Point (PEP) Table Address of Z Procedure A Procedure B Procedure C Procedure D Procedure Z Unassigned Addresses Address of XD Address of XC Address of XB Address of XA External Entry Point (XEP) Table Page Boundary Unallocated Space C [65535] End of Code Segment VST283.
TNS Execution Modes Procedure Attributes Procedure Attributes Some procedures use privileged instructions in performing certain operations. Those procedures can switch the processor into privileged mode (and thus be able to execute the privileged instructions) only if they have the required procedure attribute. Every procedure has one of the following attributes: Nonprivileged Procedures having this attribute can be called by any procedure.
TNS Execution Modes Procedure Attributes Figure 6-19. Procedure Entry Points Are Grouped by Attribute in the PEP Table C [0] C [1] C [2] . . . PEP table address of first callable procedure PEP table address of first privileged procedure Entry points of nonprivileged procedures Entry points of callable procedures PEP Table Entry points of privileged procedures VST284.
TNS Execution Modes Defining the Procedure’s Data Defining the Procedure’s Data As previously explained, the first half of the user data segment contains the process’s global variables and TNS user data stack. The left part of Figure 6-20 illustrates the overall organization of the user data segment. Variables in the global data area are addressable by any instruction in the TNS procedure.
TNS Execution Modes Defining the Procedure’s Data Figure 6-20. Procedure Data Consists of Global Areas and Stack Frame User Data Segment G [0] Primary Global Area Secondary Global Area TNS User Data Stack Area Main procedure's stack frame TNS User Data Stack Calling procedure's stack frame S G [32768] L Register Current procedure's stack frame Second half of user data segment S Register Currently unused space for stack expansion G [65535] VST285.
TNS Execution Modes Data Segment Addressing Modes Data Segment Addressing Modes All direct addressing in the data segment is relative to one of the three addressing bases: G, L, or S. Memory reference instructions for data contain a 9-bit address field for specifying one of the three addressing bases and a relative displacement from that base. Four addressing modes are provided for addressing relative to these bases.
TNS Execution Modes Data Segment Addressing Modes Figure 6-21.
TNS Execution Modes Operations at the Procedure’s Top-of-Stack Operations at the Procedure’s Top-of-Stack The top-of-stack area can be addressed implicitly through use of the PUSH and POP instructions. Implicit addressing means that it is not necessary to specify a mode or a register. The S register is implied by both instructions; all operations take place at the top of the memory stack. A word count is used rather than a displacement value.
TNS Execution Modes Operations at the Procedure’s Top-of-Stack Figure 6-22. PUSH and POP Instructions Add and Delete Stack Elements Adding elements to the top-of-stack (S increases) Register Stack PUSH 777 1 2 3 4 5 6 7 8 158 G [158] S Register 166 S [0] 1 2 3 4 5 6 7 8 G [166] G [158] Deleting elements from the top-of-stack (S decreases) Register Stack POP 333 5 6 7 8 . . . S Register 162 S [0] 166 1 2 3 4 5 6 7 8 G [162] Undefined After POP VST287.
TNS Execution Modes Overview of Procedure Call and Exit Overview of Procedure Call and Exit Procedures are invoked using procedure call instructions—PCAL to a procedure within the same code segment, XCAL to a procedure in some other code segment, or DPCL to an indirectly specified target procedure. An example of a procedure call and exit is shown in Figure 6-23. This example assumes the called procedure is in the same segment as the caller, UC.2; therefore, the PCAL instruction is used.
TNS Execution Modes Overview of Procedure Call and Exit Figure 6-23. Example of a Procedure Call and Exit Code Segment (UC.2) Data Segment 401 C [4] Procedure A • • • PCAL 4 PEP Top-of-stack at time of call to procedure B C [272] 272 • • • 272 P Register C[401] 401 Procedure B P Register • • • EXIT 2 P ENV L Stack marker used to save and restore caller's (procedure A's) environment VST288.
TNS Execution Modes Actions of the PCAL Instruction Actions of the PCAL Instruction The following steps are performed when a Procedure Call (PCAL) instruction is executed. The step numbers refer to Figure 6-24. Note that before PCAL executes, the program must push the procedure parameters (and the mask word or words, for procedures with a variable number of parameters) onto the memory stack. 1.
TNS Execution Modes Actions of the PCAL Instruction Figure 6-24.
TNS Execution Modes Actions of the EXIT Instruction Actions of the EXIT Instruction The EXIT instruction uses the three-word stack marker to restore the caller’s environment. The sequence is as follows, with reference to Figure 6-25. (For simplicity, and continuity with the preceding PCAL description, this sequence assumes the return is from a procedure that was called with PCAL rather than XCAL.) 1.
TNS Execution Modes Actions of the EXIT Instruction Figure 6-25.
TNS Execution Modes A Procedure’s Local Variables A Procedure’s Local Variables Unlike the global data area, which exists at all times during the life of the process, the local data area for a procedure exists only during the time between the procedure’s being called and its exiting. One of the subdivisions of the local data area is used specifically for local variables. These are found in a certain number of locations (up to 127) immediately succeeding the stack marker.
TNS Execution Modes A Procedure’s Local Variables Following the generation of the local variables, this area consists of: L[1] L[2] L[3] L[4:35] = = = = i j (initialized with a value of 5) an address pointer to the array "k" the array "k" Once allocated, data in the local area is addressed relative to the current L register setting using the L-plus-relative addressing mode.
TNS Execution Modes Passing Parameters to a Called Procedure Passing Parameters to a Called Procedure Parameters are passed to a procedure in the top-of-stack area (memory stack). Naturally, there must be coordination between the caller and the called procedure when passing parameters. The caller must know the order in which a procedure expects parameters, and whether a parameter is to be an actual operand (called a value parameter) or an address pointer (called a reference parameter).
TNS Execution Modes Passing Parameters to a Called Procedure Figure 6-27. Example of Passing Parameters to a Called Procedure Data Segment L [1] L [2] 5 124 5 124 G [159] G [160] S Register Before PUSH Register Stack 0 LOAD L + 002 1 LADR L + 001 RP After LADR 5 G [124] G [125] 158 PUSH 711 S Register After PUSH 160 RP After PUSH 7 HP NonStop S-Series Server Description Manual—520331-004 6-49 VST292.
TNS Execution Modes Accessing Parameters in the Called Procedure Accessing Parameters in the Called Procedure Procedure parameters are accessed by using the L-minus-relative addressing mode. This mode provides access to the 32 locations just below and including the current L register setting (L[–31:0]). Subtracting the three words used for the stack marker, this leaves 29 words that can be directly addressed as parameters.
TNS Execution Modes Accessing Parameters in the Called Procedure Figure 6-28.
TNS Execution Modes Saving the Stack Frame on a Call Saving the Stack Frame on a Call When a procedure is called, a new stack frame is defined. This occurs because the address contained in the L register advances to point above the current local area (the caller’s local area is then inaccessible by direct addressing).
TNS Execution Modes Saving the Stack Frame on a Call Figure 6-29. Sequence of Events for Saving a Stack Frame 1 Initially (program starts) 2 G [0] Procedure A generates its local variables. Global Data L Register L Register 123 0 123 G [123] G [123] S Register 123 S Register A's Loca l Dat a G [158] 158 3 Procedure A puts parameters on the stack in preparation for calling B. 4 Procedure A calls procedure B.
TNS Execution Modes Restoring a Stack Frame on Return From a Call Restoring a Stack Frame on Return From a Call A called procedure assumes full control of the process’s memory stack, accumulating and using the data in its own stack frame. When that procedure completes its operations and exits, the stack frame it was using is no longer needed and so is deleted.
TNS Execution Modes Restoring a Stack Frame on Return From a Call Figure 6-30. Sequence of Events for Restoring a Stack Frame 5 Procedure B generates its local variables. 6 Procedure B exits back to A. L Register 123 A's Local Data S Register 158 163 P1 P2 Stack Marker 123 S Register B's Local Data L Register 217 G [123] A's A's Loca Local l Dat Data a G [158] 163 – 5 = 158 G [163] G [217] VST295.
TNS Execution Modes Multiple Markers for Nested Calls Multiple Markers for Nested Calls In examples shown previously, only one procedure call occurred and, therefore, only one stack marker was generated. However, in practice, there can be several stack markers (and stack frames) present in a memory stack at once. This occurs when a called procedure calls another procedure and that procedure calls still another procedure, and so on.
TNS Execution Modes Multiple Markers for Nested Calls Figure 6-31.
TNS Execution Modes Returning a Value to the Caller Returning a Value to the Caller A function procedure can return a value back to its caller using the top of the register stack. This, like parameter passing, requires coordination between the caller and the called procedure. That is, the calling procedure must know the number of words constituting the return value. This topic and the following one describe an example of a procedure, named “f”, that returns a value, and the instructions used to do so.
TNS Execution Modes Returning a Value to the Caller Figure 6-32. Example of Returning a Value to the Caller of a Procedure Instructions in the Procedure F LOAD L –003 LOAD L –003 0 1 5 5 Data known to calling procedure 5 Stack Marker IMPY EXIT 4 0 L [–3] L [0] 25 VST297.
TNS Execution Modes Retrieving a Returned Value Retrieving a Returned Value The preceding topic described a function procedure that is capable of returning a value to a caller. This topic describes the overall sequence of using that procedure in the context of a call and return. Refer to Figure 6-33.
TNS Execution Modes Retrieving a Returned Value Figure 6-33.
TNS Execution Modes Subprocedure Calls Subprocedure Calls A procedure itself can contain one or more subprocedures. The following table summarizes the differences and similarities between procedures and subprocedures.
TNS Execution Modes Subprocedure Calls Figure 6-34.
TNS Execution Modes Calling External Procedures Calling External Procedures Procedures in another code segment can be called almost as efficiently as the current segment’s own procedures. Two important features that make this possible are the space ID (identification) convention and the XCAL (External Procedure Call) instruction.
TNS Execution Modes Calling External Procedures The next topic illustrates an example of the operations involved in an external procedure call. Figure 6-35. Saved Copy of the Environment Register Preserves Space ID Index 4 5 6 7 8 9 LS Priv DS CS T K 10 11 12 13 14 15 V Space ID Index VST300.
TNS Execution Modes Example of an External Procedure Call Example of an External Procedure Call In this example, procedure Z in user code calls a READ procedure in system code. The XCAL instruction that implements this call refers to an external entry point table in its own segment and a procedure entry point table in the segment that contains the called procedure. These references provide the entry point address.
TNS Execution Modes Example of an External Procedure Call Figure 6-36. Sequence of Events for an External Procedure Call User Code Procedure Entry Point (PEP) Table XEP Entry G [0] User Data 0 1 2 6 7 15 CS LS Index PEP No. Z's Local Data Procedure Z . . . CALL READ (...) XCAL 2 Parameters to READ C [4075] . . .
TNS Execution Modes Resolving Virtual Addresses for External Calls Resolving Virtual Addresses for External Calls The preceding few topics assume that a P-register address is all that is needed to identify the entry point of a procedure in memory. However, that is simply a word address that is relative to the start of some TNS code segment; it does not tell you where that address is in virtual memory.
TNS Execution Modes Resolving Virtual Addresses for External Calls Figure 6-37. Example of Resolving a Virtual Address in User Code Space Pages %h 70000000 %h 20000 Base Address of Code Space PEP code code code XEP PEP code code %h 20000 XEP PEP code code code code %h 70000000 + %h 2(20000) + %h 2100 70042100 XEP PEP code code code %h 2100 XEP Byte Segment 0 0 1 2 3 0 Segment 1 1 2 0 Segment 2 1 2 3 4 0 Segment 3 1 2 3 0 Offset P Register (%10200) VST302.
TNS Execution Modes An Accelerated Program File in Virtual Memory An Accelerated Program File in Virtual Memory An accelerated program file, when it is allocated space in absolute virtual memory as an executable process, occupies some number of consecutive absolute segments in the Kseg2 part of the privileged space. That is illustrated on the right side of Figure 6-38.
TNS Execution Modes An Accelerated Program File in Virtual Memory Figure 6-38.
TNS Execution Modes Execution Mode Switches Execution Mode Switches Although one might expect a TNS code file to execute exclusively in the TNS execution mode and an accelerated code file to execute exclusively in the accelerated execution mode, there are occasions for temporary switches to the opposite mode. Two of the main reasons for such switches are illustrated in Figure 6-39. The first case, shown on the left, involves a process that uses a code file that was never accelerated.
TNS Execution Modes Execution Mode Switches Figure 6-39. Switching Modes for System Calls and Translation Assistance Process User Code (TNS) Process System Code (Accelerated) User Code (Accelerated) TNS Instructions TNS Instructions RISC Instructions RISC Instructions VST304.
TNS Execution Modes Procedure Return in Accelerated Code Procedure Return in Accelerated Code Besides actual mode switches, as described in the preceding topic, there are other times when an accelerated program needs access to TNS information. One important example is the return from any procedure call. In this case, what is needed is the address derived by the EXIT instruction from the stack marker, rather than the next RISC instruction.
TNS Execution Modes Procedure Return in Accelerated Code the return point from the stack marker. (4) Using that P value, the corresponding RISC address is found in the Pmap table. (5) EXIT performs a jump to that address. Figure 6-40. Accelerated Procedure Return Requires Access to TNS Information TNS Code Process RISC Code Jump PCAL Pmap 1 5 Procedure N 5 Procedure N TNS P 4 3 1 RISC PC 4 2 Stack Marker EXIT P ENV L Jump 3 2 Millicode (EXIT) VST305.
TNS Execution Modes Mapping Return Addresses and Debug Points Mapping Return Addresses and Debug Points The purpose of the Pmap table is to map TNS P addresses in a given TNS code segment of an accelerated code file to corresponding RISC PC addresses. In theory, that could result in a large table (64K words, or 256 KB, for each TNS code segment). In addition, two tables are really needed: one to map return addresses for procedure returns and one to map debug points.
TNS Execution Modes Mapping Return Addresses and Debug Points Figure 6-41.
TNS Execution Modes Gateway Tables Gateway Tables When a process that is operating in TNS mode calls a CALLABLE system procedure, there is necessarily a transition to privileged mode. In the case of programs that use TNS mode, such a transition to privileged mode takes place in the millicode for the calling instruction (XCAL, PCAL, or DPCL).
TNS Execution Modes Gateway Tables Figure 6-42. Gateway Tables Provide Privileged-Mode Transitions for Accelerated Code System Library (SL) Code TNS Code Accelerated Code Accelerated User Code READ Procedure jal READ lb j lb j lb j lb j (OPEN) Gateway Table (READ) VST307.
TNS Execution Modes Far Jump Tables Far Jump Tables In computing a 32-bit PC address from the 26-bit target field of a RISC jump instruction, the RISC processor takes the four high-order bits from the current program counter value. That fact results in 16 possible direct jump areas in the 4-GB virtual address space, each being 256 megabytes. Most process code (UC, UL, and SL), as well as the interpreter and nonprivileged instruction set millicode, are in the last direct jump area of user space.
TNS Execution Modes Far Jump Tables Figure 6-43. Far Jump Tables Are Needed for Calls To and From System Code System Library (SL) Code System Code (SC) Accelerated User Code Procedure A (Nonprivileged) Procedure C (Privileged, Resident) jal C jal A Procedure B (Callable) jal B Procedure D (Callable, Resident) jal D lui : : jal B FJ jr lb GW J lb lui : jr FJ GW + FJ FJ lui : jr FJ FJ VST308.
TNS Execution Modes Maintaining TNS State Values Maintaining TNS State Values The 32 general-purpose registers used by the RISC processor are numbered $0 through $31. $0 is hardwired to contain the value 0 and so is not considered in usage assignments. Many of the registers are used by millicode or accelerated code for expression evaluation, parameter passing, and so on. Those that are used to maintain TNS state information fall in the range $14 through $30, as shown in Figure 6-44.
TNS Execution Modes Maintaining TNS State Values byte address) forms of the S and L pointers to the TNS data stack. Because the TNS stack is in segment 0 of region 0, these addresses can be converted to 16-bit word addresses with a one-bit shift. The registers are designated SX and LX. Figure 6-44. Most TNS State Values Are Kept in RISC General-Purpose Registers General-Purpose RISC Registers Executing Interpreter Millicode Carry K Condition Code (CC) RP Wrap Base Current Code Seg.
TNS Execution Modes Invoking Privilege for CALLABLE Procedures Invoking Privilege for CALLABLE Procedures Unlike TNS processors (CISC-based), which invoke privilege in the microcode of the calling instruction, RISC-based processors such as NonStop S-series processors, always go through a sequence of events involving an exception to set the privileged state.
TNS Execution Modes Invoking Privilege for CALLABLE Procedures Figure 6-45.
TNS Execution Modes Invoking Privilege for CALLABLE Procedures HP NonStop S-Series Server Description Manual—520331-004 6-86
7 Native Execution Mode The topics in this section describe the basic conventions for native-mode execution. The following topics are described.
Native Execution Mode Native Mode Uses RISC Register Conventions Native Mode Uses RISC Register Conventions The NonStop S-series architecture uses the RISC registers in the way that they are defined for the RISC internal architecture. All 32 general-purpose registers, designated GPR[0..31] or $0..$31, are used as assigned in the RISC documentation. The following table summarizes these usages.
Native Execution Mode Native Mode Uses RISC Register Conventions %h 08007FF0. (Global data is not limited to 64 KB; with two instructions, any address in the 4-gigabyte address space can be accessed.) Up to four words or parameters can be passed to a procedure in a0 through a3, and results are returned in registers v0 and v1. Procedures save and restore registers s0 through s8 (if they are used) and return sp to its original value. Registers t0 through t9 are used for procedure temporary usage.
Native Execution Mode RISC Stack Frames RISC Stack Frames The primary stacks used by a native process (that is, the main stack and the privileged stack) use RISC stack frame conventions as illustrated in Figure 7-2. These stacks grow downward, toward smaller addresses. They both originate at the high-address end of their containing segments. (In diagrams throughout this manual, addresses are shown as increasing downward on the page.
Native Execution Mode RISC Stack Frames Figure 7-2. Stack Frames Overlap and Grow to Lower Addresses Currently Unused Space sp Stack Growth Call-Out Parameters Register-Save Area Current Stack Frame Static Local Variables vfp Increasing Addresses Call-In Parameters Caller's Stack Frame VST312.
Native Execution Mode Procedure Name Spaces for the System Library Procedure Name Spaces for the System Library The system library exists in two separate name spaces, SL and SLr. That is, a name can appear once in each space. The SL name space contains all the TNS library procedures, and the SLr name space contains all the native RISC library procedures. Most system library procedures are executed as native library procedures in the SLr name space.
Native Execution Mode Procedure Name Spaces for the System Library results if needed, reverts to accelerated mode and the TNS stack, and returns control to the TNS or accelerated code that called it. In summary, referring to Figure 7-3: an XCAL instruction in TNS mode fetches the XEP table entry for the target procedure. A DPCL instruction is presented with the XEP entry as an argument.
Native Execution Mode Example of TNS Call to a Native Library Procedure Example of TNS Call to a Native Library Procedure The example illustrated in Figure 7-4 assumes that some user code (UC) process is executing in either TNS mode or accelerated mode, using variables on the TNS stack (1). At some point in its execution the process executes an XCAL to a system library procedure (2), such as DNUMOUT. Because DNUMOUT exists as a native mode procedure, the processor must be put into native mode.
Native Execution Mode Example of TNS Call to a Native Library Procedure Figure 7-4. A TNS Call to the System Library Is Directed Through the Shell Map 00 Region TNS Stack 7C Region System Library (SLr) System Library Shells $DNUMOUT Main Stack 4 5 DNUMOUT RISC Procedure 3 1 7F Region System Tables and Millicode Shell Map 70 Region User Code (UC) Gateways TNS Procedure 2 Call to System Library VST314.
Native Execution Mode Invoking Privilege Requires Taking an Exception Invoking Privilege Requires Taking an Exception Unlike TNS processors (CISC-based), which invoke privilege in the microcode of the calling instruction, RISC-based processors, such as the NonStop S-series processors, always go through a sequence of events involving an exception to set the privileged state.
Native Execution Mode Invoking Privilege Requires Taking an Exception Figure 7-5.
Native Execution Mode Stack Switching for Native Privilege Transition Stack Switching for Native Privilege Transition If a nonprivileged process, operating in nonprivileged native mode, calls a callable procedure, the process must switch its operation from the main stack to the privileged stack. This switch is performed as part of the transition to privileged mode (discussed in Invoking Privilege Requires Taking an Exception on page 7-10). The stack switch is accomplished by these steps.
Native Execution Mode Stack Switching for Native Privilege Transition Figure 7-6. Millicode Routines Switch Between Main and Privileged Stacks Main Stack Nonprivileged Code SP(1) Parameters Active Frame 1 Exception Frame 3 (Millicode) Privilege Exception Frame 2 Enter_Priv Frame 1 3 2 Frame 0 Save Return Information Load Exit Address Set SP Privileged Stack Called Callable Procedure 5 4 SP(2) Frame of Callable Procedure 6 Parameters Exit_Priv Return (Millicode) 7 sp ra VST316.
Native Execution Mode Example of Enter_Priv Transition Example of Enter_Priv Transition Because privileged mode operation provides access to operating system elements, transitions to privileged mode by nonprivileged procedures must be restricted to callable procedures only. Transitions in the reverse direction, from privileged to nonprivileged, occur while the code is running privileged (and therefore trusted), and so this transition direction is accomplished simply by the Exit_Priv routine.
Native Execution Mode Example of Enter_Priv Transition Figure 7-7. Deliberate Invocation of Error Exception Triggers Privilege Transition Nonprivileged Native User Code 7C Region System Library (SLr) Code jal READX 1 READX Procedure Nonprivileged Accelerated User Code 4 3 $READX To-RISC Shell jal READX 1 3 Kseg2 7E Region (OPEN) SPAD Page Gateway Table (READX) 2 Load Byte $READX VST317.
Native Execution Mode Far Jumps and Far Gateways Are Needed for SCr Far Jumps and Far Gateways Are Needed for SCr In computing a 32-bit PC address from the 26-bit target field of a RISC jump instruction, the RISC processor takes the four high-order bits from the current program counter value. That fact results in 16 possible direct jump areas in the 4-GB virtual address space, each being 256 megabytes.
Native Execution Mode Far Jumps and Far Gateways Are Needed for SCr Procedure D is both callable (requiring a gateway table entry) and located in SCr (requiring a far jump table entry). Both entries are combined as a far gateway, concluding with the jump instruction that completes the jump to procedure D. Calls to D from within SCr go through a dummy gateway in SCr. Figure 7-8.
Native Execution Mode Far Jumps and Far Gateways Are Needed for SCr HP NonStop S-Series Server Description Manual—520331-004 7-18
8 Interrupt System Certain defined events can interrupt the processing of a running program. Servicing of these events is accomplished by interrupt handlers, which are not processes. This section describes how control is passed to and from the interrupt handlers.
Interrupt System Interrupt Overview Interrupt Overview Figure 8-1 is a simplified overview of the sequence by which an interrupt condition temporarily stops the execution of the current process (or possibly some other interrupt handler), executes the interrupt handler that is appropriate for the particular interrupt condition, and eventually restores control to the interrupted program code. Step 1 assumes that there is some code currently executing. In Step 2, some interrupt condition occurs.
Interrupt System Interrupt Overview Figure 8-1. An Interrupt Can Interrupt a Process or Another Interrupt Handler Processor Attention Current Process ServerNet Attention System Software Attention Current Interrupt Handler 2 1 Processor 3 Interrupt Current Code 4 Run Interrupt Handler 5 Resume Current Code Page Fault Processing Return to Interrupted Process or Interrupt Handler VST360.
Interrupt System Interrupt Sequence Interrupt Sequence Figure 8-2 expands on the simplified interrupt sequence shown in the preceding topic. This diagram separates hardware and millicode elements (top part) from the software elements (lower part). The focal point for the various categories of interrupts is the Cause register in the RISC chip. The shaded part of the Cause register represents “internal interrupts,” and the unshaded part is used for “external interrupts.” The sequence is as follows.
Interrupt System Interrupt Sequence Figure 8-2.
Interrupt System Interrupt Stack Marker Format Interrupt Stack Marker Format Beginning with the G05.00 RVU, all code is native, and therefore the process environment is saved in the register-save area. Figure 8-3 illustrates the arrangement for storing the environment only for the case of TNS code. The interrupt stack frames are allocated in the system data segment, each one corresponding to one of the interrupt handlers.
Interrupt System Interrupt Stack Marker Format Figure 8-3. The Interrupt Stack Marker Saves RISC and TNS State System Interrupt Vector Interrupt Stack Saved RISC State LXi LXi LXi LX LXi SX Space ID Mask S P E L R0 R1 R2 R3 R4 R5 R6 R7 Filled In If Not Accelerated LXi LXi Local Data of Interrupt Handler LXi VST362.
Interrupt System Transferring Control to an Interrupt Handler Transferring Control to an Interrupt Handler After the interrupted environment has been saved, as described in the preceding topic, the interrupt millicode transfers control to the interrupt handler in system software. To do this transfer, the millicode refers to a table of 32-byte items in system data called the system interrupt vector (SIV) and selects the appropriate entry. See Figure 8-4.
Interrupt System Transferring Control to an Interrupt Handler another interrupt is pending, the interrupt sequence for that interrupt begins, using its own SIV entry to set up the interrupt environment. Figure 8-4. The System Interrupt Vector Transfers Control to Software System Interrupt Vector 0 1 UCME 2 Memory Access BkPt. 3 Instruction Failure 4 Page Fault SIV Table Entry Format LXi Interrupt Stack Mi Mask 5 6 7 8 Power Fail 9 Correctable Mem.
Interrupt System Interrupt Masking Interrupt Masking Four TNS registers, simulated by exception-handling millicode, are associated with interrupts: two 16-bit interrupt registers (INTA and INTB) and two 16-bit mask registers (Mask A and Mask B). (Mask A is frequently referred to as “Mask” because it is the only one recognized by the operating system.) The bit assignments of these registers are illustrated in Figure 8-5.
Interrupt System Interrupt Masking Figure 8-5. Some Interrupts Can Be Masked by Mask Register Bits Interrupt Register Mask Register INTA Mask A 0 Uncorrectable Memory Error Memory Access Breakpoint 2 AND Sampler 3 AND Power Fail 8 AND Correctable Memory Error 9 AND Page Fault 10 11 12 13 IPC and I/O 14 AND Dispatcher 15 AND Stack Overflow Instruction Failure Instruction Breakpoint Arithmetic Overflow V T VST364.
Interrupt System TNS Interrupts TNS Interrupts The following paragraphs describe the TNS interrupts in order of their SIV numbers. Each type requires zero, one, or two parameters. Table 8-1 on page 8-14 summarizes the interrupts. Uncorrectable Memory Error (1) This interrupt occurs when a memory word is accessed by the processor and contains an error that cannot be corrected. Two parameter words are placed in the SIV entry. The first parameter word contains the physical address of the page at fault.
Interrupt System TNS Interrupts Time List (13) Every 10 milliseconds, the millicode detects an interval clock interrupt, updates the quadrupleword clock at SG[%350], and decrements the wait time of the element at the head of the time list. If the wait time has gone to zero, control passes to the time list interrupt handler; otherwise, no action is taken. There is no parameter. IPC and I/O (14) This interrupt occurs when a ServerNet interrupt requires servicing. There is no parameter.
Interrupt System TNS Interrupts Table 8-1.
9 Interprocessor Communication This section describes the hardware, software, and operating sequences by which processors in NonStop S-series servers communicate with each other. Such communication is termed interprocessor communication (IPC) and is achieved by the exchange of messages between processes. To provide transparency as to whether two communicating processes are in the same or different processors, all message traffic is managed by the message system.
Interprocessor Communication Interprocessor Protocols Interprocessor Protocols Section 2, Principles of System Operation, showed that ServerNet devices, including those associated with processors, communicate with each other by exchanging ServerNet packets and that each single exchange is a ServerNet transaction. The originating device sends a read or write request packet, and the receiving device sends back a corresponding read or write response packet.
Interprocessor Communication Interprocessor Protocols might be the file system and thus not a process at all. The processes shown are generic representations for all such cases. For convenience of reference throughout this section, the processor containing the linker process is called the linker processor and the processor containing the listener process is called the listener processor. Figure 9-1.
Interprocessor Communication Linker-Listener Protocol Linker-Listener Protocol Figure 9-2 separately shows the linker-listener protocol as if lower levels of protocol did not exist. However, it is those lower levels that actually carry out the actions shown here. The linker-listener protocol consists of a request (1) and a reply (2). Optionally, data can be included in either the request or the reply—or both or neither, depending on what the linker process wants to do.
Interprocessor Communication Linker-Listener Protocol Figure 9-2. From Linker-Listener Perspective: One Request and One Reply Request Data Linker Processor Listener Processor Request Data Reply Data Reply Data Linker Process Listener Process 1 Request Control [and Request Data] Reply Control [and Reply Data] 2 HP NonStop S-Series Server Description Manual—520331-004 9-5 VST339.
Interprocessor Communication Message System Protocol Message System Protocol When the linker and listener processes exchange messages back and forth (as described in the preceding topic), the message system adds its own protocol information to those same messages. In Figure 9-3, that added information is shown enclosed in shaded boxes in the messages; the unshaded information in the messages is exactly the same as shown in Figure 9-2.
Interprocessor Communication Message System Protocol Figure 9-3.
Interprocessor Communication Message Transfer Mechanisms Message Transfer Mechanisms Referring back to Figure 9-1 on page 9-3, which showed the four levels of protocol that are involved in interprocessor communication, three have at this point been described. The ServerNet hardware protocol was covered in Section 2, Principles of System Operation, and the linker-listener and message system protocols were covered in the preceding two topics.
Interprocessor Communication Message Transfer Mechanisms When the remote processor sends an interrupt packet (such as to signify the end of a transfer), the packet is placed in the interrupt queue (12) for processing by different levels of exception and interrupt logic (13), and the message system stores the information in an MQC (14). Figure 9-4.
Interprocessor Communication Message Transfer Methods Message Transfer Methods Message System Protocol on page 9-6 shows that different kinds of transfers can use different combinations of mechanisms. Sometimes the target processor of a message can reverse roles to pull data from the originator of the message, and the request data can be handled different ways depending on the length of the data. The upper part of Figure 9-5 tabulates the three basic phases that are used as a basis for succeeding figures.
Interprocessor Communication Message Transfer Methods Figure 9-5. Message Transfers Use Three Phases and Two Transfer Methods Request Reply Acknowledge Reply Short-Length Data and Control Medium-Length Data and Control Long-Length Data and Control Acknowledge Request Pre-Push Transfer Setup Packet Data Packets Control Packets Receiving Processor Sending Processor Post-Pull Transfer 1 Setup Packet 2 Data Packets Control Packets VST342.
Interprocessor Communication Request With Short Request Data Request With Short Request Data A request phase that includes short-length request data (Figure 9-6) makes temporary use of pre-push buffers to transfer data from a linker’s buffer to a listener’s buffer. This transfer method is used when the total length of control information and data does not exceed the size of a pre-push buffer, currently 1920 bytes.
Interprocessor Communication Request With Short Request Data Figure 9-6. For Request With Short Data, Listener Pre-Pushes Data Linker Processor Send Request Req Control Req Setup Listener Processor First Third ReadLink Cache MQC 3 BTE BTE 7 Request Data Pre-Push Buffer Second BTE Descriptors 2 AVT 1 4 TIB 5 Int Queue Linker Processor Store Control and Data 6 AVT Listener Processor Req Control MQC BTE BTE 8 9 AVT Request Data AVT VST344.
Interprocessor Communication Request With Medium Request Data Request With Medium Request Data When the combination of request control and data is too big to fit in the pre-push buffers but small enough to fit in a readlink cache buffer (Figure 9-7), the message system eliminates use of the pre-push buffers (shown in Figure 9-6 on page 9-13).
Interprocessor Communication Request With Medium Request Data Figure 9-7.
Interprocessor Communication Request With Long Request Data Request With Long Request Data When the combination of request control and data is too big to fit in either the pre-push buffers or the readlink cache, the message system eliminates use of both of these elements and instead pulls the data directly to the listener’s buffer. This operation is shown in Figure 9-8. In the first part of this phase (upper part of Figure 9-8), only the setup information is sent from the linker to the listener.
Interprocessor Communication Request With Long Request Data Figure 9-8.
Interprocessor Communication Reply Data and Reply Acknowledgement Reply Data and Reply Acknowledgement Every time a listener receives a request, whether short, medium, or long, it must respond with a reply. That reponse occurs in a reply phase, which may or may not necessarily include data. But whether or not reply data is included with the reply, the linker, after it receives the reply, must respond with an acknowledgment.
Interprocessor Communication Reply Data and Reply Acknowledgement Figure 9-9. For All Read Requests, Listener Pre-Pushes Data in Reply Phase Linker Processor Listener Processor Reply 4 BTE Reply Ctrl BTE First Third 2 Reply Ctrl Reply Setup 5 Reply Data BTE Descriptors Reply Setup AVT AVT 3 Linker Processor Reply Data 1 TIB Int Queue 6 Second Listener Processor Acknowledge Reply BTE BTE BTE Descriptors 8 Reply Data Reply 10 Acknowledge AVT 7 TIB AVT 9 Int Queue VST343.
Interprocessor Communication Reply Data and Reply Acknowledgement HP NonStop S-Series Server Description Manual—520331-004 9-20
10 Input/Output Operations This section describes the operating sequences by which processors in NonStop S-series servers transfer data to and from input/output devices. Before reading this section, you should have read Section 2, Principles of System Operation, for a basic understanding of ServerNet transactions and ServerNet packets. ServerNet transactions (request and response) form the basis for all input and output operations through the ServerNet fabrics.
Input/Output Operations Storage and Communications I/O Compared Storage and Communications I/O Compared Figure 10-1 illustrates the basic similarities and differences between storage I/O and communications I/O. Both modes of operation transfer information through the ServerNet hardware whenever data needs to be exchanged between a processor and a controller.
Input/Output Operations Storage and Communications I/O Compared Figure 10-1.
Input/Output Operations Overview of the I/O System Overview of the I/O System Figure 10-2 expands upon information presented in Section 1, Introduction. (See Figure 1-8 on page 1-15.) In this figure, those components that make up the ServerNet hardware are highlighted in the central part of the illustration. These details are mostly eliminated in succeeding illustrations for the sake of simplicity.
Input/Output Operations Overview of the I/O System Figure 10-2. ServerNet Hardware Bridges Controllers to I/O Software Processor Processor Application Application I/O Software Layers I/O Software Layers ServerNet Services ServerNet Services Processor ServerNet Interface Processor ServerNet Interface Multifunction I/O Board Multifunction I/O Board X SBI Comm. Ctlr ServerNet Hardware SCSI Ctlr ServerNet Adapters SBI SBI Comm. Ctlr Comm. Ctlr Y SBI Comm.
Input/Output Operations Layers of I/O Components Layers of I/O Components Figure 10-3 illustrates the various software and hardware levels of I/O control that accomplish input/output transfers, with storage I/O illustrated on the left and communications I/O illustrated on the right. The most significant difference between these two types of I/O is the location of the request queues.
Input/Output Operations Layers of I/O Components The “ServerNet Addressable Controllers” layer is the lowest level of the I/O architecture, carrying out the actual transfer of data across the ServerNet hardware, and providing the interface to the hardware I/O devices. Figure 10-3.
Input/Output Operations I/O Process Models for Storage I/O I/O Process Models for Storage I/O Figure 10-4 shows two I/O process models. Both models use the conventional process-pair arrangement of I/O processes that is used in all NonStop servers, including those prior to the NonStop S-series servers. Those earlier servers, however, required the I/O process and its backup to be in the two processors which interfaced to the two I/O buses that connected to the relevant I/O controllers.
Input/Output Operations I/O Process Models for Storage I/O Figure 10-4. Alternative Storage I/O Models Provide Backward Compatibility Standard I/O Storage Model A B C Client D Client Client Client Data Data Data Data Data Backup IOP IOP Controller Direct Bulk I/O Transfer Model A B C D Client Data I/O Process 1 Backup I/O Process 2 5 3 4 Controller VST350.
Input/Output Operations Storage Operation Queuing Storage Operation Queuing As mentioned previously, it is the module driver that takes generalized I/O requests and formulates specific commands for driving I/O devices. Figure 10-5 shows a closeup view of how such commands are queued and delivered to the controllers. As shown in Figure 10-5, request queues are located in two places, both on the same I/O board: either a ServerNet adapter or a multifunction I/O board (MFIOB).
Input/Output Operations Storage Operation Queuing Figure 10-5.
Input/Output Operations Packaging and Delivery of Storage Commands Packaging and Delivery of Storage Commands A command entry (CE) in a request queue defines an I/O operation to be executed by the controller firmware. Each such entry is 64 bytes in size, the maximum size that can be conveyed in ServerNet packets. Figure 10-6 shows how these commands are transmitted to a particular storage I/O device. The example shown assumes that the device is a SCSI device.
Input/Output Operations Packaging and Delivery of Storage Commands Figure 10-6.
Input/Output Operations Storage Read Request Processing Storage Read Request Processing When an I/O process in a processor requests a read from a storage device, the only action that the processor initiates is to send the command to the controller. Thereafter, it is the responsibility of the controller to transfer the data, pushing the data to the processor as if the controller is the originator of the request. The resultant sequence consists of three phases, illustrated in Figure 10-7.
Input/Output Operations Storage Read Request Processing Figure 10-7.
Input/Output Operations Storage Write Request Processing Storage Write Request Processing When an I/O process in a processor requests a write to a storage device, the only action that the processor initiates is to send the command to the controller. Thereafter, it is the responsibility of the controller to transfer the data, pulling the data to itself as if the controller is the originator of the request. The resultant sequence consists of three phases, illustrated in Figure 10-8.
Input/Output Operations Storage Write Request Processing Figure 10-8.
Input/Output Operations Communications Operation Queuing Communications Operation Queuing CThe remaining topics in this section describe communications I/O. The descriptions assume that you have read the first three topics in this section, which describe the basic differences between storage I/O and communications I/O. As illustrated earlier in Figure 10-3 on page 10-7, communications I/O uses work queues (NIOC queues) that are located in processor memory.
Input/Output Operations Communications Operation Queuing Figure 10-9. Communications Controllers Use Work Queues That Are in Processor Memory Work Queues Data Buffers Queue Services DMA Data Transfer ServerNet Services Processor ServerNet Interface Processor ServerNet Hardware ServerNet Adapter ServerNet Bus Interface DMA Data Transfer ServerNet Addressable Controller Controller Firmware Controller Memory VST355.
Input/Output Operations Application of Communications Queues Application of Communications Queues Figure 10-10 illustrates the typical application of communications work queues. Note that the direction of the arrows indicates which entity (controller or communications monitor) writes to a given queue, and which entity reads from that queue.
Input/Output Operations Application of Communications Queues Figure 10-10.
Input/Output Operations Typical Use of Queue Pairs Typical Use of Queue Pairs Figure 10-11 illustrates the typical way in which pairs of queues work. The illustration is applicable to both transmission from the processor (TX) and reception by the processor (RX). However, the application differs in the TX and RX cases, so they are described separately in the following paragraphs. Be aware that all manipulation of the queues is accomplished by calls to queue services.
Input/Output Operations Typical Use of Queue Pairs address. When the module driver reads this entry (4), it notifies the appropriate client, and the operation is completed. Queue services advances the read pointer to eliminate the xx entry. Figure 10-11. Monitor Writes in Outbound Queues, Module Driver Writes in Inbound Queues Outbound: Inbound: TX Command Queue or RX Buffers Queue TX Completion Queue or RX Indication Queue 1. Write x (Module Driver’s) Read (Controller’s) 2. Read x Write 3.
Input/Output Operations Actions for Empty or Full Queues Actions for Empty or Full Queues In all of the actions described in the preceding topic, the read pointer is essentially chasing the write pointer. That is, the writer of entries into a queue is adding new entries to the head of the queue at some unpredictable, irregular rate, and the reader of those entries is acting upon the entries at the tail of the queue, trying to catch up to the most recently added entry.
Input/Output Operations Actions for Empty or Full Queues Figure 10-12. Empty Queue Requires Wakeup Prod, Full Queue Requires Full Notice Queue Condition Next Action Queue Empty Write Read When Write pointer advances, send Wakeup Prod to reader. Queue Full Read Write Send Full Notice to prevent further writes. Reading continues until Low-Water Mark is reached. Low-Water Mark Write Writes may resume. Read Low-Water Mark VST358.
Input/Output Operations Communications Request Processing Communications Request Processing As stated back in the first topic of this section, transfers that are inbound to the host server originate externally by some request from a workstation that is part of an external network. Transfers that are outbound from the host server typically provide information or control from some service in the NonStop processor.
Input/Output Operations Communications Request Processing Note that the bus transfer engine (BTE) is not involved in any of these operations, because none of the work originates in the processor. Figure 10-13.
Input/Output Operations Communications Request Processing HP NonStop S-Series Server Description Manual—520331-004 10-28
11 TNS Instruction Set The TNS instruction set of the NonStop S-series processor consists of approximately 280 machine instructions. This section provides text descriptions of these instructions, with the exception of a few that are reserved for operating system use. Diagrams are also included showing the action of some of the more commonly used instructions.
TNS Instruction Set Memory Addressing Instructions Memory Addressing Instructions Figure 11-1 shows the instruction word format for memory data reference instructions that refer to single-length (16-bit) operands. There are ten such instructions: LDX, NSTO, LOAD, STOR, LDB, STB, LDD, STD, LADR, and ADM. For both the single-length and doubleword formats, bit 7 begins the mode and displacement field. The 9-bit field of I.<7:15> provides different displacement ranges depending on the mode selected.
TNS Instruction Set Memory Addressing Instructions Figure 11-2 illustrates the addressing methods for the doubleword instructions LDD and STD. The upper example illustrates LDD (Load Doubleword) with direct addressing and no indexing. The lower example illustrates LDD with indirect addressing and indexing. Figure 11-2.
TNS Instruction Set Immediate Operand and Shift Instructions Immediate Operand and Shift Instructions Figure 11-3 illustrates the general instruction word format for instructions that use immediate operands. Immediate operand instructions operate on stack registers. The first example shows how an 8-bit immediate value is extended to a 16-bit value for comparison purposes. The second example shows the result of a load-left operation; the sign is extended into the right eight bits. Figure 11-3.
TNS Instruction Set Immediate Operand and Shift Instructions Figure 11-4 presents a comparison of logical (unsigned) shifts and arithmetic (signed) shifts. In arithmetic left shifts, the sign bit is unaffected (except in accelerated mode); in logical left shifts, the sign bit participates in the shift. In arithmetic right shifts, the sign bit is propagated to the right; in logical right shifts, vacated positions are filled with zeros. Figure 11-4.
TNS Instruction Set Boolean Instructions Operate on Stack Registers Boolean Instructions Operate on Stack Registers Figure 11-5 shows examples of the four basic Boolean instructions: LAND, LOR, XOR, and NOT. In these examples of Boolean operations, both operands are on the top of the register stack. The instructions delete the operands and leave the result on the register stack, in A. Figure 11-5.
TNS Instruction Set Boolean Instructions Operate on Stack Registers Similarly, Figure 11-6 shows examples of the four Boolean instructions that use immediate operands: ORRI, ORLI, ANRI, and ANLI. These examples show how the 8-bit or 9-bit immediate operand is expanded to a 16-bit operand for the four immediate Boolean instructions. Only the immediate operand is shown here (operand 1); the second operand is in A on the register stack. Figure 11-6.
TNS Instruction Set Move, Compare, and Scan Instructions Move, Compare, and Scan Instructions One bit in the instruction word format of nonextended memory-to-memory move, compare, and scan instructions specifies an ascending order or descending order of addresses used for the source and destination of the moved data. Starting addresses for the destination and the source are specified in the register stack, as well as the count of elements to be moved.
TNS Instruction Set Move, Compare, and Scan Instructions Figure 11-7. Moves Can Be Ascending or Descending 9 RL Right-Left Indicator 0 = Left-to-right (ascending addresses) 1 = Right-to-left (descending addresses) Direction = 0 (ascending) Register Stack C B A Destination Destination Source Count Count Elements Source Direction = 1 (descending) Destination Count Elements Register Stack C B A Destination Source Count Source VST325.
TNS Instruction Set Definitions of TNS Instructions Definitions of TNS Instructions The instruction definitions given on this and the following pages are listed in alphabetical order to facilitate quick reference. A listing by general category is provided in Table A-2 on page A-9. Unless otherwise stated, “stack” refers to the register stack. ADAR (00016-). Add A to a Register. A is added in signed integer form to the register pointed to by the Register field of the instruction.
TNS Instruction Set Definitions of TNS Instructions ANG (000044). AND to Memory. The word in B is logically ANDed to a word in the current data segment that is specified by a 16-bit address in A. The result remains in the data segment location, and A and B are deleted from the stack. Condition Code is set. ANLI (007---). AND Left Immediate Operand With A.
TNS Instruction Set Definitions of TNS Instructions through the location specified by P + A. Figure 11-8 illustrates the action of the BFI instruction. Both examples of BFI in Figure 11-8 use the same branch list. In the first example, A is 0, so the first item in the list is used as the offset from P. In the second example, A is 3, so the fourth item in the list is used. Figure 11-8.
TNS Instruction Set Definitions of TNS Instructions BGEQ (-13---). Branch if CC Is Greater or Equal. If the Condition Code in the ENV register is CCG or CCE (N = 0), a direct or indirect branch is taken (depending on the “i” field of the instruction). If the condition is not met, the next instruction is executed. For binary coding details, refer to Table B-4 on page B-4. BGTR (-11---). Branch if CC Is Greater.
TNS Instruction Set Definitions of TNS Instructions the BPT instruction is executed, a Debug trap occurs when the BPT instruction is reached. When Debug has completed processing the breakpoint event, it can resume process execution at that interrupted point. Debug can leave the BPT instruction in place or it can have replaced it with the original contents of that location.
TNS Instruction Set Definitions of TNS Instructions CDF (000306). Convert Double to Floating. The doubleword signed integer in BA is converted to a floating-point quantity in BA, with truncation if the result exceeds 23 significant bits. CDFR (000326). Convert Double to Floating, Rounded. The doubleword signed integer in BA is converted to a floating-point quantity in BA, with rounding if the result exceeds 23 significant bits. CDG (000366). Count Duplicate Words.
TNS Instruction Set Definitions of TNS Instructions CEFR (000277). Convert Extended to Floating, Rounded. The four-word floating-point quantity in DCBA is converted to a two-word floating-point quantity. The new quantity is rounded according to the contents of truncated bit 7 of C. DCBA is deleted, and the two-word result is pushed onto the stack. CEI (000337). Convert Extended to Integer. The extended floating-point quantity in DCBA is converted to a single-word signed integer.
TNS Instruction Set Definitions of TNS Instructions CFQ (000320). Convert Floating to Quadruple. The floating-point quantity in BA is converted to a quadrupleword integer in DCBA. Overflow is set if the value of the operand was greater than 263–1 or less than –263. Condition Code is set on the result. CFQR (000321). Convert Floating to Quadruple, Rounded.
TNS Instruction Set Definitions of TNS Instructions source byte address, and C to contain a destination byte address. The source and destination segments to be used are specified by the “S” and “D” fields of the instruction and by the DS, CS, and LS, bits of the ENV register. If the source address is specified as current code segment, the byte address is taken to be in the same 64K half of the code space as the current P register value.
TNS Instruction Set Definitions of TNS Instructions CQE (000336). Convert Quadruple to Extended. The quadrupleword signed integer in DCBA is converted to an extended floating-point quantity in DCBA, with truncation if the result exceeds 55 significant bits. CQER (000335). Convert Quadruple to Extended, Rounded. The quadrupleword signed integer in DCBA is converted to an extended floating-point quantity in DCBA, with rounding if the result exceeds 55 significant bits. CQF (000324).
TNS Instruction Set Definitions of TNS Instructions DCMP (000225). Double Compare DC With BA. The Condition Code in the ENV register is set as a result of the doubleword integer comparison of DC and BA. Both operands are then deleted from the stack. DDIV (000223). Double Divide DC by BA. The doubleword integer contained in DC is divided in doubleword integer form by the doubleword integer in BA. Both operands are then deleted, and the result is pushed onto the stack.
TNS Instruction Set Definitions of TNS Instructions less than 0 give undefined results. Condition Code is set. Refer to Figure 11-4 on page 11-5 for a comparison of logical (unsigned) shifts and arithmetic (signed) shifts. DMPY (000222). Double Multiply DC by BA. The doubleword integer contained in DC is multiplied in doubleword integer form by the doubleword integer in BA. Both operands are then deleted, and the result is pushed onto the stack.
TNS Instruction Set Definitions of TNS Instructions Figure 11-9. Example of Depositing a Field Using the DPF Instruction INT i : % 023003 i.
TNS Instruction Set Definitions of TNS Instructions the result falls outside the range of extended floating-point numbers. Condition Code is set on the result. EMPY (000302). Extended Multiply. The extended floating-point quantities in HGFE and DCBA are multiplied in extended floating-point form. Both operands are deleted, and the result is pushed onto the stack. Overflow is set if the result falls outside the range of extended floating-point numbers. Condition Code is set on the result. ENEG (000304).
TNS Instruction Set Definitions of TNS Instructions Condition Code settings; the “a” states apply for comparisons.) Both operands are then deleted from the stack. FDIV (000273). Floating-Point Divide. The floating-point quantity in DC is divided in floating-point form by the floating-point quantity in BA. Both operands are deleted and the result is pushed onto the stack. Overflow is set if the result falls outside the range of floating-point numbers. Condition Code is set on the result. FMPY (000272).
TNS Instruction Set Definitions of TNS Instructions the result in R[7]. If any subscript is out of bounds, overflow is set. DCBA is then deleted. IDXD (000317). Calculate Index, Data Space. For an n-dimensional array, IDXD compares the subscript values in n stack registers (B, C, D, and so on) against lower and upper bounds in a table in the current data segment (2n + 1 words) specified by a starting address in A.
TNS Instruction Set Definitions of TNS Instructions LAND (000010). Logical AND A With B. A and B are logically ANDed. The two words are deleted from the stack and the result pushed on. Condition Code is set. (For an example, see Figure 11-5 on page 11-6.) LBA (000364). Load Byte via A. The unsigned byte contained in the effective memory location pointed to by the byte address in A is loaded onto the stack, with zero extension, replacing the prior contents of A. LBA accesses the current data segment only.
TNS Instruction Set Definitions of TNS Instructions Figure 11-10.
TNS Instruction Set Definitions of TNS Instructions LBX (000406). Load Byte Extended. The unsigned byte in the memory location specified by the 32-bit byte address in registers B and A is loaded onto the register stack (bits 8 through 15 of A), after the address in BA is deleted. The left byte of A is set to zero. The Condition Code is set on the category of the loaded byte in A: CCL indicates ASCII numeric, CCE indicates ASCII alphabetic, and CCG indicates special ASCII character. LBXX (0256--, 0266--).
TNS Instruction Set Definitions of TNS Instructions LDI (100---). Load Immediate Operand Into A. The immediate operand is pushed onto the stack, with the sign bit propagating into the high-order bits. Condition Code is set. (For binary coding details, refer to Table B-2 on page B-2.) LDIV (000203). Logical Divide CB by A, leaving the remainder in B. The 32-bit positive (unsigned) integer in C and B is divided by the 16-bit positive integer in A.
TNS Instruction Set Definitions of TNS Instructions LQAS (000445). Load Quadrupleword via A From SG. The quadrupleword contained in the four memory locations starting at the location pointed to by the address in A is loaded into DCBA (after the address in A is deleted). The address in A refers to an address in the system data segment. Condition Code is set. This is a privileged instruction. LQX (000414). Load Quadrupleword Extended.
TNS Instruction Set Definitions of TNS Instructions so indicated is assumed to be the first word of a two-word even-byte extended memory pointer. The index value in A is sign-extended, then shifted left one bit position (multiplication by 2, because this instruction requires word addressing rather than byte addressing) and then added to the extended memory pointer to address the word that is to be loaded. Condition Code is set. For binary coding details, refer to Table B-3 on page B-3. MBXR (000420).
TNS Instruction Set Definitions of TNS Instructions count, B to contain the source byte address, and C to contain the destination byte address. The source and destination segments to be used are specified by the “S” and “D” fields of the instruction and by the DS, CS, and LS bits of the ENV register. The “RL” field of the instruction determines whether the source and destination addresses will be incremented (“RL” = 0) or decremented (“RL” = 1) after each move.
TNS Instruction Set Definitions of TNS Instructions NSTO (-34---). Nondestructive Store From A. The contents of the A register are stored into the effective address memory location. The register stack is not modified. For binary coding details, refer to Table B-1 on page B-1. ONED (000003). One Double. A doubleword 1 is pushed onto the top of the register stack (BA). Condition Code is set. ORG (000045). OR to Memory.
TNS Instruction Set Definitions of TNS Instructions POP (124nrc). Pop Data Space to Registers. This instruction loads the register stack with the top elements of the data stack (as indicated by the current S register setting). The “n” field of the instruction indicates the value RP will have following the instruction, the “r” field specifies the last register stack element to be loaded from memory, and the “c” field specifies the number of registers minus one that will be loaded.
TNS Instruction Set Definitions of TNS Instructions Figure 11-11.
TNS Instruction Set Definitions of TNS Instructions QADD (000240). Quadruple Add. The two quadrupleword integers contained in HGFE and DCBA are added in quadrupleword integer form. Both operands are deleted, and the quadrupleword result is pushed onto the stack. Overflow is set if the result is greater than 263–1 or less than –263. Carry can be set, and Condition Code is set on the result. QCMP (000245). Quadruple Compare.
TNS Instruction Set Definitions of TNS Instructions QSUB (000241). Quadruple Subtract. The quadrupleword integer contained in DCBA is subtracted in quadrupleword integer form from the quadrupleword integer in HGFE. Both operands are deleted, and the quadrupleword result is pushed onto the stack. Overflow is set if the result is greater than 263–1 or less than –263. Carry is set if no borrow-out occurs. Condition Code is set on the result. QUP (00025-). Quadruple Scale Up.
TNS Instruction Set Definitions of TNS Instructions SBAS (000355). Store Byte via A Into System. The byte in B is stored into the effective memory location pointed to by the byte address in A. Both B and A are then deleted. A refers to an address in the system data segment. SBRA (00015-). Subtract Register From A. The contents of the register pointed to by the Register field of the instruction are subtracted in integer form from register A.
TNS Instruction Set Definitions of TNS Instructions the first word of a two-word extended memory pointer. The index value in A is then added to the extended memory pointer to address the location that is to receive the byte being stored. For binary coding details, refer to Table B-3 on page B-3. SCS (000444). Set Code Segment. Registers B and A are assumed to contain a 17-bit byte address within the current code segment.
TNS Instruction Set Definitions of TNS Instructions SSW (000027). Store A Into Switch Register. The contents of the A register are set into sysstack[%122]. A is then deleted. This instruction is nonprivileged even though it alters an SG cell. STAR (00011-). Store A in a Register. The A register contents are stored in the register pointed to by the Register field of the instruction. A is then deleted from the stack. (For binary coding details, refer to Table B-5 on page B-5.) STB (-54---).
TNS Instruction Set Additional Operating-System-Only Instructions other code segment specifies a procedure entry point within that segment. The address space mappings of relative segments 2 and 3 (current code segment and latest user code segment) are updated. See detailed descriptions in Section 6, TNS Execution Modes. XMSK (000064). Exchange MASK With A. The contents of the MASK register are interchanged with the contents of the A register. This is a privileged instruction. XOR (000012).
TNS Instruction Set Resource Management Resource Management MXON (000040) Mutual Exclusion On MXFF (000041) Mutual Exclusion Off SFRZ (000053) System Freeze DOFS (000057) Disk Record Offset DLEN (000070) Disk Record Length HALT (000074) Processor Halt PSEM (000076) “P” a Semaphore VSEM (000077) “V” a Semaphore FRST (000405) Firmware Reset RPT (000442) Read Process Time SPT (000443) Set Process Timer BCLD (000452) Bus Cold Load DDTX (000456) DDT Request Memory Managem
A TNS Instruction Lists This appendix provides two tables that list all instructions in the TNS instruction set with their mnemonics and opcodes, first in alphabetic order by mnemonic and then grouped by type of instruction. The tables are: Table A-1, Alphabetic List of Instructions, on page A-1 Table A-2, Categorized List of Instructions, on page A-9 For some instructions, the six-digit opcode notation used in Table A-1 and Table A-2 cannot give complete information about the opcode.
TNS Instruction Lists Table A-1.
TNS Instruction Lists Table A-1.
TNS Instruction Lists Table A-1.
TNS Instruction Lists Table A-1.
TNS Instruction Lists Table A-1.
TNS Instruction Lists Table A-1.
TNS Instruction Lists Table A-1.
TNS Instruction Lists Table A-2.
TNS Instruction Lists Table A-2.
TNS Instruction Lists Table A-2.
TNS Instruction Lists Table A-2.
TNS Instruction Lists Table A-2.
TNS Instruction Lists Table A-2.
TNS Instruction Lists Table A-2.
TNS Instruction Lists Table A-2.
TNS Instruction Lists Table A-2.
TNS Instruction Lists HP NonStop S-Series Server Description Manual—520331-004 A-18
B TNS Instruction Binary Coding This appendix provides a number of reference tables that define the binary coding for most of the TNS instructions, grouped according to the coding patterns of the fields of the instruction words. (For example, all memory reference instructions are listed together.) These tables break down each instruction, bit by bit, into its component parts, indicate the operands, results, and ENV register bit settings, and show relationships between similar instructions.
TNS Instruction Binary Coding Table B-1. Binary Coding, Memory Reference Instructions (page 2 of 2) I [0 : 1] indicates direct or indirect address. XX [0 : 3] indicates index register selection. +/– [0 : 1] implies two’s complement notation; the sign is extended through bit 0 at execution. v = Overflow k = Carry cc = Condition Codes: a CCL (result < CCE (result = CCG (result > b CCL CCE CCG 0) 0) 0) or or or Note: opr1 is first item pushed on stack, opr2 is second.
TNS Instruction Binary Coding Table B-3.
TNS Instruction Binary Coding Table B-4.
TNS Instruction Binary Coding Table B-5.
TNS Instruction Binary Coding Table B-5.
TNS Instruction Binary Coding Table B-6.
TNS Instruction Binary Coding Table B-7.
C TNS Instruction Set Definition Symbol Definitions This appendix defines the TNS instruction set for the NonStop S-series processors, using conventions of the TAL programming language but based upon the special symbols that are defined in Table C-1. Following this table of symbol definitions, Table C-2 on page C-11 provides the formal definitions of the instructions in numeric order according to the octal codes. Table C-1.
TNS Instruction Set Definition Symbol Definitions Table C-1. Definitions of Symbols (page 2 of 9) Notation Description A A = R[RP] address = if indirect then $XADR(xmem[ dir.adr ]) else dir.adr B = R[RP-1] BA = B.<0:15>^A.
TNS Instruction Set Definition Symbol Definitions Table C-1. Definitions of Symbols (page 3 of 9) Notation Description chkp(x)= if memory location "x" is absent then Page Fault CLOCK = sysstack[ %350:%353 ] code[ la ] = mem[ CCSEG[ csegx ], $XADR(la) ] codeb[ ba ] mem[ CCSEG[csegx], ba ] for 1 byte COLDTIME = sysstack[ %354:%357 ] computeshiftcount (max) = if I.<10:15>=0 then {shiftcount:= A.<11:15>; RP:=RP-1} else shiftcount:= $min(max,I.
TNS Instruction Set Definition Symbol Definitions Table C-1. Definitions of Symbols (page 4 of 9) Notation Description dir.adr = if I.<7> = 0 then 'global variable' $XADR(I.<8:15>) (0:255) else if I.<8> = 0 then 'local variable' Lx.<0:31>+$XADR(I.<9:15>) (0:127) else if I.<9> = 0 then 'system global' SG.<0:31>+$XADR(I.<10:15>) (0:63) else if I.<10> = 0 then 'procedure param' Lx.<0:31>-$XADR(I.<11:15>) (0:31) else Sx.<0:31>-$XADR(I.<11:15>);'subroutine param' (0:31) DS = ENV.<6> dseg = if I.
TNS Instruction Set Definition Symbol Definitions Table C-1. Definitions of Symbols (page 5 of 9) Notation Description Indivisible On 'turn off all external interrupts'. Exceptions for page fault, overflow, IFAIL will still be processed. INQ[0:1,0:15]. <0:15>= interprocessor bus in queues INTA.<0:15> = interrupt register A INTB.
TNS Instruction Set Definition Symbol Definitions Table C-1. Definitions of Symbols (page 6 of 9) Notation Description PHYTNSSEGSZ = Size of a physical segment in logical TNS pages. Physical segments directly mapped and do not have a SEG entry. PRIV = ENV.<5>, simulated privileged bit priv trap = instruction failure interrupt via SIV[3] PTIME = sysstack[ 126:127 ] REGSAVE= { REGS[0:31].<0:31> ARITHHI.<0:31>; ARITHLO.<0:31>; RETPC.<0:31> FLTPC.<0:31> CDS.<0:31> TNSREGSVALID.<0:7> CSPACEID.
TNS Instruction Set Definition Symbol Definitions Table C-1. Definitions of Symbols (page 7 of 9) Notation Description SIV = 32-bit system interrupt vector { Lx.<0:31> GIH stack pointer, INT32 aligned MASK.<0:15> FILLER.<0:15> RETPC.<0:31> PC of the interrupt handler PMAP.<0:31> address of SC.0's PMAP table PARM1.<0:31> PARM2.<0:31> FILLER.<0:63> }; source(la) = mem[ srcseg, $XADR(la) ] SPAD = PDS[%hFFFF9000] srcsegx = case I.
TNS Instruction Set Definition Symbol Definitions Table C-1. Definitions of Symbols (page 8 of 9) Notation Description Trap_Int_zero_divide = %60 Trap_Int_Overflow = %61 Trap_Bounds = %62 Trap_soft_Overflow = %63 Trap_Fp_Zero_divide = %64 Trap_Fp_Exp_Overflow = %65 Trap_Fp_Exp_Underflow= %66 TRACE = sysstack[ %121 ] TRBASE = sysstack[ %117 ] TRLIM = sysstack[ %120 ] UC= ENV.
TNS Instruction Set Definition Symbol Definitions Table C-1. Definitions of Symbols (page 9 of 9) Notation Description xmem2[ x ] = xmem4[ x ] = xmap(x)= xmem[ x : x+3 ]32 xmem[ x : x+7 ]64 ! cross code space map: ! x= new spaceid ! x.<4>= new LS value ! x.<7>= new CS value ! x.
TNS Instruction Set Definition Instruction Definitions Instruction Definitions Table C-2 presents symbolic definitions of the TNS instruction set for the NonStop S-series processor, in numeric opcode order. Refer to Table C-1 for definitions of the symbols used in this table. The one-character symbols immediately to the right of the instruction opcodes have the following meanings: * indicates privileged instruction. @ indicates operating system use only.
TNS Instruction Set Definition Instruction Definitions Table C-2.
TNS Instruction Set Definition Instruction Definitions Table C-2. Instruction Definitions (page 2 of 38) 0 0 0 0 2 2 SETE set ENV register ENV.RP := A.<13:15>; ENV.<0:7> := ENV.<0:7> & A.<0:7>; if ENV.DS <> A.DS then 'IFAIL(TRAP_INVALID_OPERAND)'; if (ENV.<0:7> & ~A.<0:7>) <> 0 then IFAIL(TRAP_INVALID_OPERAND); 'validate ENV.NZ'; case A.<11:12> of {cc(1); ! N,Z = (0,0) cc(0); ! N,Z = (0,1) cc(-1); ! N,Z = (1,0) 'IFAIL'; ! N,Z = (1,1); }; ENV.V := A.<10>; K := A.<9>; ENV.T := A.<8>; if ENV.T & ENV.
TNS Instruction Set Definition Instruction Definitions Table C-2. Instruction Definitions (page 3 of 38) 0 0 0 0 3 2 DPCL dynamic procedure call A.<0:6> - space id A.<7:15> - pep index t := (ENV & %177740) | CSPACEID ; stack[S+1:S+3] := (Px.<15:30>,t,Lx.<15:30>); t.<7> := A.<0>; ! CS t.<4> := A.<1>; ! LS t.<11:15> := A.<2:6>; ! space index xmap( t ); m := A.<0> + 2*A.<1> + 2; t := A.<7:15>; p := t.
TNS Instruction Set Definition Instruction Definitions Table C-2. Instruction Definitions (page 4 of 38) 0 0 0 0 4 0* MXON mutex on A=<0:7> INTNS code size <8:15> INTNS stack size 'Restart Point:' 'Indivisible On'; if chkp(stackb[(Lx-$XADR(20)) max 0]) then {page fault; goto 'restart point'}; if chkp(stackb[Sx+$XADR(A.<8:15>)]) then {page fault; goto 'restart point'}; if A.<0:7> then if chkp(codeb[TNSP+$XADR(A.
TNS Instruction Set Definition Instruction Definitions Table C-2.
TNS Instruction Set Definition Instruction Definitions Table C-2.
TNS Instruction Set Definition Instruction Definitions Table C-2. Instruction Definitions (page 7 of 38) 0 0 0 0 7 6* PSEM "P" a semaphore DC=wait time BA=semaphore extended absolute address 'Indivisible On'; xmem[BA+4]:=xmem[BA+4]-1; if xmem[BA+4] < 0 then {$R[4] := DC; $R[5] := BA; siv[15].parm1_lo:=siv[15].parm1_lo | 5; set dispatcher interrupt; 'Indivisible Off'; D := $R[3].
TNS Instruction Set Definition Instruction Definitions Table C-2.
TNS Instruction Set Definition Instruction Definitions Table C-2.
TNS Instruction Set Definition Instruction Definitions Table C-2.
TNS Instruction Set Definition Instruction Definitions Table C-2.
TNS Instruction Set Definition Instruction Definitions Table C-2.
TNS Instruction Set Definition Instruction Definitions Table C-2. Instruction Definitions (page 13 of 38) 0 0 0 2 7 1 FSUB floating subtract if BA<>0 then B.<0>:=~B.<0>; goto FADD 0 0 0 2 7 2 FMPY floating multiply V:=0 if DC=0 or BA=0 then DC:=0 else {t1:=exponent(C); t2:=exponent(A); exp:=t1+t2-255; sign:=D.<0> xor B.<0>; D.<0>:=B.<0>:=1; exponent(C):=0; exponent(A):=0; DCBA:=DC'*'BA; norm(DC); DC:=DC'+'%400; if carry out then exp:=exp+1; if exp.<6>=1 then call overflow; D.
TNS Instruction Set Definition Instruction Definitions Table C-2. Instruction Definitions (page 14 of 38) 0 0 0 2 7 5 FCMP floating compare V := 0; if D.<0> <> B.<0> then cc(D:B) else {sign:=D.<0>; D.<0>:=B.
TNS Instruction Set Definition Instruction Definitions Table C-2. Instruction Definitions (page 15 of 38) 0 0 0 3 0 0 EADD extended add V:=0 t1:=exponent(E); t2:=exponent(A); if DCBA<>0 and HGFE<>0 and abs(t1-t2)<56 then {sign1:=H.<0>; sign2:=D.<0>; H.<0>:=D.<0>:=1; exponent(E):=0; exponent(A):=0; s:=t1-t2; if s>=0 then DCBA:=DCBA'>>'s; else {HGFE:=HGFE'>>'-s; HGFE:=:DCBA; t1:=t2} if sign1=sign2 then {HGFE:=HGFE'+'DCBA; if carry then {HGFE:=HGFE'>>'1; t1:=t1+1; H.
TNS Instruction Set Definition Instruction Definitions Table C-2. Instruction Definitions (page 16 of 38) 0 0 0 3 0 2 EMPY extended multiply V:=0 if HGFE=0 or DCBA=0 then HGFE:=0 else {t1:=exponent(E); t2:=exponent(A); exp:=t1+t2-255; sign:=H.<0> xor D.<0>; H.<0>:=D.<0>:=1; exponent(E):=0; exponent(A):=0; HGFE:=HGFE'*'DCBA; norm(HGFE); HGFE:=HGFE'+'%400; if carry out then exp:=exp+1; if exp.<6>=1 then call overflow; H.
TNS Instruction Set Definition Instruction Definitions Table C-2. Instruction Definitions (page 17 of 38) 0 0 0 3 0 5 ECMP extended compare V := 0; if H.<0> <> D.<0> then cc(H:D) else {sign:=H.<0>; H.<0>:=D.<0>:=0; t1:=exponent(E); t2:=exponent(A); if t1<>t2 then if sign=0 then cc(t1:t2) else cc(t2:t1) else if sign=0 then cc(HGFE:DCBA) else cc(DCBA:HGFE)} 0 0 0 3 0 6 CDF convert double to floating V := 0; sign:=B.
TNS Instruction Set Definition Instruction Definitions Table C-2. Instruction Definitions (page 18 of 38) 0 0 0 3 1 2 CFD convert floating to double V := 0; t:=31+256-exponent(A); sign:=B.<0>; if -2**31 <= BA <= 2**31-1 then {B.<0>:=1; exponent(A):=0; BA:=BA'>>'t; if sign=1 then BA:=-BA} else V:=1; cc(BA) 0 0 0 3 1 3 CFDR convert floating to double with rounding V := 0; t:=31+256-exponent(A); sign:=B.<0>; if -2**31 <= BA <= 2**31-1 then {B.
TNS Instruction Set Definition Instruction Definitions Table C-2. Instruction Definitions (page 19 of 38) 0 0 0 3 1 6 CEIR convert extended to integer with rounding V := 0; t:=15+256-exponent(A); sign:=D.<0>; if -2**15 <= DCBA <= 2**15-1 then {D.<0>:=1; DC:=(DC'>>'t) '+' %100000; if sign=1 then D:=-D else if D.<0>=1 then V:=1} else V:=1; cc(D); RP:=RP-3 0 0 0 3 1 7 IDXD calculate index offset and test for bounds violation (bounds table in data space) V := 0; t:=stack[A]; bc:=t.<0>; t.
TNS Instruction Set Definition Instruction Definitions Table C-2. Instruction Definitions (page 20 of 38) 0 0 0 3 2 1 CFQR convert floating to quad with rounding V := 0; t:=63+256-exponent(A); sign:=B.<0>; RP:=RP+2; if -2**63 <= DC <= 2**63-1 then {D.<0>:=1; exponent(C):=0; B:=A:=s:=0; DCBAs:=(DCBAs'>>'t) '+' %100000; if sign=1 then DCBA:=-DCBA} else V:=1; cc(DCBA) 0 0 0 3 2 2 CEQ convert extended to quad V := 0; t:=63+256-exponent(A); sign:=D.<0>; if -2**63 <= DCBA <= 2**63-1 then {D.
TNS Instruction Set Definition Instruction Definitions Table C-2. Instruction Definitions (page 21 of 38) 0 0 0 3 2 6 CDFR convert double to floating with rounding V := 0; sign:=B.<0>; exp:=31+256; if sign=1 then BA:=-BA; if BA<>0 then {norm(BA); BA:=BA'+'%400; if carry out then exp:=exp+1; exponent(A):=exp; B.<0>:=sign} 0 0 0 3 2 7 CID convert integer to double H:=A; A:=A>>15; V:=0; RP:=RP+1 0 0 0 3 3 0 CQFR convert quad to floating with rounding V := 0; sign:=D.
TNS Instruction Set Definition Instruction Definitions Table C-2. Instruction Definitions (page 22 of 38) 0 0 0 3 3 4 CDE convert double to extended V := 0; sign:=B.<0>; exp:=31+256; if sign=1 then BA:=-BA; H:=0; if BA<>0 then {norm(BA); G:=exp; B.<0>:=sign} else G:=0; RP:=RP+2 0 0 0 3 3 5 CQER convert quad to extended with rounding V := 0; sign:=D.<0>; exp:=63+256; if sign=1 then DCBA:=-DCBA; if DCBA<>0 then {norm(DCBA); DCBA:=DCBA'+'%400; if carry out then exp:=exp+1; exponent(A):=exp; D.
TNS Instruction Set Definition Instruction Definitions Table C-2.
TNS Instruction Set Definition Instruction Definitions Table C-2. Instruction Definitions (page 24 of 38) 0 0 0 3 4 7 IDXP calculate index offset and test indices for bounds violation (bounds table in code space) V := 0; t:=code[A]; bc:=t.<0>; t.
TNS Instruction Set Definition Instruction Definitions Table C-2.
TNS Instruction Set Definition Instruction Definitions Table C-2.
TNS Instruction Set Definition Instruction Definitions Table C-2.
TNS Instruction Set Definition Instruction Definitions Table C-2. Instruction Definitions (page 28 of 38) 0 0 0 4 4 2* RPT read process timer 'Indivisible On'; RP := RP + 2; if not 'trusted copy of DS' then BA := PTIME + (TIMER) + (10000 * INTA.<13>) else BA := PTIME 'Indivisible Off' 0 0 0 4 4 3* SPT set process timer 'Indivisible On'; if not DS then PTIME := BA - TIMER - (INTA.
TNS Instruction Set Definition Instruction Definitions Table C-2. Instruction Definitions (page 29 of 38) 0 0 0 4 5 6* DDTX DDT request A.
TNS Instruction Set Definition Instruction Definitions Table C-2. Instruction Definitions (page 30 of 38) 0 0 0 5 0 1* XSST XRAY Set State CB=ext addr A=counter offset 'Indivisible On'; t := xmem2[CB]; if t.
TNS Instruction Set Definition Instruction Definitions Table C-2. Instruction Definitions (page 31 of 38) 0 0 0 5 0 3* XIST XRAY increment state CB=ext addr A=counter offset 'Indivisible On'; t := xmem2[CB]; if t.
TNS Instruction Set Definition Instruction Definitions Table C-2. Instruction Definitions (page 32 of 38) 0 0 0 5 2 6* CAFL Cache Flush Inputs A - flags A.<0:13> = reserved A.<14> = flush data cache A.<15> = flush instruction cache CB - byte count ED - extended address 'Indivisible On'; vpte := RSPT(ED); if K then IFAIL( NO_Segment ); K := 0; 'flush cache( A.
TNS Instruction Set Definition Instruction Definitions Table C-2.
TNS Instruction Set Definition Instruction Definitions Table C-2. Instruction Definitions (page 34 of 38) 1 2 5 0-- - - EXIT exit procedure xmap( stackb[Lx-2] & %4437 ); (Sx,P,ENV,Lx):=( Lx-I.<8:15>*2, stackb[Lx-4], (stackb[Lx-2])&ENV&%073000 | stack[Lx-2]&%104740 | ENV&%37, $XADR(stackb[Lx])); if P is register-exact point then use Accelerated Mode else use Nonaccelerated Mode if ENV.<0> then Instruction Breakpoint if ENV.V and ENV.
TNS Instruction Set Definition Instruction Definitions Table C-2. Instruction Definitions (page 35 of 38) 1 2 6 40mssd n SBW scan bytes while while bytesource(B)<>0 and bytesource(B)=A do B:=B+movestep K:=bytesource(B)=0; RP:=n 1 2 6 42mssd n SBU scan bytes until while bytesource(B)<>0 and bytesource(B)<>A do B:=B+movestep K:=bytesource(B)=0; RP:=n 0 2 7 PCAL procedure call stack[Sx+2:Sx+6]:=(Px.<15:30> ,(ENV & %177740) | CSPACEID ,Lx.<15:30>); t:=I.
TNS Instruction Set Definition Instruction Definitions Table C-2. Instruction Definitions (page 36 of 38) 1 2 7 - - - XCAL external call stack[Sx+2:Sx+6]:=(Px.<15:30> ,(ENV & %177740) | CSPACEID ,Lx.<15:30>); ! calculate CCSEG segment size @vSEG := CPDST[ (xa :=CCSEG[csegx] ).<1:6> ]; @page := vSEG[ xa.<7:14> ]; i:=page.TNSSEGSZ*%2000-1; t := code[i-I.<7:15>]; s.<7> := t.<0>; ! CS s.<4> := t.<1>; ! LS s.<11:15> := t.<2:6>; ! space index xmap( s ); m := t.<1> | t.<0>; p := t.
TNS Instruction Set Definition Instruction Definitions Table C-2.
TNS Instruction Set Definition Instruction Definitions Table C-2. Instruction Definitions (page 38 of 38) I 7 0xx - - - LADR load address RP:=RP+1; A:=address.
TNS Instruction Set Definition Compatibility Notes Compatibility Notes The following list defines notes referred to in Table C-2 on page C-11. These notes identify significant differences in the operation of an instruction in the NonStop (RISCbased) processors as compared to the operation in earlier TNS (CISC-based) processors. 1. CALLABLE PRIV These are nonprivileged instructions that require access to privileged state or memory. The implementation temporarily becomes privileged (and back) if necessary.
TNS Instruction Set Definition Compatibility Notes 11. Single Shifts >= 32 Single-word shift counts in the range [16 : 31] have the same effect as a shift count of 16. Single-word shift counts less than 0 or greater than 31 give undefined answers. 12. SG Address in Nonpriv Mode SG addresses are not allowed in nonprivileged mode, and cause an INSTRUCTION FAILURE interrupt. TNS processors simply redirect the SG address to short address space 0. 13. (Not used.) 14.
Index Numbers 6770 cluster switch 1-42 6780 cluster switch 1-50 A Absolute address translation 4-42 Absolute addressing 4-6, 4-26, 4-30 Absolute memory allocation 4-30 Absolute segment 4-30 Accelerated execution benefits of 6-2 described 6-70/6-84 Accelerated mode defined 6-2 return from procedure 6-74 switch to TNS 6-72 Accelerated object code absence, indication of 4-22 allocation 4-20/4-23 expansion factor 4-22 location in code region 6-70 system code 4-28 Accelerated program file 6-70 Accelerator 6-2 A
Index B Allocation (continued) Kseg2 4-30, 4-46 main stack 4-14 regions 4-12/4-21 SC and SCr 4-28 shared run-time library (SRL) 4-18, 4-24 system code 4-28 system data 4-28 system library 4-16/4-21 native mode 4-18 TNS mode 4-20 TNS object code 4-20/4-23 user code, TNS 4-16 user data, TNS 4-12 user library, TNS 4-20 user space 4-24 Vseg table 4-28 Appearance side 1-6 ASID (address space identifier) 4-38 AVT (access validation and translation) 2-8, 9-8, 10-6 AVTT (access validation and translation table) 2
Index D Communications monitor 10-2 Communications work queue 10-18 Condition Code (CC) 3-9 Context-bound address (CBA) 4-50 Context-free addressing 4-30 Controller See ServerNet addressable controller (SAC) Core tetrahedron 1-4 CRU group number 1-28 CRU (customer-replaceable unit) 1-2 Current code segment 4-12, 6-82 Customer-replaceable unit (CRU) 1-2 D Data alignment rules 3-2/3-4 Data cache 4-34 Data segment 5-6, 6-20 Debug stack 4-30 Decimal arithmetic 3-10 Direct addressing 6-16 Direct branch addres
Index G Far gateway 7-17 Far jump 6-80 Far jump table 6-80, 7-16 Fault tolerance 1-10 FCSA (Fibre Channel ServerNet adapter) 1-38 Fibre Channel ServerNet adapter (FCSA) 1-38 Flag, execution mode 5-10 Flat segments allocation of 4-24 defined 4-10 Floating-point arithmetic 3-11 Foreign process data space 4-50 Four-lane link 1-46 FOX ring 1-42 Frame interrupt stack 8-6 origin 7-4 physical memory 4-4, 4-36, 4-44 pointer 7-4 stack RISC 7-4, 7-12 TNS 6-34 G G4SA 1-38 Gateway 6-84 Gateway table accelerated mode
Index K Interrupt arithmetic overflow 8-13 correctable memory error (CME) 8-12 dispatcher 8-13 handler 8-2, 8-8 instruction breakpoint 8-13 instruction failure 8-12 IPC and I/O 8-13 masking 8-2 memory access breakpoint 8-12 packet 8-4, 9-9, 9-18, 10-14 page fault 8-12 power fail 8-12 power on 8-13 priority 8-10 queue 2-14, 8-4, 9-9 register (INTA) 8-4 sampler 8-13 stack frame 8-6 stack marker 8-6 stack overflow 8-13 time list 8-13 uncorrectable memory error (UCME) 8-12 Interrupt register (INTA) 8-4 IOAM 1
Index M LXi 8-6 L-minus-relative addressing mode 6-36, 6-50 L-plus-relative addressing mode 6-36, 6-46 M Main stack allocation of 4-14 described 5-4 Mask field 4-40 Mask register 8-10 Memory access 4-32/4-51 Memory cache 4-34 Memory descriptor 2-10 Memory-exact point 6-76 Memory-mapped registers 4-6 Message checkpoint 1-10 defined 9-1 system 9-1 transfer 9-8 transfer protocol 9-2, 9-6 MFIOB (multifunction I/O board) 1-8, 10-4 Millicode 4-18, 4-20, 4-28 Mirrored volume 1-12 Mode accelerated See Accelerate
Index O O Overflow (V) indicator 3-9, 8-10 Overflow, floating-point 3-12 P Packet acknowledgment 9-6 interrupt 8-4, 9-9, 9-18, 10-14 request 2-6 response 2-6 ServerNet 2-6 setup 9-2 Page 4-4, 4-36 Page fault 4-36 Page table (PT) described 4-44 null 4-48 Parameters, procedure accessing 6-50 deletion of 6-54 example 6-52 passing 6-48 reference 6-48/6-51 stacked 6-48/6-56 value 6-48/6-51 PC (program counter), RISC 6-14, 6-76 PCAL instruction 6-40/6-43 PDST (process data space table) 4-44 PEP (procedure entr
Index Q Process code and data allocations 5-6 TNS 5-2 TNS/R native 5-2 Process address space 4-2 Process data space table (PDST) 4-44 Process file segment (PFS) 4-30 Process identifier (TLBPID) See TLBPID Process pair 1-10 Processor and memory board (PMB) 1-8 Processor enclosure 1-2 Processor multifunction (PMF) CRU 1-2, 1-8 Processor ServerNet interface 2-2, 2-8 Process-relative addressing 4-6 Program counter (PC), RISC 6-14, 6-76 Protocol linker-listener 9-4 message system 9-6 message transfer 9-2 post-
Index S Register (continued) v0 7-2 $0 7-2 Register stack accelerated mode 6-82 described 6-8/6-12 in interrupt stack 8-6 simulated 4-46 top of 6-38 Register stack pointer (RP) 6-8/6-12, 6-38 Register-exact point 6-76 Relative addressing 4-6/4-24 Relative segment number 4-8 Request packet 2-6 Request queue, I/O 10-6, 10-10 Response packet 2-6 Right-left indicator 11-8 RISC environment 8-6 RISC processor 6-2 RISC registers 7-2 RISC word 3-2 Rmap (return map) 6-76 Router hop 1-22 Router port 1-14 Router, Se
Index S ServerNet adapter 1-6, 10-4 ServerNet address 2-6, 10-4 ServerNet addressable controller (SAC) 1-8, 1-14, 10-4 ServerNet buffer board (SBB) 1-18, 1-20 ServerNet bus interface (SBI) 1-8, 1-14, 2-2, 10-4 ServerNet cluster 1-42/1-53 ServerNet device 2-2, 2-4 ServerNet end device 2-2 ServerNet expansion board (SEB) See SEB (ServerNet expansion board) ServerNet fabric external 1-42 internal 1-10, 1-14, 1-42 ServerNet ID 2-4 ServerNet link 1-22/1-24 ServerNet packet 2-6 ServerNet router 1-8, 1-10 Server
Index T Star topology 1-44 Subdevice, ServerNet 2-4 Sublocal area, stack 6-34, 6-36 Subprocedure 6-30 Subprocedure call 6-62, 7-4 Subsystem manager process 10-6 Switch group 1-50 Switch layers 1-50 Switch, cluster 6770 1-42 6780 1-50 Switch, ServerNet 1-38 SX register 8-6 System data segment absolute access 4-28 described 6-28 System enclosure 1-6 System global data 6-28 System interrupt vector (SIV) 8-4, 8-8 System library allocation 4-16/4-21 native mode 4-18 TNS mode 4-20 defined 5-8 native mode 7-6 S-
Index U Transaction type, ServerNet 2-6 Transfer information block (TIB) 2-10, 9-8 Transition, execution mode 5-10 Translation of object code 4-22 of virtual address 4-36/4-51 Translation lookaside buffer (TLB) See TLB (translation lookaside buffer) Tri-star topology 1-48 Two-lane link 1-48 Two’s-complement notation 3-9 TX command queue 10-22 TX completion queue 10-22 TX (transmission) operations, communications 10-20 U UCr code allocation 4-16 UC.0 4-20, 6-4 UL.
