NonStop S-Series Server Description Manual (G06.27+)

TNS Data Formats and Number Representations
HP NonStop S-Series Server Description Manual—520331-004
3-9
Instructions for Unsigned and Signed Arithmetic
Signed Arithmetic
Signed numbers are represented in 16 bits (a TNS word), 32 bits (TNS doubleword), or
64 bits (TNS quadrupleword).
Positive values are represented in true binary (base 2) notation. Negative values are
represented in two’s-complement notation with the sign bit of the most significant
word set to 1 (that is, WORD[0].<0>). The two’s complement of a number is obtained
by inverting each bit position in the number, and then adding a 1. For example, in
16 bits, the number 2 is represented:
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
and the number –2 is represented:
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
Signed arithmetic is indicated by the execution of integer instructions. The integer
instructions for single words provide for integer arithmetic (IADD, ADDI, ADDM, ADAR,
ADRA, ADXI, ISUB, SBAR, SBRA, IMPY, IDIV), comparison and two’s complement
negation (ICMP, CMPI, INEG), special load operations (LDI, LDLI, LDXI, LDRA,
STAR), and arithmetic shifts (ALS, ARS).
Similarly, instructions are provided for integer arithmetic on doubleword operands
(DADD, DSUB, DMPY, DDIV), comparison and negation (DCMP, DNEG), special load
and test operations (MOND, ZERD, ONED, DTST), and arithmetic shifts (DALS,
DARS).
Six instructions for quadrupleword operands provide for integer arithmetic (QADD,
QSUB, QMPY, QDIV) and for comparison and negation (QCMP, QNEG). In addition,
three instructions (QUP, QDWN, QRND) provide utility operations when used as part of
a decimal arithmetic computation (see next topic).
For all integer add, subtract, and negate instructions, the result on an overflow is the
truncated sum or difference. For multiplication and division instructions, the result on
overflow is undefined and will differ from results produced by other TNS or TNS/R
processors. When an overflow occurs, the Overflow (V) indicator is set and (if the
overflow trap is currently enabled) an interrupt to the operating system overflow
interrupt handler occurs. An overflow condition also occurs if a divide operation is
attempted with a divisor of 0. When no overflow occurs in these signed instructions,
V is reset to 0. (Any instruction that cannot set V always leaves V unchanged.)
In addition to the Overflow indicator, two other indicators are subject to change as the
result of an arithmetic operation. They are:
•
Condition Code (CC). This generally indicates whether the result of a
computation or a load operation was a negative value, zero, or a positive value. In
cases where overflow occurred, CC reflects the truncated result.
•
Carry (K). This indicates that a carry out of the high-order bit position occurred on
an add instruction. For subtract instructions, K=1 indicates that a borrow out of the
high-order bit position did not occur; that is, A–B sets K only if A '>=' B. For
multiply and divide instructions K is meaningless and is reset to 0.