NonStop S-Series Server Description Manual (G06.27+)

Memory Addressing and Access
HP NonStop S-Series Server Description Manual—520331-004
4-40
Nonglobal Address Translation
Nonglobal Address Translation
The entries in the translation lookaside buffer (TLB) are 128 bits wide, as shown in the
lower part of Figure 4-19. The high-order 64 bits contain the fields used to identify the
page address that is translated in one given slot of the TLB: a virtual page number
(VPN) and a translation lookaside buffer’s process identifier (TLBPID). Any given slot
of the TLB has two translations: one for an even virtual address and one for the
immediately following odd virtual address. These two translations occur in the low-
order 64 bits of the TLB entry.
The mask field specifies a page size, which is 16,384 bytes in the random TLB entries.
The TLBPID is described in the preceding topic. It specifies a process address space.
The VPN term is RISC terminology and is directly equivalent, in NonStop S-series
processor terms, to all of the most significant fields of a virtual address down to and
including the page field. Generally, this is an 18-bit field, bits 0 through 17 of a virtual
address; however, because of the even-odd pairing of translations (used for increased
efficiency), only 17 bits are used for comparison—that is, VPN divided by two, shown
as VPN/2. The low-order bit of the page field in the virtual address is used as an even-
odd selector in selecting one of the two translations in the TLB slot.
Nonglobal address translations need both of these fields in checking for a translation
hit. Addresses using global addressing do not require a matching TLBPID; translation
hits for such global elements are described in the next topic. The following paragraphs
describe the nonglobal case (specified by the one-bit G field being 0).
When a nonglobal address is applied to the TLB for translation, the TLB logic scans
the combination of VPN/2 and TLBPID fields, looking for a match with the combination
of the supplied TLBPID of the process and the first 18 bits of the address (ignoring the
lowest-order bit). In a nonglobal address, the first 18 bits comprise four fields: the
relative/absolute identifier, the region number, the relative segment number, and the
page number.
When an exact match is found in one of the 48 slots of the TLB, a translation hit has
occurred. The 22-bit field in bits 65 through 87 of the TLB entry (or 97 through 119 in
the case of an odd page) is then taken as the frame number of the target physical
address. The frame number field combined with the byte field of the nonglobal
address produces a 32-bit physical address that is capable of addressing a 4-gigabyte
range of physical memory.
TLB entry bits C, D, and V are used for special purposes and are described in the
succeeding topics.
In summary, referring to Figure 4-19: together, the first four (high-order) fields of the
nonglobal address form what the RISC processor considers to be the virtual page
number. In effect, the TLBPID is a superior part of the address. These two fields are
compared with corresponding fields in TLB entries. For a matching entry, the
translated frame number is in the 22-bit field from bits 65 through 87 (even page) or 97
through 119 (odd page).