NonStop S-Series Server Description Manual (G06.27+)

Memory Addressing and Access
HP NonStop S-Series Server Description Manual—520331-004
4-44
Address-Mapping Tables
Address-Mapping Tables
The translation lookaside buffer (TLB) is located on the RISC chip, and it is extremely
fast in performing virtual-to-physical address translations—actually in half a machine
cycle. However, any time a reference is made to a location in a page that does not
currently have a translation in the TLB (a translation miss), the memory-management
millicode must obtain the page translation from memory tables. Once that translation is
found (as part of a pair), the pair is stored in the TLB, overlaying some existing pair of
translations. The desired translation is then used for the current reference and
possibly future references, until it is itself replaced.
Figure 4-21 shows how a pair of translations is obtained from the memory tables, for
the case of nonprivileged and Kseg2 space addresses. All of these tables are in
Kseg0 memory, so they are resident and can be accessed without using the TLB.
Note that the objective is to store a pair of physical frame numbers in the right half of a
TLB entry.
As a first step, the region number in the region field of the address is used to index into
the process data space table (PDST) that is allocated for this process. The location
pointed to contains a 32-bit pointer to the beginning of one of 128 possible Vseg
tables. One Vseg table exists for each region that is currently allocated to the
nonprivileged space and the Kseg2 space. Note that region numbers 64 through 95
are not used, because they indicate Kseg0 and Kseg1; these and some other PDST
entries point to the null Vseg, described later.
Next, the relative segment number in the relative segment field of the address is used
to index into the selected Vseg table. The location pointed to contains another 32-bit
pointer, which points to the beginning of one of 256 page tables (PTs). One PT exists
for each segment that is currently allocated to the region. (Other Vseg entries point to
the null PT, described later.)
Finally, the page number in the page field of the address is used to index into the
selected page table. The location pointed to (if the V bit indicates valid) contains the
frame number needed to complete the translation. This content and the one in the
location preceding (if odd page) or following (if even page), are then loaded into the
right half of one slot in the TLB, along with the virtual page number in the left half.
These translations are now available for the current virtual reference.
If the V bit does not indicate valid (that is, the page is absent from physical memory), a
page-fault interrupt invokes the memory manager software to load the page from disk
to memory and to set up the page table entry. Then, when the process next executes,
the instruction that caused the TLB-miss exception is tried again.