NonStop S-Series Server Description Manual (G06.27+)

Instruction Processing Environments
HP NonStop S-Series Server Description Manual—520331-004
5-10
Restricting Mode Transitions
Restricting Mode Transitions
When a process begins execution, the mode of execution depends on the form of the
program object code. If the program was compiled as a TNS program, execution
begins in TNS mode, wherein a millicode interpreter program executes on behalf of the
TNS instructions. If the program was a TNS program that was accelerated, execution
begins in TNS mode but quickly switches to accelerated mode, wherein the translated
TNS code, in the form of RISC instructions, executes directly instead of the millicode
interpreter. If the program was compiled directly to RISC instructions, program
execution begins in native mode.
Changes of execution mode are restricted as shown in Figure 5-5. A program
executing in TNS mode must first make a transition to accelerated mode if, for
example, it calls a native library procedure. Likewise, on return from the native library
procedure, execution mode must switch to accelerated mode before returning to the
calling point in the TNS process. Such transitions are accomplished within shell
procedures. Shell procedures are discussed in detail in Section 7, Native Execution
Mode.
In this example there are three programs: A is TNS code, B is TNS code that has been
accelerated, and C is native code. Each kind of code executes in its own mode.
Accelerated objects usually execute in accelerated mode, but sometimes execute the
original TNS code in TNS mode. For system library calls, native code can call only SLr
routines, and accelerated code can call procedures in either SL or SLr; however, TNS
code can call only SL routines and SL shells that can access SLr.
The current execution mode of the current process is maintained as a mode flag in the
RP wrap page. Although the RP wrap page is in unprotected virtual memory,
protection for the mode flag is unncessary, because (unlike switching to privileged
state), changing execution mode offers no particular privileged advantage.
The state of the mode flag determines which set of stacks is in effect for the current
process—either the TNS stacks or the native RISC stacks. The mode also determines
how the RISC processor registers are used; different register conventions apply in
each mode. TNS and accelerated register usages are similar, using several registers
to hold emulated TNS processor state. Native mode usage is quite different.
Execution mode switches between TNSmode and accelerated mode occur at
procedure calls and exits; an acceleratedmode to TNS mode switch sometimes occurs
within a procedure. Execution mode switches from accelerated to native mode only at
procedure calls, and reverts at exit.
The following table summarizes register and stack conventions for the three modes.
Mode Flag Register State and Usage Stack Location and Structure
TNS TNS (nonaccelerated) TNS
Accelerated TNS (accelerated) TNS
Native Native Native