NonStop S-Series Server Description Manual (G06.27+)

TNS Execution Modes

HP NonStop S-Series Server Description Manual—520331-004

6-14

Basic P Register Operations

The P register (Program register) is the program counter of the TNS environment. It

contains the 16-bit C[0]-relative address of the next instruction to be executed.

Conventionally, the contents of the P register are incremented by 1 at the beginning of

instruction execution so that, ordinarily, instructions are fetched (and executed) from

ascending memory locations. This is shown in the upper part of Figure 6-8.

When a program branch is taken or a procedure or subprocedure is called, the

C[0]-relative address of the next instruction to be executed is placed in the P register.

Execution then resumes sequentially from this new point. A simple branching example

is shown in the lower part of the figure. In this example, the P register at C[1015]

causes an unconditional branch (BUN) instruction to be fetched, and advances to

C[1016]. The execution of the BUN instruction causes a value of 5 to be added to the

current P register value, resulting in a new P value and a jump to C[1021].

Both of these cases assume that TNS instructions are executing in a TNS

environment. Instead, only RISC instructions actually execute, and strictly in the RISC

environment. All TNS instructions must either be translated to RISC instructions prior

to run time or be interpreted during run time. Translation to RISC instructions (if done

at all) is performed by the Accelerator.

The RISC processor has its own PC register that, generally speaking, increments

several times for each single increment of the TNS P register. Thus the

correspondence of TNS P to RISC PC is often difficult to ascertain. To further

complicate matters in the case of accelerated code, optimization of a group of TNS

instructions frequently results in a corresponding group of RISC instructions. This

action blurs any instruction-for-instruction association. Thus, conversion from TNS P

to RISC PC (a topic considered later in this section) can be done only at certain

definable points, and the inverse conversion is precise only at those points.

TNS P is exact in nonaccelerated mode, except for interrupt handlers and memory

access debug points. RISC PC can always be ignored in TNS mode.