NonStop S-Series Server Description Manual (G06.27+)

Interrupt System
HP NonStop S-Series Server Description Manual—520331-004
8-10
Interrupt Masking
Interrupt Masking
Four TNS registers, simulated by exception-handling millicode, are associated with
interrupts: two 16-bit interrupt registers (INTA and INTB) and two 16-bit mask
registers (Mask A and Mask B). (Mask A is frequently referred to as “Mask” because
it is the only one recognized by the operating system.) The bit assignments of these
registers are illustrated in Figure 8-5. In general, the priority of interrupts is in top-to-
bottom order as shown in the figure—that is, uncorrectable memory error is the highest
and dispatcher the lowest. However, certain interrupts are exceptions to this general
rule and may be preemptive or mutually exclusive with other interrupts.
Only certain TNS interrupts are maskable—that is, the corresponding bits of the
associated mask register are used by the operating system to allow or defer particular
interrupt types at various times. The checking operation is performed by a logical AND
of the interrupt and mask registers. The interrupt condition is ignored if the
corresponding mask bit is equal to 0, and it will continue to be deferred until the mask
bit is set to 1.
Bits 1 and 4 of Mask A are not used as masks, although they are assigned. Thus
when the defined interrupt condition occurs, the interrupt handler is entered regardless
of the state of the mask bit. Accordingly, setting the corresponding interrupt register bit
would serve no purpose and so these bits also are never set (although assigned). A
partial exception is INTA.<1> and its corresponding Mask A bit (uncorrectable memory
error), which millicode does use in some circumstances.
The V bit (overflow bit in the Environment register) substitutes for bit 6 of INTA
(formerly assigned as arithmetic overflow or divide by zero), and it is separately
masked by the trap enable bit (T) of the Environment register to enable or disable that
interrupt. The V bit behaves differently from other interrupt bits; it gets cleared or set
by the most recent instruction that can affect it. (Other interrupt bits persist until
explicitly cleared by the exception millicode or the interrupt handler.)
If two or more interrupt conditions exist simultaneously (assuming a maskable
condition has its corresponding mask register bit set), the interrupt type with the
highest priority (lowest bit number) takes precedence. The others are deferred until
the higher-priority interrupts have been processed.
Interrupts for stack overflow, instruction failure, and instruction breakpoint have entries
neither in the interrupt registers nor in the mask registers; these cause an interrupt
whenever they occur, ignoring priority. The page fault interrupt, although it does have
an (unused) assignment in INTA and Mask A, also causes an interrupt whenever it
occurs, ignoring priority.