NonStop S-Series Server Description Manual (G06.27+)

Input/Output Operations

HP NonStop S-Series Server Description Manual—520331-004

10-18

Communications Operation Queuing

CThe remaining topics in this section describe communications I/O. The descriptions

assume that you have read the first three topics in this section, which describe the

basic differences between storage I/O and communications I/O. As illustrated earlier in

Figure 10-3 on page 10-7, communications I/O uses work queues (NIOC queues) that

are located in processor memory. Most of the following information concerns the

purpose and operation of these work queues, which are basically lists of I/O

operations—such as request commands for reading or writing of data, or for delivery of

addresses or status.

As shown in Figure 10-9, processor memory has allocations both for work queues and

for data buffers. A single resource, such as one communications line, can have several

queues assigned and several data buffers of differing sizes. Queue information gets

transferred between processor and controller memory, through the ServerNet

hardware, under control of queue services in the processor and controller firmware in

the controller. Data gets transferred between processor and controller memory by DMA

engines in the processor ServerNet interface in the processor and the ServerNet bus

interface (SBI) on a ServerNet adapter or multifunction I/O board (MFIOB).

Work queues are unidirectional. That is, a particular queue is used only for information

that is being written by the controller and read by the processor, or that is being written

by the processor and read by the controller. Unlike the queue entries used for storage

I/O (which are of fixed size, 64 bytes each), entries in these communications work

queues can be of varying length. The queues themselves may differ in length, one

from another, but once created their length remains fixed. They are circular (first in, first

out), and master copies of the head and tail pointers are maintained in the processor;

the controller reads these master copies whenever it needs to know current settings,

and can at times manipulate the head and tail pointers.