NonStop S-Series Server Description Manual (G06.27+)

TNS Instruction Set Definition
HP NonStop S-Series Server Description Manual—520331-004
C-50
Compatibility Notes
11. Single Shifts >= 32
Single-word shift counts in the range [16 : 31] have the same effect as a shift
count of 16.
Single-word shift counts less than 0 or greater than 31 give undefined answers.
12. SG Address in Nonpriv Mode
SG addresses are not allowed in nonprivileged mode, and cause an
INSTRUCTION FAILURE interrupt. TNS processors simply redirect the SG
address to short address space 0.
13. (Not used.)
14. Double Shift Counts >= 256
Doubleword shift counts less than 0 or greater than or equal to 256 give undefined
answers. Doubleword shift counts in the range [32 : 255] have the same net effect
as a shift count of 32.
15. EMPY Greater Precision
EMPY results have more precision than TNS processors for certain multiplications.
The NonStop answer is correct but different from TNS results.
16. Unimplemented TNS Op
These TNS instructions do not exist in the instruction set of the NonStop processor
and generate an INSTRUCTION FAILURE ‘Unimplemented TNS Opcode’
exception at run time, if executed.
17. Arith Left Shift Overflow
TNS arithmetic left shift instructions ALS and DALS do not allow the sign bit of the
result to change. Thus a (%040000 << 1) becomes %000000 after the TNS
arithmetic left shift.
The arithmetic left instructions behave this way in the NonStop processor only in
nonaccelerated mode. The Accelerator treats all left shifts as logical left shifts, in
which the sign bit is included in the bits being shifted. The result is the same bit
pattern, using either kind of shift, in all normal nonoverflow cases where the
operand was arithmetically small enough to avoid loss of significant bits when
shifted. The result’s sign bit is undefined in overflow cases.
As on TNS processors, overflow cases of shift instructions never set V and never
cause overflow traps.
18. Range Error
On a range error in the NonStop processor, CC and R[7] differ from values given in
TNS processors.
19. Sometimes Atomic
This instruction is atomic if the doubleword is aligned.