Object Code Accelerator Manual

Glossary
Object Code Accelerator Manual—528144-003
Glossary-14
logical page
logical page. (1) 2048 contiguous bytes of memory. (2) The size of a printed page given as
a number of lines.
logical processor. See processor.
logical segment. A single data area consisting of one or more consecutive 128-kilobyte
unitary segments that is dynamically allocated by a process. The two types of logical
segments are selectable segments and flat segments. See also selectable segment
and flat segment.
logical processor. The combination of equivalent processor elements in the processor
slices that are running in the same instruction stream in loose lock-step.
login. The activity by which a user establishes a locally authenticated identity on a server.
Each login has one login name.
login name. A user name associated with a session.
logon sequence. The process through which the HP NonStop™ server to be managed is
determined, the security constraints to interact with that server are met, and a
connection with that server is established.
low PIN. A PIN in the range 0 through 254.
main memory. Data storage, specifically the chips that store the programs and data
currently in use by a processor.
memory-exact point. A potential breakpoint location within an accelerated object file at
which the values in memory (but not necessarily the values in registers) are the same
as they would be if the object file were running in TNS interpreted mode or on a TNS
system. Most source statement boundaries are memory-exact points. Complex
statements might contain several such points: at each function call, privileged
instruction, and embedded assignment. Contrast with register-exact point and
nonexact point
.
message system. A set of operating system procedures and data structures that handles
the mechanics of exchanging messages between processes.
MIPS Computer Systems, Incorporated. RISC processor manufacturer.
MIPS region of a TNS object file. The region of a TNS object file that contains MIPS
instructions and the tables necessary to execute the instructions in accelerator mode
on a TNS/R system. Accelerator creates this region and writes it into the TNS object
file. Contrast with Intel® Itanium® instruction region.
MIPS RISC instructions. Register-oriented 32-bit machine instructions in the MIPS-1 RISC
instruction set that are native to and directly executed on TNS/R systems. MIPS RISC
instructions do not execute on TNS systems and TNS/E systems. Contrast with TNS
instructions and Intel® Itanium® instructions.