pTAL Guidelines for TAL Programmers

pTAL Guidelines for TAL Programmers—527256-002
Glossary-1
Glossary
accelerate. To speed up emulated execution of a TNS object file by applying the
Accelerator for TNS/R system execution or the TNS Object Code Accelerator (OCA)
for TNS/E system execution before running the object file.
accelerated mode. See TNS accelerated mode.
accelerated object code. The MIPS RISC instructions (in the MIPS region) that result from
processing a TNS object file with the Accelerator or the Intel® Itanium® instructions (in
the Itanium instruction region) that result from processing a TNS object file with the
Object Code Accelerator (OCA).
accelerated object file. A TNS object file that, in addition to its TNS instructions (in the
TNS region) and symbol information (in the symbol region), has been augmented by
the Accelerator with equivalent but faster MIPS RISC instructions (in the MIPS region),
the Object Code Accelerator (OCA) with equivalent but faster Intel® Itanium®
instructions (in the Itanium instruction region), or both.
Accelerator. A program optimization tool that processes a TNS object file and produces an
accelerated object file that also contains equivalent MIPS RISC instructions (called the
MIPS region). TNS object code that is accelerated runs faster on TNS/R processors
than TNS object code that is not accelerated. See also TNS Object Code Accelerator
(OCA).
CISC. See complex instruction set computing (CISC).
complex instruction set computing (CISC). A processor architecture based on a large
instruction set, characterized by numerous addressing modes, multicycle machine
instructions, and many special-purpose instructions. Compare to reduced instruction
set computing (RISC) and explicitly parallel instruction set computing (EPIC).
EPIC. See explicitly parallel instruction set computing (EPIC)
.
EpTAL compiler. The compiler that takes pTAL source code as input and generates either
TNS/R native object code
or TNS/E native object code. Compare to pTAL compiler and
TAL compiler.
explicitly parallel instruction set computing (EPIC). A processor architecture in which
the instruction stream encodes what can be done in parallel (so that the hardware
need not do this). Compare to complex instruction set computing (CISC) and reduced
instruction set computing (RISC).
HP Transaction Application Language (TAL). A high-level, block-structured language
used to write system software and transaction-oriented applications on NonStop
operating systems.