System Generation Manual for G-Series RVUs

Reading the CONFLIST Report

System Generation Manual for G-Series RVUs—523407-001

5-19

SIV Listing

The System Interrupt Vector (SIV) listing is a table of system interrupt vector addresses

for the interrupt handlers located in memory. The column headings and their meanings

are as follows:

The following is a portion of a System Interrupt Vector listing for a TNS/R system.

System Image List

Finally, SYSGENR produces a system image list for each processor, showing the

processes and memory use for that processor. The column headings and their

meanings are as follows:

You can use this system image list along with PEEK to ensure proper allocation of

processes and memory in a processor. The main memory size of each processor must

equal or be greater than the “MINIMUM PAGES OF MEMORY REQUIRED” given at

the end of the listing for that processor.

Column Heading Meaning

IH A list of the 24 interrupt handlers.

SIV_L The KSEG0 address of the regsave area for the interrupt handler.

SIV_SP The KSEG0 address for the pointer into its interrupt stack.

SIV LISTING 15 APR 1996 11:19

PAGE 748

IH SIV_L SIV_SP

SIV [ 0 ] 8002.2C04 80A4.DF40

SIV [ 1 ] 8002.2CBC 80A4.E040

SIV [ 2 ] 8002.2D74 80A4.E408

SIV [ 3 ] 8002.314C 80A4.E708

…

SIV [ 22 ] 8002.4A14 80A5.5890

SIV [ 23 ] 8002.4ADC 80A5.58D0

Column Heading Meaning

# The process ID number.

PROCESS NAME The internal entry point name.

DATA SEG The data segment number.

DATA SEG ADDR The data segment location within the OSIMAGE file.

CODE SEG The code segment number.

#SEGS The number of nonaccelerated or native code segments

used.

#AXLSEGS The number of accelerated code segments used.