Memory technology evolution: an overview of system memory technologies, 9th edition

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Memory technology evolution: an overview

of system memory technologies

Technolo

y brief, 9

edition

Introduction ......................................................................................................................................... 2

Basic DRAM operation ......................................................................................................................... 2

DRAM storage density and power consumption ................................................................................... 4

Memory access time ......................................................................................................................... 4

System bus timing ............................................................................................................................. 4

Memory bus speed ........................................................................................................................... 5

Burst mode access ............................................................................................................................ 5

SDRAM technology .............................................................................................................................. 5

Bank interleaving ............................................................................................................................. 6

Increased bandwidth ........................................................................................................................ 6

Registered SDRAM modules .............................................................................................................. 6

DIMM configurations ........................................................................................................................ 6

DIMM error detection/correction technologies ..................................................................................... 8

Memory protection technologies ...................................................................................................... 10

Advanced memory technologies .......................................................................................................... 12

Rambus DRAM ............................................................................................................................... 12

Double Data Rate SDRAM technologies ............................................................................................ 12

Fully-buffered DIMMs ...................................................................................................................... 15

Importance of using HP-certified memory modules in ProLiant servers ....................................................... 18

Conclusion ........................................................................................................................................ 18

For more information .......................................................................................................................... 19

Call to action .................................................................................................................................... 19

Summary of content (19 pages)

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Memory technology evolution: an overview of system memory technologies Technology brief, 9th edition Introduction ......................................................................................................................................... 2 Basic DRAM operation ......................................................................................................................... 2 DRAM storage density and power consumption .....................................................................
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Introduction This paper gives you an overview of the memory technologies that we use in HP ProLiant servers, and describes how we evaluate these technologies. It also briefly summarizes the evolution of server memory and explores the different dynamic random access memory (DRAM) technologies. Processors use system memory to store the operating system, applications, and data they use and manipulate. As a result, speed and bandwidth of the system memory controls application performance.
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The memory subsystem operates at the memory bus speed. When the memory controller accesses a DRAM cell, it sends electronic address signals that specify the target cell’s row address and column address. The memory controller sends these signals to the DRAM chip through the memory bus, which consists of: • The address/command bus • The data bus The data bus is a set of lines, also known as traces, that carry the data to and from the DRAM chip. Each trace carries one data bit at a time.
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DRAM storage density and power consumption DRAM storage capacity is inversely proportional to the cell geometry. In other words, the storage density increases as the cell geometry shrinks. Over the past few years, capacity has expanded from 1 kilobit (Kb) per chip to 2 gigabit (Gb) per chip. We expect that the capacity will soon grow to 4 Gb per chip. The industry-standard operating voltage for computer memory components was originally 5 volts.
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cycles for data or instructions. In contrast, synchronized components know which clock cycle will make data available, eliminating these timing delays. Memory bus speed DRAM speed is not the same as the true speed, or frequency, of the memory subsystem. The memory subsystem operates at the memory bus speed, which may not be the same frequency (in MHz) as the main system bus clock. Memory timing and maximum DRAM speed control memory subsystem speed.
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addition to synchronous operation and burst mode access, SDRAM has other features that accelerate data retrieval and increase memory capacity: • Multiple memory banks • Greater bandwidth • Register logic chips. Bank interleaving SDRAM divides memory into two to four banks for simultaneous access to more data. This division and simultaneous access is interleaving.
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Single-rank, dual-rank, and quad-rank DIMMs Along with single-sided and double-sided configurations, we classify DIMMs by rank. A memory rank is an area or block of 64-bits (72 bits for ECC memory) created by using some or all of the DRAM chips on a DIMM. A single-rank ECC DIMM (x4 or x8) uses all of its DRAM chips to create a single block of 72 bits, and all the chips are activated by one chip-select (CS) signal from the memory controller (top two illustrations in Figure 5).
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To prevent such memory-related problems, we advise our customers to use only HP-certified DIMMs, which are available in the memory option kits for each ProLiant server (see the “Importance of using HP-certified memory modules in ProLiant servers” section). Another important difference between single-rank and dual-rank DIMMs is cost. Memory costs generally increase with DRAM density. For example, the cost of an advanced, high-density DRAM chip usually runs more than twice that of a conventional DRAM chip.
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all HP ProLiant servers. ECC detects both single-bit and multi-bit errors in a 64-bit data word; it corrects single-bit errors. ECC encodes information in a block of 8 bits to recover a single-bit error. When the DIMM writes data to memory, ECC uses a special algorithm to generate values called check bits. The algorithm adds the check bits together to calculate a checksum, which it stores with the data.
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Figure 7. Advanced ECC Since each ECC device can correct single-bit errors, Advanced ECC can correct a multi-bit error that occurs within one DRAM chip. As a result, Advanced ECC gives you protection from device failure (Table 1). Table 1.
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correctable memory errors, the channel goes off line and the system copies data to the spare channel. This prevents data corruption, a server crash, or both, and you can replace the defective DIMM at your convenience during a scheduled shutdown. This also maintains server availability and memory reliability without service intervention or server interruption.
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Advanced memory technologies Advanced memory technologies fill the growing performance gap between memory and processor despite the gains made possible by SDRAM. The industry has developed several technologies to boost system performance using the latest high-speed processors (Figure 8). Figure 8. Peak bandwidth comparison of SDRAM and advanced SDRAM technologies Rambus DRAM Rambus DRAM (RDRAM) is a memory technology introduced in the late 1990s to achieve faster memory throughput than SDRAM.
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data bus, and Stub-Series Terminated Logic_2 (SSTL_2) low-voltage signaling. At 400 MHz, DDR increases memory bandwidth to 3.2 GB/s—400% more than original SDRAM. Prefetching SDRAM transfers one bit per clock cycle from the memory cell array to the I/O buffer or data queue (DQ). The I/O buffer releases one bit to the bus per pin and clock cycle (on the rising edge of the clock signal).
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Figure 9. DDR2 DIMM with 240-pin interface DDR3 DDR3, the third-generation of DDR SDRAM technology, makes further improvements in bandwidth and power consumption. DDR3 manufacturers began fabrication using with 90 nm technologies. With increasing production volumes, they are moving toward 70 nm technology. DDR3 operates at clock rates from 400 MHz to 1066 MHz with theoretical peak bandwidths ranging from 6.40 GB/s to 17 GB/s.
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industry based the DDR-SDRAM naming convention on the actual peak data transfer rate in MB/s. For example, PC266 is equivalent to PC2100 (64 bit * 2 * 133 MHz = 2.1 GB/s or 2100 MB/s). DDR3 SDRAM DIMM manufacturers produce two types of DIMMs: Unbuffered DIMMs (UDIMM) and Registered DIMMs (RDIMM). UDIMMs are the most basic type of memory module and offer a lower latency and low power consumption but are limited in capacity. An E suffix in the manufacturer’s module name identifies Unbuffered DIMMs with ECC.
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Figure 11. Stub-bus topology Each stub-bus connection creates resistance that can degrade signal integrity. In addition, each DIMM creates an electrical load on the bus. Adding more DIMMs increases the electrical load. As the bus speed increases, these factors decrease the number of supportable DIMMs per channel. For example, Figure 12 shows the number of loads supported per channel at data rates ranging from PC 100 to DDR3 1600.
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connect the memory controller to an Advanced Memory Buffer (AMB) chip that resides on each FB-DIMM, creating a point-to-point architecture. The outbound links transmit commands and write data to the FBDIMMs while the inbound links transmit read data back to the memory controller. The clock signal travels over a different set of pins. In addition to communicating over the outbound lanes, the memory controller communicates configuration information with each AMB over the System Management bus or SMBus.
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Importance of using HP-certified memory modules in ProLiant servers There are several reasons why you should use only HP memory option kits to replace or add memory in ProLiant servers. First, not all DIMMs are created equal. They can vary greatly in quality and reliability. In the highly competitive memory market, some third-party memory resellers forego the level of qualification and testing needed for servers because it adds to the price of DIMMs.
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For more information For additional information, refer to the resources listed below. Resource description Web address JEDEC Web site http://www.jedec.org HP ProLiant Server Memory web page http://h18004.www1.hp.com/products/servers/options/memorydescription.html DDR3 memory technology, technology brief http://h20000.www2.hp.com/bc/docs/support/SupportManual /c02126499/c02126499.pdf Call to action Send comments about this paper to TechCom@HP.