Memory technology evolution: an overview of system memory technologies, 9th edition

Single-rank, dual-rank, and quad-rank DIMMs
Along with single-sided and double-sided configurations, we classify DIMMs by rank. A memory rank is an
area or block of 64-bits (72 bits for ECC memory) created by using some or all of the DRAM chips on a
DIMM.
A single-rank ECC DIMM (x4 or x8) uses all of its DRAM chips to create a single block of 72 bits, and all
the chips are activated by one chip-select (CS) signal from the memory controller (top two illustrations in
Figure 5). A dual-rank ECC DIMM produces two 72-bit blocks from two sets of DRAM chips on the DIMM,
requiring two chip-select signals. The chip-select signals are staggered so that both sets of DRAM chips do
not contend for the memory bus at the same time. Quad-rank DIMMs with ECC produce four 72-bit blocks
from four sets of DRAM chips on the DIMM, requiring four chip-select signals. Like dual-rank DIMMs, the
memory controller staggers the chip-select signals.
Figure 5. Single-sided and double-sided DDR SDRAM DIMMs and corresponding DIMM rank
Sin
g
le-sided,
single-rank
Side 1, 4b DRAM x9
Side 1(only), 8b DRAM x9
72b CS
72b CS
Side 2, 4b DRAM x9
Double-sided,
single-rank
Double-sided,
dual-rank
Side 1, 8b DRAM x9*
Side 1
,
8b DRAM x18*
Side 2, 8b DRAM x9*
Side 2
,
8b DRAM x18*
72b CS (2)
Double-sided,
quad-rank
72b CS (4)
* Actual DRAM configuration can vary depending
on DRAM density and configuration
Memory ranks have become more important because of new chipset and memory technologies and larger
memory capacities. Dual-rank DIMMs improve memory capacity by placing two single-rank DIMMs on one
module. The chipset considers each rank as an electrical load on the memory bus. At slower bus speeds,
the number of loads does not degrade bus signal integrity. For faster memory technologies, the chipset can
drive only a certain number of ranks. For example, if a memory bus has four DIMM slots, the chipset may
be capable of supporting only two dual-rank DIMMs or four single rank DIMMs. If you install two dual-rank
DIMMs, then the last two slots must remain empty. To compensate for the reduction in the number of slots,
chipsets now use multiple memory buses.
If the total number of ranks in the populated DIMM slots exceeds the maximum number of loads, the chipset
can support, the server may not boot properly or it may not operate reliably. Some systems check the
memory configuration while booting to detect invalid memory bus loading. If the system detects an invalid
memory configuration, it stops the boot process to avoid unreliable operation.
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