HP F8 Architecture Technology Brief

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HP F8 Architecture

Table of Contents

April 2003

HP Industry

Standard Servers

Technology Brief

TC0304013TB

Abstract.................................................................................................................... 2

Introduction .............................................................................................................. 2

Need for F8 Architecture ........................................................................................... 2

Overview of F8 Chipset............................................................................................. 4

Hot-Plug RAID Memory ............................................................................................. 5

Memory Configuration.......................................................................................................5

RAID Memory Striping .......................................................................................................5

Hot-Plug Memory Capabilities............................................................................................6

Benefits of Data Protection With RAID ................................................................................7

Error Detection and Correction ...........................................................................................7

Architectural Differences From Storage Subsystem RAID......................................................8

F8 Crossbar Switch ................................................................................................... 8

Buffer Design.....................................................................................................................8

Multiport Design................................................................................................................9

Cache Coherency Filter ......................................................................................................9

Optimizing Cross-bus Traffic ...........................................................................................10

I/O Subsystem........................................................................................................ 11

PCI Mode ........................................................................................................................11

PCI-X Mode.....................................................................................................................11

Xeon MP Processor Subsystem ................................................................................ 12

Hyper-Threading Technology ...........................................................................................12

Frequency and Full-Speed Cache.....................................................................................13

Processor and I/O Bus Design..........................................................................................13

SIMD Instructions.............................................................................................................13

Out-of-order Execution ....................................................................................................13

Branch Prediction ............................................................................................................13

Conclusion.............................................................................................................. 14

Feedback................................................................................................................ 14

Summary of content (14 pages)

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HP Industry Standard Servers April 2003 HP F8 Architecture Technology Brief TC0304013TB Table of Contents Abstract.................................................................................................................... 2 Introduction .............................................................................................................. 2 Need for F8 Architecture ........................................................................................... 2 Overview of F8 Chipset .......
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HP F8 Architecture Abstract HP has developed an 8-way multiprocessing architecture that will meet or exceed the greatly increased bandwidth demands of high-end peripherals and the Intel Xeon MP processors. The HP F8 chipset provides key functionality, such as Hot Plug RAID Memory, that was previously unavailable within industry-standard servers.
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HP F8 Architecture Specifically, the Profusion 8-way architecture has a bus bandwidth of 800 MB/s for the dedicated processor and I/O buses. The F8 architecture is capable of a bandwidth that is four times greater: 3.2 gigabytes per second (GB/s) for each processor bus and for the I/O subsystem (Figure 1). Figure 1. Bandwidth comparison between Profusion and F8 architectures to Memory... Aggregate Memory Bandwidth: 8.5 GB/s ry mo Me idth X w >5 and B 3.2 GB/s to Memory...
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HP F8 Architecture Overview of F8 Chipset The backbone of the new 8-way architecture is the F8 chipset designed by HP. It includes five memory controllers with patent-pending HP Hot-Plug RAID Memory and a multiported crossbar switch (Figure 2). Product implementations will vary. The F8 chipset supports: • An aggregate memory bandwidth of 8.5 GB/s using five separate memory controllers with 400 mega transfers per second3 (MT/s) point-to-point connections.
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HP F8 Architecture Hot-Plug RAID Memory Probably the most significant improvement in the F8 architecture is the addition of Hot-Plug RAID Memory, which increases availability, scalability, and fault tolerance in industrystandard servers. The F8 memory controllers provide greatly increased memory bandwidth to handle the Xeon MP bus speeds, which are four times greater than the P6 bus speeds. The F8 architecture supplies hot-add, hot-replace, and hot-upgrade capabilities.
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HP F8 Architecture remaining four cartridges if the data from any DIMM is incorrect or if any cartridge is removed. Figure 4. Data striping across one of the channels in HP Hot Plug RAID Memory Cache line Cartridge 1 A1 B1 C1 D1 Cartridge 2 A2 B2 C2 D2 Cartridge 3 A3 B3 C3 D3 Cartridge 4 Parity Cartridge A4 A parity B4 C4 D4 B parity C parity D parity Because one memory cartridge is dedicated to storing parity information, the architecture has the effective bandwidth of four memory controllers, or 8.
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HP F8 Architecture read. Errors found will be reported to the system. If the verify fails, the system continues to operate in non-redundant mode and the new memory will not be brought online until the problem is corrected. Hot-add and hot-upgrade capabilities allow a user to scale up a computer system as needed by adding or exchanging DIMMs in a memory cartridge while the system is operating.
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HP F8 Architecture Architectural Differences From Storage Subsystem RAID The technology used in HP Hot-Plug RAID Memory is conceptually similar to RAID technology that provides fault tolerance and high availability in storage subsystems for servers. However, there are some key performance and implementation differences between Hot-Plug RAID Memory and typical storage subsystem RAID.
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HP F8 Architecture crossbar switch are distributed so that the data is stored closest to where it enters the application-specific integrated circuit (ASIC). Figure 5. The F8 crossbar switch uses distributed buffers and multiple read and write ports. 8.5 GB/s Memory Network Interface Left Processor Bus Processor Buffer 3.2 GB/s Processor Buffer Memory Buffer 3.2 GB/s Right Processor Bus Read Ports I/O Buffer Write Port 3.
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HP F8 Architecture Figure 6. Comparison of a snoop cycle with and without a cache coherency filter Processors Processors Remote Bus Host Controller Processors Snoop cycle without filter goes to remote bus Processors Remote Bus F8 Crossbar Switch Snoop cycle with filter stays off remote bus Cache Coherency Filter The F8 chipset uses a cache coherency filter to reduce the number of snoop cycles on the remote processor bus. The cache coherency filter is also known as a cache accelerator.
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HP F8 Architecture The F8 chipset optimizes cross-bus traffic by incorporating a patent-pending Guaranteed Snoop Access algorithm. The algorithm defers fewer requests than Profusion does, thus reducing the amount of traffic on the processor bus. The F8 chipset defers cycles only when necessary to prevent a livelock situation5, yet maintains the order and coherency of the requests.
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HP F8 Architecture PCI-X improves performance over conventional PCI as a result of two primary differences: higher clock frequencies made possible by a register-to-register protocol and new protocol enhancements, such as split transactions, to make the bus more efficient. The register-toregister protocol eases the timing constraints by allowing an entire clock cycle for the decode logic to occur.
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HP F8 Architecture logical processors just as it would in a traditional multiprocessor system. The execution core processes instructions in an order determined by dependencies in the data and availability. Therefore, the processor is allowed to execute instructions in the order that will yield the best overall performance. For more information, read the HP technology brief entitled “Intel® Hyper-Threading Technology,” Document Number TC0300306, available on the HP website: www.hp.com.
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HP F8 Architecture Conclusion On December 6, 2002, HP announced a new TPC-C performance mark for 8-processor systems.8 Running Microsoft® Windows® .NET Datacenter Server and Microsoft SQL Server 2000 Enterprise Edition SP3, the ProLiant DL760 G2 server—HP’s first implementation of the F8 architecture—performed 115,025 tpmC while supporting 92,000 users.