HP F8 Architecture Technology Brief

HP F8 Architecture
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Figure 6. Comparison of a snoop cycle with and without a cache coherency filter
The F8 chipset uses a cache coherency filter to reduce the number of snoop cycles on the
remote processor bus. The cache coherency filter is also known as a cache accelerator. It
holds the addresses of data stored in all of the L2 processor caches, as well as information
about the state of the data. For example, the state information may describe whether the
data is owned by a particular L2 cache or shared between multiple caches.
The cache coherency filter also acts as a filter for the I/O bus, keeping track of which cache
lines are owned on the I/O bus for the PCI devices. When a processor requests a cache
line, the crossbar switch snoops the I/O filter to determine if that cache line resides in one of
the PCI bridges on the I/O bus. If the cache line is not present in one of the bridges, then no
transaction is run on the I/O bus. This reduces snoop traffic on the I/O bus whenever a
processor requests data.
Optimizing
Cross-bus Traffic
The F8 chipset alleviates some inefficiency that the Profusion chipset has when snoop traffic
must cross to the remote processor bus. When a processor requests data, the Profusion
chipset checks the cache coherency filter to determine the specific location of the data it
needs. If the data is located in an L2 cache on the remote bus, the chipset snoops the remote
bus to obtain the data, causing cross-bus traffic. In the Profusion chipset, a read request that
requires a snoop cycle on the remote bus is automatically deferred,
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causing a reply to be
sent at a later time. This situation generates two cycles on the processor bus for every single
read request.
Host Controller
Snoop cycle without filter
goes to remote bus
F8 Crossbar Switch
Snoop cycle with filter
stays off remote bus
Processors
Cache
Coherency Filter
Remote Bus
Remote Bus
Processors
Processors
Processors
Host Controller
Snoop cycle without filter
goes to remote bus
F8 Crossbar Switch
Snoop cycle with filter
stays off remote bus
ProcessorsProcessors
Cache
Coherency Filter
Cache
Coherency Filter
Remote BusRemote Bus
Remote BusRemote Bus
ProcessorsProcessors
ProcessorsProcessors
ProcessorsProcessors
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A deferred request is split into two transactions so that the processor makes a read request and gets off the bus. Then a
reply is sent when the data is available.