Technologies in HP ProLiant G6 c-Class server blades with AMD Opteron™ processors

For applications that cannot take advantage of linear memory configuration, activating memory

interleaving may improve performance. However, reducing the level of interleaving can result in

power savings. System administrators can activate full interleaving or channel only interleaving using

the HP ROM-Based Setup Utility (RBSU).

Memory interleaving breaks memory into 4-KB addressable

entities. Table 1 shows how memory interleaving assigns memory. An application that uses a common

allocation thread will benefit from memory interleaving.

Table 1. Memory interleaving node addressing

Node Sequential Address Sequential Address

0 0 – 4095 16384 – 20479

1 4096 – 8191 20480 – 24575

2 8192 – 12287 24576 – 28671

3 12288 – 16383 Process continues until all memory has been assigned

HP ProLiant c-Class Server Blades with AMD processors support PC2 Registered double data rate

(DDR2) DIMMs. DDR2 memory devices operate at 1.8V and use high clock frequencies to increase

data transfer rates and on-die termination control to improve signal quality. For example, at a clock

frequency of 400 MHz, the data transfer rate is 800 megatransfers per second (MT/s), which

translates to a memory bandwidth of 6400 MB/s per DIMM. The memory will operate at 800 MHz

with 4 or fewer DIMMs per processor. Because of the electrical load on the bus, when 6 or 8 DIMMS

are installed on a single processor, the memory bus for that processor will be clocked down to

667 MHz or 533 MHz respectively.

I/O technologies

HP ProLiant c-Class Server Blades support PCI Express (PCIe), serial attached SCSI (SAS), serial ATA

(SATA) I/O technologies, Multifunction 1 Gb or 10 Gb Ethernet, 4 Gb Fibre Channel, and 4X DDR

(20 Gb) InfiniBand.

PCI Express technology

The PCI Express (PCIe) serial interface provides point-to-point connections between the chipset I/O

controller hub and I/O devices. Each PCIe serial link consists of one or more dual-simplex lanes. Each

lane contains a send pair and a receive pair to transmit data at the signaling rate in both directions

simultaneously (Figure 6). ProLiant server blades with AMD processors support PCIe 1.0 slots, which

have a signaling rate of 2.5 Gb/s per direction per lane. After accounting for 20 percent

serializing/deserializing encoding overhead, the resulting effective maximum bandwidth is 2 Gb/s

(250 MB/s) per direction per lane. Therefore, a x4 link with 4 send and receive pairs has an effective

bandwidth of 2 GB/s. A x8 link has an effective bandwidth of 4 GB/s. This flexibility allows slower

devices to transmit on a single lane with a relatively small number of pins while faster devices can

transmit on more lanes as required.

Additional information is provided in the “HP ROM-Based Setup Utility User Guide”:

http://h20000.www2.hp.com/bc/docs/support/SupportManual/c00191707/c00191707.pdf.

For additional information, refer to the HP technology brief titled “Memory technology evolution: an overview of

system memory technologies"

http://h20000.www2.hp.com/bc/docs

/support/SupportManual/c00256987/c00256987.pdf.