Double Data Rate SDRAM: Fast Performance at an Economical Price

Double Data Rate SDRAM: Fast

TECHNOLOGY BRIEF (cont.) Performance at an Economical Price

Doc Number TC020603TB

THE F UTURE OF DDR SDRAM

The JEDEC Solid State Technology Association is currently developing the next-generation DDR

SDRAM technology, called DDR SDRAM II. This next generation technology will be backward

compatible with DDR SDRAM but not with standard SDRAM. DDR SDRAM II will improve bus

utilization to double the bandwidth, yielding a theoretical peak bandwidth of 6.4 GB/s (see

Figure 7). It is also expected to provide improvements in cost, power requirements, I/O, packaging,

and clocking.

Figure 7. Comparison of bandwidths for standard SDRAM,

Rambus DRAM, DDR SDRAM, and DDR SDRAM II.

CONCLUSION

SDRAM continues to provide good performance in servers and workstations; but for memory

subsystem performance to keep up with future processors, the memory bus bandwidth must

continue to increase. Compared to revolutionary memory technologies, DDR SDRAM delivers

faster performance at lower cost, which is necessary for industry-wide adoption. While the basic

principle of DDR SDRAM is simple—transfer data on both the rising and falling edges of the

system clock signal—the reality is that system designers had to solve several technical issues

regarding signal integrity at the higher bus speeds. System designers were successful; however,

the technical advances that enable DDR SDRAM to achieve higher data rates also make it

incompatible with standard SDRAM. The next version, DDR SDRAM II, promises to push the

performance of the memory subsystem to even higher levels. DDR SDRAM II will be backward

compatible with DDR SDRAM and will improve bus utilization to increase performance and

bandwidth, yielding a theoretical peak bandwidth of 6.4 GB/s.