Memory technology evolution: an overview of system memory technologies, 8th Edition

Parity and ECC DIMMs
The ninth DRAM chip on one side of a DIMM is used to store parity
or ECC bits. With parity, the memory controller is capable of
detecting single-bit errors, but it is unable to correct any errors.
Also, it cannot consistently detect multiple-bit errors. With ECC, the
memory controller is capable of detecting and correcting single bit
errors and multiple-bit errors that are contiguous. Multiple-bit
contiguous errors occur when an entire x4 or x8 chip fails. The
chipset (memory controller) is also capable of detecting double-bit
errors that are not contiguous. The chipset halts the system and
logs an error when uncorrectable errors are detected. Servers use
ECC DIMMs to improve availability and reliability.
Memory ranks are not new, but their role has become more critical with the advent of new chipset
and memory technologies and growing server memory capacities. Dual-rank DIMMs improve memory
density by placing the components of two single-rank DIMMs in the space of one module. The chipset
considers each rank as an electrical load on the memory bus. At slower bus speeds, the number of
loads does not adversely affect bus signal integrity. However, for faster memory technologies such as
DDR2-667, there are a maximum number of ranks that the chipset can drive. For example, if a
memory bus on a server has four DIMM slots, the chipset may only be capable of supporting two
dual-rank DIMMs or four single rank DIMMs. If two dual-rank DIMMs are installed then, the last two
slots must not be populated. To compensate for the reduction in the number of DIMM slots on a bus at
higher speeds, modern chipsets employ multiple memory buses.
If the total number of ranks in the populated DIMM slots exceeds the maximum number of loads the
chipset can support, the server may not boot properly or it may not operate reliably. Some systems
check the memory configuration while booting to detect invalid memory bus loading. When an
invalid memory configuration is detected, the system stops the boot process, thus avoiding unreliable
operation.
To prevent this and other memory-related problems, customers should only use HP-certified DIMMs
available in the memory option kits for each ProLiant server (see the “Importance of using HP-certified
memory modules in ProLiant servers” section).
Another important difference between single-rank and dual-rank DIMMs is cost. Typically, memory
costs increase with DRAM density. For example, the cost of an advanced, high-density DRAM chip is
typically much higher (more than 2x) than that of a conventional DRAM chip. Because large capacity
single-rank DIMMs are manufactured with higher-density DRAM chips, they typically cost more than
dual-rank DIMMs of comparable capacity.
Rank interleaving
As described previously, bank interleaving allows the processor to initiate an access to one memory
bank before the previous access to a different bank has been completed, resulting in continuous data
flow. Essentially, dual-rank and quad-rank DIMMs increase the number of “banks” available for
interleaving. Rank interleaving can result in improved system performance for memory-intensive
applications such as high-performance computing and video rendering.
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