Technologies for the ProLiant ML570 G4 and ProLiant DL580 G4 servers

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Technologies for the ProLiant ML570 G4

and ProLiant DL580 G4 servers

technology brief

Abstract.............................................................................................................................................. 3

Introduction......................................................................................................................................... 3

Processor architecture........................................................................................................................... 3

64-bit architecture............................................................................................................................ 3

Dual-core architecture....................................................................................................................... 4

Xeon dual-core processors................................................................................................................. 4

Memory architecture ............................................................................................................................ 5

Background: memory banks and ranks ............................................................................................... 5

Intel E8501 chipset .......................................................................................................................... 6

Partitioning for electrical isolation................................................................................................... 6

Maximum memory configurations................................................................................................... 7

High-performance memory ................................................................................................................ 7

DDR-2 memory............................................................................................................................. 7

Memory interleaving..................................................................................................................... 8

Errors in memory............................................................................................................................ 11

High-availability memory technologies.............................................................................................. 11

Supported Advanced Memory Protection technologies........................................................................ 11

Architecture trade-offs with a large memory footprint .......................................................................... 12

Updated I/O technologies.................................................................................................................. 12

Serial Attached SCSI ...................................................................................................................... 12

Small Form Factor hard drives ......................................................................................................... 13

The Smart Array SAS P400 Controller .............................................................................................. 13

Expansion slot options .................................................................................................................... 14

Updated networking technologies........................................................................................................ 14

TCP Offload Engine........................................................................................................................ 14

Receive Side Scaling (RSS).............................................................................................................. 15

iSCSI ............................................................................................................................................ 15

Improved manageability through iLO 2 ................................................................................................ 15

Mechanical design for serviceability .................................................................................................... 16

Common components ..................................................................................................................... 16

ProLiant ML570 G4........................................................................................................................ 18

Summary of content (22 pages)

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Technologies for the ProLiant ML570 G4 and ProLiant DL580 G4 servers technology brief Abstract.............................................................................................................................................. 3 Introduction......................................................................................................................................... 3 Processor architecture..................................................................................................
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ProLiant DL580 G4 ............................................................................................................................ 19 Conclusion........................................................................................................................................ 21 For more information.......................................................................................................................... 21 Call to action .......................................................
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Abstract The fourth generation of HP ProLiant 500 series servers—the HP ProLiant ML570 G4 and the HP ProLiant DL580 G4 servers—can transition easily from 32-bit to 64-bit x86 processing. The architecture for these servers uses the Intel® 64-bit Xeon™ dual-core processor designed to operate in either 32-bit or 64-bit mode, depending on the application and operating system (OS) used.
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Dual-core architecture Dual-core processors are two separate microprocessors on the same physical die. When combined with Intel Hyper-Threading technology, each dual-core processor has the ability to execute four simultaneous threads. By increasing the number of processors available to the operating system, multiple threads can be executed more efficiently. In addition, a dual-core processor uses less power than two equivalent single-core processors and therefore produces less heat.
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Intel first released the Execute Disable Bit functionality with the Itanium® processor family. The technology allows the processor to classify areas of memory that cannot execute application code. When combined with OS support, this helps to prevent certain classes of malicious buffer overflow attacks. Intel Execute Disable bit is supported by Microsoft Windows Server 2003 SP1, Microsoft Windows XP SP2, SuSe Linux Enterprise Server 9.2, or Red Hat Enterprise Linux 3 Update 3.
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Intel E8501 chipset The E8501 chipset has a high-availability memory subsystem that consists of the north bridge [TNB] and the XMB memory controller. The E8501 chipset supports dual-core versions of Intel processors and has the important feature of using two separate front side buses to connect to the processors (Figure 2). Each north bridge can connect to up to four memory boards, and each memory board includes an XMB memory controller chip.
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noise is increasingly important as bus speeds increase and bus signals become more susceptible to slight differences in voltages. Figure 3. Partitioning of the TNB and XMB chips to reduce power noise and crosstalk issues Maximum memory configurations Each XMB memory controller supports eight electrical loads. A single-rank DIMM is considered one electrical load; a dual-rank DIMM is two electrical loads.
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In DDR memory, an external termination resistor is added to the system board to improve signal quality and reduce noise for the memory signals. This reduces the likelihood of a signal reflecting, or bouncing back, toward the driving source. DDR-2 memory, on the other hand, moves this resistor into the silicon of the memory itself. This reduces signal reflection and therefore improves signal quality (Figure 4).
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Figure 5. Interleaving between the two channels of memory: 64-bits go to memory controller (channel) 1, the next 64 bits to go to memory controller 2, and so on. XMB rank interleaving Rank interleaving within the XMB groups several ranks of memory together so that cache lines are sequentially read or written across the entire group. For example, suppose that bank A and bank B are interleaved together. (In this example, all contain single-rank DIMMs, so bank A is equivalent to a rank.
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Interleaving across XMB memory controllers Because there are up to four XMB memory controllers (one per memory board), the north bridge device also splits requested cache lines among all memory controllers. This type of interleaving is automatically enabled when using more than one memory board (if hot-add is disabled).
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Errors in memory As memory capacity grows, it becomes statistically more likely that memory errors will occur: both hard and soft errors. Errors can be categorized as either correctable or uncorrectable. In the ProLiant ML570 G4 and the DL580 G4 servers, the memory controller calculates check bits every time it writes to memory. When memory is read, it re-calculates those check bits from the data stored in the DRAM devices and compares the re-calculated check bits to the stored check bits.
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Table 1. Functionality comparison of four memory protection options Memory Option Hot-add support Hot-replace support Memory available to OS Advanced ECC Yes No 100% Online Spare No No Varies Mirroring No Yes 50% RAID No Yes 75% Architecture trade-offs with a large memory footprint Three ProLiant 500 series servers—the ProLiant ML570 G4, ProLiant DL580 G4, and ProLiant DL585 G2—all have large memory footprints and high performance architectures.
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For more information about SAS technology, refer to the HP technology brief titled “Serial Attached SCSI technology”. 8 Small Form Factor hard drives SFF drives offer several advantages over 3.5-inch drives. The smaller physical size of the drives increases the number of gigabytes per U that can be implemented in a server rack. SFF drives have been shown to be more reliable than their larger counterparts, largely due to the use of smaller parts and better control of vibration.
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Expansion slot options The ML570 G4 is optimized for expansion, and the DL580 G4 is optimized for efficient use of space in a server rack. Because of the different design goals, the two servers offer different expansion slot configurations. The ML570 G4 has the following expansion slots: • Four 64-bit/100-MHz PCI-X slots • Six PCI Express x4 slots An x4-x8 PCI Express bus expander is available for converting two PCI Express x4 slots into one PCI Express x8 slot.
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Receive Side Scaling (RSS) The Network Driver Interface Specifications (NDIS) define a common Application Programming Interface for network interface cards on Microsoft operating systems. Early versions of NDIS did not differentiate between computers with single or multiple CPUs. The result was that one CPU was forced to handle the entire network processing load. NDIS v6.0 includes support for multiple processors. With NDIS v6.
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port with normal traffic. This shared arrangement eliminates the need for an extra network connection for iLO 2. For more information about iLO 2, refer to the HP technology brief titled “Integrated Lights-Out technology: enhancing the manageability of ProLiant servers.” 11 Mechanical design for serviceability The ProLiant ML570 G4 and DL580 G4 servers follow the well-established tradition of excellent mechanical design in ProLiant servers.
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Both servers incorporate a System Insight Display diagnostic display inside the server chassis to provide specific trouble-shooting information (Figures 11 and 12). The display includes LEDs for all major subsystems of the server: PCI-E and PCI-X, memory, processors, redundant fans, overtemp indicator, etc. During normal operations, all of the LEDs are off. An amber LED gives instant visual indication of a fault condition. Figure 11.
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ProLiant ML570 G4 The ProLiant ML570 G4 is compact (6U), lightweight, and almost cable-free. The chassis has two levels, with most of the components on the top level (Figure 13). The components plug into the system board for easy access. The G4 has a front-accessible video port, two front USB ports, and two back USB ports. Figure 13. Internal view of the ProLiant ML570 G4 server. Customer systems may look somewhat different. Administrators will find it easy to service the ML570 G4.
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Figure 14. Center wall in the ML570 G4 server (left). An administrator can remove a portion of the center wall (right) to insert additional VRMs for the processors ProLiant DL580 G4 The ProLiant DL580 G4 provides a compact design for a powerful 4-way server. Like the ProLiant ML570 G4, the DL580 G4 uses plug-in components to eliminate many of the cables.
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The memory modules in the ML580 G4 use the same intuitive locking mechanism as the ML570 G4 to prevent a user from inserting or removing a memory board when it is in the hot, or active, state (Figure 16). Figure 16. Memory modules have a simple locking mechanism that shows whether the memory board can be removed. Locking mechanism The four processors are all housed in a processor cage that is accessible from the front.
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Conclusion The ProLiant ML570 G4 and the ProLiant DL580 G4 servers continue to build on the success of their G3 predecessors, offering both high performance and reliability. The server designs share a common processor and memory architecture that optimizes performance through the use of the latest Intel 64-bit Xeon dual-core processors, fast DDR-2 400 memory, and multiple layers of memory interleaving to reduce latencies in the memory subsystem.
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Call to action Send any comments about this paper to: TechCom@HP.com. © 2006 Hewlett-Packard Development Company, L.P. The information contained herein is subject to change without notice. The only warranties for HP products and services are set forth in the express warranty statements accompanying such products and services. Nothing herein should be construed as constituting an additional warranty. HP shall not be liable for technical or editorial errors or omissions contained herein.