PCI Bus Numbering in a Microsoft Windows NT Environment

PCI Bus Numbering in a Microsoft Windows NT Environment 9
13UK-1200A-WWEN
IMPORTANT: PCI Bus numbers are assigned in “device detection order,” not by slot
numbering.
Dual-Peer PCI Bus – The Compaq ProLiant ML350 server, an example
of the dual-peer PCI architecture, begins the PCI BIOS discovery process
at the Host Bus. When it detects the primary bus, it assigns bus 0 to it.
The PCI BIOS then looks for PCI controllers in slots on the Primary Bus.
PCI controllers detected without bridged PCI buses are assigned bus 0,
the number of the bus in which it is seated. However, if the PCI Bios
detects a bridged PCI device, it increments the bus number to 1 and
assigns that bus number to the PCI bus detected on the bridged
controller. (The next PCI bus detected is assigned a bus number
according to the hardware designation for that system). This discovery
process continues until all PCI controllers and controllers with bridged buses on the Primary Bus
are detected. The PCI BIOS then continues the discovery process on the Secondary Bus until all
PCI buses are detected.
The diagram in Table 3 shows an example of the discovery process. Table 3 does not represent all
the PCI slots and bus assignment possibilities, it depicts snapshot of what occurs when controllers
are loaded in the server.
Table 3. Example of PCI bus number detection order for the ProLiant ML350 (a dual-peer system)
ProLiant ML350 PCI Server Architecture
PCI BIOS Discovery Process
Controller Bus Detection
Order
Bus Number
Assignment
! Host Bus
" Primary PCI Bus First 0
! Slot 1 – Server Feature Card Second 0
! Slot 4 – Empty Third 0
! Slot 5 – Empty Fourth 0
! Slot 6 – NC3131 Fast Ethernet NIC Fifth 1
" Secondary PCI Bus Sixth 5
! Slot 2 – Smart Array 5300 Controller Seventh 5
! Slot 3 – Empty Eighth 5
End of bus
discovery
As indicated in Table 3, the order of detection on the ProLiant ML350 server is Primary Host-to-
PCI Bridge, followed by PCI controllers and bridged controllers on the Primary Bus in slots
beginning at 1, skipping 2-3, and ending at 6. The bus discovery process continues with the
Secondary Host-to-PCI Bridge, followed by PCI controllers and bridged controllers in slots
beginning at 2 and ending at 3.
Highly Parallel PCI Bus – The Compaq ProLiant ML530 provides an example of highly parallel
PCI architecture. This architecture uses dual memory controllers, dual-peer-PCI buses to deliver
optimized multiprocessing support to deliver increased system throughput, and increased system
performance when compared to traditional x86-based designs.
Bus numbers are assigned during
bus initialization according to
predefined hardware designators.
The bus numbers may not appear to
follow a set increment and some
numbers may be skipped.
However, by this method, these
hardware designators prevent
overlays in bus numbering from
occurring.