Technologies for the ProLiant ML570 G3 and ProLiant DL580 G3 Servers Technology Brief

Figure 6. Rank interleaving splits cache lines across a group of memory ranks.
Interleaving across XMB memory controllers
Because there are up to four XMB memory controllers (one per memory board), the north bridge
device also splits requested cache lines among all memory controllers. This type of interleaving is
automatically enabled when using more than one memory board (if hot add is disabled).
For example, if an application requires 40 cache lines of data and the server contains four memory
boards, the north bridge will split those 40 cache lines across the four memory boards in a sequential
fashion: cache line 1 comes from memory board 1, cache line 2 comes from memory board 2, and
so on (Figure 7). Assuming that rank interleaving is also enabled, the memory controller will read the
fifth cache line from the second rank of DIMMs on memory board 1. Distributing the memory reads
and writes across multiple controllers reduces memory access times for individual controllers and
reduces the likelihood of processors waiting on data.
The north bridge has no mechanism for updating the interleaving scheme on-the-fly if new memory
boards are added. Therefore, if hot-add memory is enabled, interleaving cannot be done across
memory controllers and must be disabled.
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The one exception is if all four memory boards are installed and hot-add is enabled: because the system is already fully populated with memory
boards, the north bridge controller can interleave memory across the XMB memory controllers.
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