Technologies for the ProLiant ML570 G3 and ProLiant DL580 G3 Servers Technology Brief
This can result in performance advantages for the 64-bit architectures because of their ability to use
large amounts of memory, such as with intensive floating-point calculations used in scientific and
engineering modeling programs.
For additional information about 64-bit extensions and architecture, see the technology brief
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titled
“
Characterizing x86 processors for industry-standard servers: AMD Opteron and Intel Xeon”
Xeon processor MP
The 64-bit Xeon processor MP comes in two different versions: a version with a 1 MB L2 cache; and a
version with up to 8 MB of L3 cache in addition to the 1 MB L2 cache. Both are built using 90 nm
process technology and use a 166-MHz front side bus which is quad-pumped to 667 MHz, providing
up to 5.3 GB/s of data transfer rates. The processors support IA-32 and the EMT64 instruction set for
running 64-bit applications and operating systems.
As of this writing, the ProLiant ML570 G3 and DL580 G3 platforms support the following processors:
• Xeon MP 3.3 GHz/8 MB L3/1 MB L2
• Xeon MP 3.0 GHz/8 MB L3/1 MB L2
• Xeon MP 2.83 GHz /4MB L3/1 MB L2
• Xeon MP 3.66 GHz/1 MB L2
• Xeon MP 3.16 GHz/1 MB L2
The 64-bit Xeon processor MP uses the NetBurst architecture with Hyper-Threading technology, Hyper-
Pipelined technology, and a 12K Execution Trace Cache. It includes support for Enhanced Intel
Speed-Step Technology and Intel Execute Disable Bit technology.
As server and rack densities have increased, power and heat management are becoming
increasingly important. In response, Intel developed Enhanced Intel Speed-Step Technology, which
exposes power state registers in the processor. With the appropriate ROM or OS interface, these
registers can be used to switch the processor between different power states, changing the
processor’s operating frequency and voltage. This, in turn, lowers the power usage and heat
production of the processor. Demand-based switching is the OS implementation of power
management using the Enhanced Speed-Step technology, and is supported by some new operating
systems including Microsoft Windows Server 2003 SP1, Red Hat Enterprise Linux 4 Update 1, and
SUSE Linux Enterprise Server 9 SP1.
HP Power Regulator for ProLiant
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is an OS–independent power management feature of HP ProLiant
servers that uses Enhanced Speed-Step technology. HP Power Regulator supports both dynamic and
static modes. With HP Static Low Power Mode, the processors are configured to run continuously in a
lower power state. This is useful for customers with power-constrained data centers who require a
guaranteed maximum power usage for each server. For servers that operate in moderately or
minimally loaded environments, there will be little, if any, performance degradation. HP Dynamic
Power Savings mode lowers overall power usage of the server without affecting system performance.
When this feature is enabled,
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the System ROM will dynamically modify each processor’s frequency
and voltage based on the processor workload. The processor operates in a high power state only
when needed, thus reducing the overall system power usage.
Intel first released the Execute Disable Bit functionality with the Itanium processor family. The
technology allows the processor to classify areas of memory which cannot execute application code.
When combined with OS support, this helps to prevent certain classes of malicious buffer overflow
attacks. As of this writing, Intel Execute Disable bit is supported by Microsoft Windows Server
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Available on the ISS Technology Papers website at http://h18004.www1.hp.com/products/servers/technology/whitepapers/
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For additional information about Power Regulator for ProLiant, see http://h18000.www1.hp.com/products/servers/management/ilo/power-
regulator.html
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The ProLiant ML570 G3 and ML580 G3 system ROMs are expected to support HP Power Regulator mid-year 2005.
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