Technologies for the ProLiant ML570 G3 and ProLiant DL580 G3 Servers Technology Brief

Partitioning for electrical isolation
One of the features of a well-designed chipset is the degree to which the silicon is partitioned to allow
different signal areas to be electrically isolated. The E8500 chipset is partitioned so that the front-side
bus interconnects to a partitioned area for the “left” CPU, the “right” CPU, and each memory board
(Figure 3). The XMB is similarly partitioned so that each internal memory controller is isolated
electrically from the other to avoid power noise and crosstalk issues. Avoiding crosstalk and other
noise is increasingly important as bus speeds increase and bus signals become more susceptible to
slight differences in voltages.
Figure 3. Example of how the TNB and XMB chips are partitioned to reduce power noise and crosstalk issues.
Maximum memory configurations
Each XMB memory controller supports eight electrical loads. A single-rank DIMM is considered one
electrical load; a dual-rank DIMM is two electrical loads. Therefore, the ProLiant ML570 G3 supports
the following maximum DIMM configurations per memory board:
• Six single-rank DIMMs ( three per memory channel)
• Four dual-rank DIMMs (two per memory channel)
• Two dual-rank DIMMS and four singe-rank DIMMs
When 4-GB, dual-rank DIMMs are available, a customer can use four dual-rank DIMMs per memory
board to provide the maximum memory of 64 GB for the ProLiant ML570 G3.
The ProLiant DL580 G3 also supports a maximum of 64 GB of memory using four, dual-rank, 4-GB
DIMMs per memory board. The system can support a maximum of four DIMMs per memory board,
using either single-rank DIMMs, dual-rank DIMMs, or a combination of the two.
In either system, DIMMs must be installed in pairs on the memory board. Each DIMM pair must be
identical, with the same capacity, technology, and density. Refer to the server’s user guide for valid
memory configurations when combining single and dual-rank DIMMs.
High-performance memory
Processor performance has kept pace fairly consistently with Moore’s law of doubling performance
every two years. On the other hand, memory bandwidth doubles roughly every three years. To keep
pace, designers are challenged to make memory subsystems that are faster. The ProLiant ML570 G3
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