Serial ATA technology, 4th edition

4
Serial data transmission
Serial communication requires a serializer/deserializer (SerDes) to convert parallel data into a serial bit stream and
vice versa (Figure 2). A SerDes contains these components:
• A parallel digital interface
• First-In-First-Out (FIFO) caches
• 8 bit/10 bit (8b/10b) encoder and decoder
• A serializer
• A deserializer
Figure 2: The SerDes core integrates 8b/10b coding and decoding logic.
The 8b/10b encoder converts each 8-bit data byte to a 10-bit transmission character. That allows encoding the
clocking information into the data stream. It adds about 20% embedded overhead to the data stream, but it
eliminates clock skew problems.
SATA devices transmit signals in a single stream across the SATA interface in packets called Frame Information
Structures (FIS). SATA uses a half-duplex scheme that transmits data in one direction at a time. One wire pair
transmits the FIS, and the other wire pair transmits feedback from the receiving device. Figure 3 shows as serial
actions the transmission of the original signal on one pair and the return of status information on the other pair.
Figure 3: Half-duplex LVD signaling transmits data in one direction at a time.
Initiator Target Initiator Target
Each FIS includes a Cyclic Redundancy Check (CRC) that can detect single-bit or double-bit errors. The SATA drive
reports CRC errors to the host. The host then re-transmits all packet types except data packets. SATA does not