HP Smart Array Controllers and basic RAID performance factors

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processor writes the parity data to the drive array, the performance of the XOR operations is a key contributor to overall
write performance of parity-based arrays.
Performance improvements are most apparent in arrays with larger drive counts. The aggregate I/O of smaller drive
counts, not the bandwidth of the Smart Array processor, constrains drive array performance.
The following Smart Array controllers use an embedded RAID-on-Chip (RoC) processor running at 1000 MHz:
• HP Smart Array P222 Controller
• HP Smart Array P420 Controller
• HP Smart Array P421 Controller
• HP Smart Array P822 Controller
While it is not a direct measure of overall RAID performance, the RoC processor can support up to 200,000 4 KB random
Input/Output Operations Per Second (IOPS). Previous generations of the processors support up to 60,000 4 KB random
IOPS.
Figure 1. Smart Array controller architecture
Smart Array cache
Smart Array controllers use cache to improve the overall performance of drive arrays for both read and write operations.
You can use the HP Array Configuration Utility (ACU) to configure the percentage of the cache to use for read caching and
write caching.
Cache width
Gen8 Smart Array controllers support the following cache modules:
• 512 MiB, 40-bit wide (32 bits data + 8 bits parity) cache module
• 1 GiB, 72-bit wide (64 bits data + 8 bits parity) cache module
• 2 GiB, 72-bit wide (64 bits data + 8 bits parity) cache module
The 1 GiB and 2 GiB cache modules improve array performance because they provide significantly more cache for read
and write operations, and double the bandwidth for moving cache data to and from the storage system.
Read cache
Read cache does not improve array read performance significantly because simply reading from a drive array is already
fast. The default configuration on Smart Array controllers assigns only 10% of the available cache space for read cache.
Read cache is most effective in increasing the performance for sequential small-block read workloads and, in particular,
read workloads at low queue depth. The Smart Array controller differentiates between sequential and random