HP Smart Array Controller technology, 4th edition

3
3
Ys
es.
T
he Smart Array processing engine is responsible for processing all operations, but its capabilities are
particularly critical to complex RAID functions such as write operations. Both RAID 5 and RAID 6 use
mathematical XOR (Exclusive or) operations to calculate the parity data written to the drive array for data
recovery. The processing engine is essential for high performance operations at these RAID levels,
particularly write performance. Newer Smart Array controllers managing arrays with larger drive counts
display the most performance improvements. With smaller drive counts, logical drive array performance
tends to be constrained by the aggregate I/O of the drives and not the bandwidth of the Smart Array
processing engine.
Hardware tuning
RAID controllers with poor signal integrity between devices and without an optimized PCIe bus can have
poor performance. Our engineering teams tune connection settings on every Smart Array controller with
every connected device, and even the PCIe bus, to reduce error rates.
HP signal integrity requirements for the Smart Array controllers are far more stringent than the industry
standard. The generally accepted industry standard for the Unrecoverable Bit Error rate is typically
specified at 1 bit error in 10
12
for enterprise-class disk drives in Fibre Channel and SAS environments. We
feel that an error rate of even 10
15
is unacceptable.
Our engineers customize controller link settings to maximize signaling margins and reduce error rates. We
adjust PHY
1
transmitter and receiver connections to provide optimum settings for each Smart Array
controller with every connected device. Controllers and connected devices are tested at 1.5 Gb/s SATA,
Gb/s SATA, 3 Gb/s SAS, and 6 Gb/s SAS. HP assigns “loss factors” to each device slot to indicate
optimum PHY tuning using the results of these tests. Unique IDs identify all devices and loss factor data. The
IDs and associated loss factor data provide the information needed to precisely adjust the controller PH
for highest performance and signal margins. We stress test our controllers by intentionally degrading the
signal to the point of failure. This determines the exact signal margins. We also test Smart Array controllers
with all compatible operating systems, HP servers, server backplanes, and compatible HP devic
The Smart Array controller powers up using a default configuration that lets it function efficiently until the
retrieval of device-unique IDs and associated loss factor data. If the Smart Array controller cannot retrieve
any loss factor data, or if it detects compromised signal integrity by an event like cable failure, Smart Array
controllers can “step down” operating speed to maintain a connection. iLO management intervention
accomplishes the performance step down. The Smart Array controller resumes normal operations once it no
longer detects an issue.
The Smart Array controller PCIe connector has a unique ID and customized settings. HP engineering adjusts
the settings for the PCIe connector to account for the PCIe topology where the controller resides. These
customized settings apply to both embedded and add-in cards attached to the PCIe bus.
Cache module performance benefits
With advanced read-ahead and write-back caching capabilities, Smart Array controller cache modules
significantly improve I/O performance.
Read-ahead caching
T
he HP Smart Array controller family uses an adaptive read-ahead algorithm that anticipates data needs
and reduces wait time. It can detect sequential read activity on single or multiple I/O threads and predict
when sequential read requests will follow. The algorithm then reads ahead from the disk drives. When the
read request occurs, the controller retrieves the data from high-speed cache memory in microseconds rather
than from the disk drive in milliseconds. This adaptive read-ahead scheme provides excellent performance
for sequential small block read requests.
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The physical layer device, a circuit block that includes a PMD (physical media dependent), a PMA (physical media attachment), and
a PCS (physical coding sublayer)