Adding and Configuring Components

Each path has its own address bus, control bus, data bus, M2s, and DIMMs. The cell controller (CC) runs
each path 180 degrees out of phase, with respect to the other, to facilitate pipelining in the CC. Address
and control signals are fanned out through registers to the DIMMs. Data is transferred between the CC
and the DIMMs through the M2 ASICs.
The M2s are bit sliced and four are required to form one 72 bit CC memory data bus (MID). It takes
eight cycles for one 576 bit cache line to be sent to the M2s.
The memory side of the group of 4 M2s connects to a 576 bit DIMM bus, which interfaces with 4 logical
DIMM ranks. Each logical DIMM rank consists of 4 physical DIMMs, which are 144 bits wide and are
accessed in parallel. The M2s queue up the cache line from the CC, and transfer it to the DIMMs in one
cycle. When taking a cache line from memory, the M2 receives the cache line in one cycle and sends the
line to the CC in 72 bits groups over eight cycles.
Overview: Memory
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