ACC Utilities Reference Guide

Chapter 2 53
TTGEN - ZCOM System Table Generator
Creating the TTGEN Configuration File
source Clock Source
INT-
EXT-
ExIn-
DPLL-
Use internal baud rate generator
Use external clock
Use external clock for X.21 interface
Use DPLL output (phase locked loop)
INT must be used for ASYNC Mode
mode Operating mode of port
ASYNC-
BISYNC-
SDLC-
Asynchronous operation
Bisynchronous operation
SDLC synchronous operation
mult Clock multiplier.
X1-
X16-
X32-
X64
X1 clock mode
(BISYNC and SDLC only)
X16 clock mode (ASYNC only)
X32 clock mode (ASYNC only)
X64 clock mode (ASYNC only)
encode Data encoding mode.
NRZ-
NRZI
FM0-
FM1-
Non-return to zero (usual)
Non-return to zero inverted
FM0 encoding
FM1 encoding
NRZI, FM0, and FM1 are only valid for BISYNC and SDLC.
parity Parity of data.
NONE-
EVEN-
ODD-
No parity
Even parity
Odd parity
Parity is only valid for ASYNC and BISYNC. Leave blank
for SDLC.
stop Number of stop bits
STP1-
STP1.5-
STP2-
1stopbit
1.5stopbits
2 stop bits
Only valid for ASYNC operation