Manual

Glossary
TNSVU User’s Guide—528143-003
Glossary-13
memory manager
as they would be if the object file were running in TNS interpreted mode or on a TNS
system. Most source statement boundaries are memory-exact points. Complex
statements might contain several such points: at each function call, privileged
instruction, and embedded assignment. Contrast with register-exact point and
nonexact point.
memory manager. An HP NonStop™ operating system process that implements the paging
scheme for virtual memory. This process services requests generated by different
interrupt handlers as well as by other system processes.
memory page. A unit of virtual storage. In TNS systems, a memory page contains 2048
bytes. In TNS/R systems, the page size is determined by the memory manager and
can vary, depending on the processor type.
microcode. Any machine code or data that can run in a microprocessor. HP produces two
types of microcode for HP NonStop™ systems: volatile and nonvolatile. Volatile
microcode is loaded into the volatile random-access memory (RAM) of some types of
printed wiring assemblies (PWAs) and is not retained in a host PWA when power to the
PWA is interrupted. For nonvolatile microcode, see firmware. See also millicode.
millicode. The system’s lowest-level machine-dependent code, often coded in assembler
language. TNS/E millicode and TNS/R millicode are functionally similar to the
microcode on TNS systems. The system has several types of millicode, including
machine interrupt handlers, operating system primitives, routines implicitly called from
native-compiled code, emulators for TNS floating-point arithmetic, and emulators for
privileged-only or long-running TNS machine operations.
millicode transfer table. A table containing addresses of all millicode entry points used by
Object Code Accelerator (OCA) generated code in the TNS emulation library and the
TNS and native shared millicode library. The emulation library builds this table rather
than relying on the global offset table (GOT) because the correct execution of the code
depends on the order of the table entries being predictable and unchanging.
MIPS region of a TNS object file. The region of a TNS object file that contains MIPS
instructions and the tables necessary to execute the instructions in accelerator mode
on a TNS/R system. Accelerator creates this region and writes it into the TNS object
file. Contrast with Intel® Itanium® instruction region.
MIPS RISC instructions. Register-oriented 32-bit machine instructions in the MIPS-1 RISC
instruction set that are native to and directly executed on TNS/R systems. MIPS RISC
instructions do not execute on TNS systems and TNS/E systems. Contrast with TNS
instructions and Intel® Itanium® instructions.
Accelerator-generated MIPS RISC instructions are produced by accelerating TNS
object code. Native-compiled MIPS RISC instructions are produced by compiling
source code with a TNS/R native compiler.