Datasheet

6 Datasheet, Volume 1
5.6.4 On-Demand Mode...................................................................................79
5.6.4.1 MSR Based On-Demand Mode .....................................................79
5.6.4.2 I/O Emulation-Based On-Demand Mode .......................................79
5.6.5 Memory Thermal Management..................................................................80
5.6.6 Platform Environment Control Interface (PECI) ...........................................80
6 Signal Description....................................................................................................81
6.1 System Memory Interface ...................................................................................82
6.2 Memory Reference and Compensation ..................................................................84
6.3 Reset and Miscellaneous Signals ..........................................................................84
6.4 PCI Express*-based Interface Signals ...................................................................85
6.5 Embedded DisplayPort (eDP)...............................................................................85
6.6 Intel
®
Flexible Display Interface Signals ...............................................................85
6.7 Direct Media Interface (DMI) ...............................................................................86
6.8 Phase Lock Loop (PLL) Signals.............................................................................86
6.9 Test Access Points (TAP) Signals..........................................................................86
6.10 Error and Thermal Protection...............................................................................87
6.11 Power Sequencing .............................................................................................88
6.12 Processor Power Signals .....................................................................................89
6.13 Sense Signals....................................................................................................89
6.14 Ground and NCTF ..............................................................................................90
6.15 Processor Internal Pull-Up / Pull-Down..................................................................90
7 Electrical Specifications ...........................................................................................91
7.1 Power and Ground Pins.......................................................................................91
7.2 Decoupling Guidelines ........................................................................................91
7.2.1 Voltage Rail Decoupling ...........................................................................91
7.2.2 PLL Power Supply ...................................................................................91
7.3 Voltage Identification (VID).................................................................................92
7.4 System Agent (SA) Vcc VID ................................................................................95
7.5 Reserved or Unused Signals ................................................................................95
7.6 Signal Groups ...................................................................................................96
7.7 Test Access Port (TAP) Connection .......................................................................98
7.8 Component Storage Condition Specifications (Prior to Board Attach).........................98
7.9 DC Specifications...............................................................................................99
7.9.1 Voltage and Current Specifications ............................................................99
7.10 Platform Environmental Control Interface (PECI) DC Specifications ......................... 106
7.10.1 PECI Bus Architecture............................................................................ 106
7.10.2 PECI DC Characteristics ......................................................................... 107
7.10.3 Input Device Hysteresis ......................................................................... 107
8 Processor Pin, Signal, and Package Information ....................................................109
8.1 Processor Pin Assignments ................................................................................ 109
8.2 Package Mechanical Information ........................................................................156
9 DDR Data Swizzling................................................................................................ 165