Trusted Execution Technology and Tboot Implementation

TBOOT: entry[2] sig = APIC @ 0x773fa000

TBOOT: acpi_table_ioapic @ 773fa06c, .address = fec00000

TBOOT: RSDP (v002 HPQOEM) @ 0x000f2b20

TBOOT: Seek in XSDT...

TBOOT: entry[0] sig = FACP @ 0x773fc000

TBOOT: entry[1] sig = HPET @ 0x773fb000

TBOOT: entry[2] sig = APIC @ 0x773fa000

TBOOT: entry[3] sig = MCFG @ 0x773f9000

TBOOT: acpi_table_mcfg @ 773f9000, .base_address = e0000000

TBOOT: mtrr_def_type: e = 1, fe = 1, type = 0

TBOOT: mtrrs:

TBOOT: base mask type v

TBOOT: 0ffc00 fffc00 05 1

TBOOT: 000000 f80000 06 1

TBOOT: 078000 ff8000 00 1

TBOOT: 000000 000000 00 0

TBOOT: min_lo_ram: 0x0, max_lo_ram: 0x77400000

TBOOT: min_hi_ram: 0x0, max_hi_ram: 0x0

TBOOT: MSR for SMM monitor control on ILP 0 is 0x0.

TBOOT: verifying ILP is opt-out or has the same MSEG header with TXT.MSEG.BASE

opt-out

TBOOT: : succeeded.

TBOOT: enabling SMIs on BSP

TBOOT: mle_join.entry_point = 8031f0

TBOOT: mle_join.seg_sel = 8

TBOOT: mle_join.gdt_base = 804000

TBOOT: mle_join.gdt_limit = 3f

TBOOT: joining RLPs to MLE with MONITOR wakeup

TBOOT: rlp_wakeup_addr = 0x77701d10

TBOOT: cpu 4 waking up from TXT sleep

TBOOT: waiting for all APs (3) to enter wait-for-sipi...

TBOOT: MSR for SMM monitor control on RLP(4) is 0x0

TBOOT: verifying ILP's MSR_IA32_SMM_MONITOR_CTL with RLP(4)'s

: succeeded.

TBOOT: enabling SMIs on cpu 4

TBOOT: .VMXON done for cpu 4

TBOOT:

TBOOT: cpu 5 waking up from TXT sleep

TBOOT: launching mini-guest for cpu 4

TBOOT: MSR for SMM monitor control on RLP(5) is 0x0

TBOOT: verifying ILP's MSR_IA32_SMM_MONITOR_CTL with RLP(5)'s

: succeeded.