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Front -Panel Operation Reference HP 16510B Logic Analyzer Module for the HP 16500A Logic Analysis System ÿCopyright Hewlett-Packard Company 1989 Manual Set Part Number 16510-90913 Printed in the U.S.A.
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Introduction About this manual... Welcome to the new generation of HP logic analyzers! The HP 16500A Logic Analysis System has been designed to be easier to use than any Hewlett-Packard logic analyzer before. In addition, because of its configurable architecture, it can easily be tailored to you specific logic design and debug needs. The user interface of the HP 16500A was designed for the most intuitive operation possible.
Contents Chapter 1: Chapter 2: HP 16510B Front-Panel Reference General Information Logic Analyzer Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accessories Supplied. . . . . . . .
Chapter 3: Using the Front-Panel Interface Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Using the Mouse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 How to Select Menus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 How to Switch Between Analyzers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Returning to the System Configuration Menu. . . . . .
Chapter 5: HP 16510B Front-Panel Reference Menus Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 System Level Menu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 State/Timing Configuration Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Name. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Type . . . . . . . . . . . . . . . . . . . .
Reading the Sequence Level Display. . . . . . . . . . . . . . . . . . . . . . . . . . . Acquisition Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Run/Trace Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Armed By . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Count . . . . . . . . . . .
Chapter 7: Using The Timing Analyzer Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 Problem Solving with the Timing Analyzer . . . . . . . . . . . . . . . . . . . . . . 7-1 What Am I Going to Measure? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 How Do I Configure the Logic Analyzer? . . . . . . . . . . . . . . . . . . . . . . . 7-2 Connecting the Probes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 9: Chapter 10: Chapter 11: Contents-6 State Compare Menu Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accessing the Compare Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Compare and Difference Listing Displays . . . . . . . . . . . . . . . . . . . . The Compare Listing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Difference Listing . . . . . . . . . . . . . . . . . . . . .
Chapter 12: Using the Timing/State Analyzer Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 Problem Solving with the Timing/State Analyzer . . . . . . . . . . . . . . . . 12-2 What Am I Going to Measure? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 How Do I Configure the Logic Analyzer? . . . . . . . . . . . . . . . . . . . . . . 12-3 Configuring the State Analyzer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80286 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8 80386 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9 6800 or 6802 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10 6809 or 6809E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11 68008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appencix C: Specifications and Characteristics Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Probes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Mode . . . . . . . . . . . . . .
1 General Information Logic Analyzer Description The HP 16510B logic analyzer is part of a new generation of general purpose logic analyzers with improved features to accommodate next generation design tasks. The 80-channel HP 16510B logic analyzer is capable of 100 MHz timing and 35 MHz state analysis on all channels. This analyzer is designed as a stand alone instrument for use by digital and microprocessor hardware designers.
The knob on the front panel is used to move the cursor on certain menus, increment or decrement numeric fields, and to roll the display. The touchscreen fields can be selected by touch or with the optional mouse. To activate a touchscreen field by touch, touch or press the field (the dark blue box) on the display with your finger until the field changes color. Then remove your finger from the screen to activate your selection.
Key Features Two 3.5-inch disk drives are integral to the instrument for storing logic analyzer configurations and acquired data. The disk drive also provides a way of loading inverse assembly configuration files into the logic analyzer for configuring ease.
Table 1-3. Accessories Accessory HP Part No.
2 Probing Introduction This chapter contains a description of the probing system of the HP 16510B logic analyzer. It also contains the information you need to connect the probe system components to each other, to the logic analyzer, and to the system under test.
The HP 10269C General Purpose Probe Interface Instead of connecting the probe tips directly to the signal lines, you may use the HP 10269C General Purpose Probe Interface (optional). This allows you to connect the probe cables (without the probes) to connectors on the interface. When the appropriate preprocessor is installed in the interface, you will have a direct connection between the logic analyzer and the microprocessor under test.
General Purpose Probing General purpose probing involves connecting the probes directly to your target system without using the interface. General purpose probing does not limit you to specific hook-up schemes as the probe interface does. The Termination Adapter The optional termination adapter (HP Part No. 01650-63201) allows you to connect the probe cables directly to test ports on your target system without the probes.
The HP 16510B Probing System The standard HP 16510B probing system consists of probes, pods, probe cable and grabbers. This system is passive (has no active circuits at the outer end of the cable). This means that the pods and probes are smaller and lighter, making them easier to use. The passive probe system is similar to the probe system used with high frequency oscilloscopes. It consists of a series R-C network (90.9 kΩ in parallel with 8 pF) at the probe tip, and a shielded resistive transmission line.
Probe Cable Caution The probe pod cable contains 17 signal lines, 34 chassis ground lines and two power lines that is woven together. It is 4.5 feet long. The probe grounds are chassis (earth) grounds, not "floating" grounds. Each cable is capable of carrying 0.67 amps for preprocessor power. Current in excess of 0.67 amps per cable will cause the preprocessor supply voltage to drop below a safe level. DO NOT exceed this 0.67 amps per cable or the preprocessor may malfunction.
You can connect the probe directly to the test pins on your target system. To do so, the pins must be 0.63 mm (0.025 in.) square pins or round pins with a diameter of between 0.66 mm (0.026 in.) and 0.84 mm (0.33 in.). Each probe has an input impedance of 100 kΩ in parallel with approximately 8 pF. Figure 2-5. Probe Input Circuit Probes can be grounded in one of two ways: a common pod ground and a probe ground for each probe.
Probe Grounds You can ground the probes in one of two ways. You can ground the probes with the pod ground only; however, the ground path won’t be the same length as the signal path through the probe. If your probe ground path must be the same as your signal path, use the short ground lead (probe ground). The probe ground lead connects to the molded probe body via a pin and socket. You can then use a grabber or grounded pins on your target system the same way as the pod ground. Figure 2-6.
Signal Line Loading Any signal line you intend to probe must be able to supply a minimum of 600 mV to the probe tip, which has an input impedance of 100 kΩ shunted by 8 pF. If the signal line is incapable of this, you will not only have an incorrect measurement but the system under test may also malfunction. Maximum Probe Input Voltage The maximum input voltage of each probe is ± 40 volts peak. Pod Thresholds There are two preset thresholds and a user-definable pod threshold for each pod.
Connecting the Probe Cables to the Logic Analyzer The probe cables are installed in the Logic Analyzer module at the factory. The cable for pod 1 is the far left cable (rear view). Cables 2 through 5 follow cable 1 consecutively from left to right. If there is a need to install or replace the cables refer the HP 16510B Service Manual.
Disconnecting the Probes from the Pods The probes are shipped already installed in the pods. However, you can disconnect any un-used probes from any of the pods. This keeps the un-used probes from getting in your way. To disconnect a probe, insert the tip of a ball-point pen in the latch opening and push while gently pulling the probe out of the pod connector as shown below. Figure 2-8.
Connecting the Grabbers to the Probes You connect the grabbers to the probes by slipping the connector at the end of the probe onto the recessed pin in the side of the grabber. If you need to use grabbers for either the pod or the probe grounds, connect them to the ground leads the same way you connect them to the probes. Figure 2-9. Connecting Grabbers to Probes Connecting the Grabbers to the Test Points The grabbers have a hook that fits around IC pins and component leads.
Labeling Pods, Probes, and Cables So you can find the pods and probes you want to connect to your target system, you need to be able to quickly identify them. Included with your logic analyzer are self-adhesive labels for each pod, cable and probe. They come in sets. Each set has labels for the end of the cable-- a label for the pod connector body, a label for the clock probe and 16 labels for each of the channels. One end of each cable is already connected to the HP 16510B logic analyzer module.
3 Using the Front-Panel Interface Introduction This chapter gives you an overview of how to use the front-panel interface. The front-panel user interface is merely accessing the many menus and using the convenient touch-screen to move around the menu tree. The front panel itself consists of a disk drive, the knob, power switch, display, and receptacle for connecting the optional mouse. The user interface allows you to configure the logic analyzer and each analyzer (machine) within the logic analyzer.
How to Select Menus Note Before you try to select one of the main menus, make sure the field in the upper left-hand corner is set to State/Timing E. If the HP 16500A is in System or Intermodule, touch that field and select State/Timing E when the pop-up appears. The field containing State/Timing (x) may have a different letter following State/Timing. Don’t be alarmed. This letter merely tells you what card slot the State/Timing module is in.
How to Switch Between Analyzers You can switch between analyzers in any main menu by touching the field (second from the left in the upper left-hand corner). When the pop-up appears you can select the desired menu in the desired analyzer when both analyzers are on.
How to Close Pop-up Menus Some pop-up menus automatically close when you touch a desired field. After closing, the logic analyzer places your choice in the main menu field from which you opened the pop-up. Other pop-up menus don’t automatically close when you make your selection (i.e. alphanumeric keyboard). These menus have a Done option. To close the pop-up all you have to do is touch the Done field. Toggle Fields Some fields will toggle between two options (i.e., off and on).
Figure 3 - 1. State Clock Pop-up Menu An example of one of these is the clock field in the State Format Specification menu. When you select the clock field in this menu it will pop-up and show you all five clocks (J, K, L, M, and N). When you select one of the five clocks, another pop-up appears showing you the available choices of clock specifications. Figure 3 - 2.
When you touch one of these the pop-up will close, however, the original clock pop-up still remains open. When you are finished specifying the choices for the clocks, you close the original pop-up menu by touching Done. How to Enter Numeric Data There are a number of pop-up menus in which you enter numeric data. The two major types are: • Numeric entry with fixed units • Numeric entry with variable units (i.e. µs, ms, etc.
If you select the User option, a numeric keypad pop-up appears where you enter the desired threshold voltage. After selecting the value, you select the units (i.e., mV or V). Touch Done when you have finished specifying the pod threshold. Figure 3 - 4. Numeric Entry Keypad If you want a negative voltage for the threshold, press the − (minus sign) in the pop-up. Entering the − (minus sign) can be done either before or after the voltage level has been entered.
For example, you can name each analyzer with a name that is representative of your measurement. The default names for the analyzers within the logic analyzer are MACHINE 1 and MACHINE 2. To rename an analyzer, touch the field to the right of Name:_______ in the State/Timing E Configuration menu. When the alphanumeric pop-up menu appears, enter the name you desire. The line above the alphanumeric keyboard contains the current name. When you first enter the pop-up, the cursor in the name field is at the left.
How to Roll Data The roll feature is available in all menus that contain off-screen data. This allows you to roll data for viewing. Data can be off-screen both above and below or left and right of what you see on screen. One example of a menu having off-screen data above and below the screen is the State Listing. The state listing is normally a list 1024 lines long, however, the display is only capable of showing you 16 lines at a time.
An example of off-screen data left and right can also be shown in figures 3-7 and 3-8. Figure 3-7 illustrates a timing Trace menu with labels off screen. In this case only six of the eight labels can be displayed at a time. Whenever there is data off screen to the left or right, an additional field exists in the menu as shown in figure 3-7. This is called a field because it is enclosed in a box and will turn light blue when touched. Figure 3 - 7.
Assignment/ Specification Menus There are a number of pop-up menus in which you can assign or specify what you want the logic analyzer to do. The basic menus of this type consist of: • • • Assigning Pod Bits to Labels Assigning bits to pods Specifying patterns Specifying edges The bit assignment fields in both state and timing analyzers work identically. The convention for bit assignment is: * (asterisk) indicates assigned bits . (period) indicates un-assigned bits.
To assign bits to either Analyzer 1 or Analyzer 2 there must be at least one pod assigned to the desired analyzer. If there are no pods assigned to the analyzer you wish to use follow steps 1 and 2. If there is a pod assigned to the desired analyzer go to step 3 where you access the Format menu. 1. Enter the State/Timing E Configuration menu. 2. Touch a Pod field. When the pop-up appears, assign the pod to the analyzer of your choice. 3. Touch the field second from left in the top left corner.
Specifying Patterns The Pattern field appears in several menus. Patterns can be specified in one of the available number bases. Patterns can be viewed in ASCII, but cannot be entered in ASCII. The convention for "don’t care" in these menus is an X except in the decimal base. If the base is set to decimal after a "don’t care" is specified, a $ will be displayed. To select a pattern, enter the Trace menu and follow these steps: 1. Touch the field to the right of Pattern.
Specifying Edges You can select a positve-going (↑), negative-going (↓), and either edge ( ) for your trigger. To specify edges, enter the Trace menu and follow these steps: 1. Touch the field in the bottom left corner of the display. This field is labeled Edge. You will see the following pop-up. Figure 3 - 11. Specifying Edges Pop-up Menu 2.
4 Using the Menus Introduction This chapter contains menu maps of the HP 16510B logic analyzer. Since the front-panel user interface consists mainly of menus that you access to configure the logic analyzer, the menu maps provide quick reference to the menus, menu options, and ultimately the functions of the logic analyzer. Menu Maps The following pages show the menu maps of all functions of the logic analyzer. The State/Timing Configuration menu is the logic analyzer’s system level menu.
State/Timing Configuration Menu Map Figure 4-1.
Timing Format Menu Map Figure 4-2.
Timing Trace Menu Map Figure 4-3.
Timing Waveform Menu Map Figure 4-4.
Figure 4-4.
State Format Menu Map Figure 4-5.
State Trace Menu Map Figure 4-6.
Figure 4-6.
State Listing Menu Map Figure 7-4.
State Compare Menu Map Figure 4-8.
State Waveform Menu Map Figure 4-9.
Figure 4-9.
State Chart Menu Map Figure 4-10.
Figure 4-10.
Mixed Display Menu Map Figure 4-11.
5 Menus Introduction This chapter describes the menus and pop-up menus that you will use on your logic analyzer. The purpose and functions of each menu are explained in detail, and we have included many illustrations and examples to make the explanations clearer. The main menus of the logic analyzer are grouped into two categories: System Level Menus and Subsystem Level Menus.
State/Timing Configuration Menu The State/Timing Configuration menu for the HP 16510B Logic Analyzer is shown below. The fields in the menu that are numbered in the figure are described in this section. 1 6 2 5 3 4 Figure 5-1. State/Timing Configuration Menu 1 Name You name an analyzer by selecting the Name field under it. An alphanumeric pop-up menu will appear. The keypad is similar to a computer keyboard. Figure 5-2.
At the top of the keypad pop-up, is a box where the current name appears when the pop-up opens, and where the new name will appear when you touch keys on the keypad. In the name box is a cursor which indicates in what space your next selection will be placed. You can name the analyzer in one of two ways. The first way is to position the cursor over the character to be replaced in the pop-up using the KNOB, then touching the new character. The new character appears in the name box.
3 Autoscale The purpose of Autoscale is to provide a starting point for setting up a measurement. The Autoscale field only appears on a timing analyzer. When you touch Autoscale, you will see a pop-up with two options: Cancel and Execute. If you select Cancel, the autoscale is cancelled and control is returned to the State/Timing Configuration menu. Figure 5-4. Autoscale Pop-up Menu If you choose Execute, autoscale configures the timing Format and Trace Specification menus and the timing Waveforms menu.
4 Pods Each pod can be assigned to one of the analyzers. When the HP 16510B Logic Analyzer is powered up, Pod 1 is assigned to Analyzer 1 and Pod 5 is assigned to Analyzer 2. To assign a pod, touch the pod field. With the pop-up that appears, you can assign the pod to Analyzer 1, Analyzer 2, or Unassign it. Making a selection closes the pop-up and moves the pod field to the analyzer to which the pod is assigned. Figure 5-5.
Print Screen. In the Print Screen mode, the printer uses its graphics capabilities so that the printout will look just like the logic analyzer screen. Print All. The Print All option prints not only what is displayed on screen but what is below, and, in the Format Specification, what is to the right of the screen at the time you initiate the printout. Note Make sure the first line you wish to print is in the light blue box at the center of the listing area when you touch Print All.
If you wish to stop a printout before it is completed, touch Cancel. This stops the print and the message "Print Cancelled" appears at the top of the display. 6 Run Subsystem Level Menus The Run field allows you to start data acquisition. The pop-up that appears when you touch this field contains the trace mode options Single, Repetitive, and Cancel. This field is explained in detail in "Run/Trace Mode" in both the Timing and State Trace specification menus sections of this chapter.
Format Specification Menus At power up the Timing and State Format Specification menus look basically the same, with a few exceptions in the state analyzer. The Timing Format Specification menu looks like that shown below: 5 1 4 2 3 Figure 5-6. Timing Format Specification Menu The State Format Specification menu for the HP 16510B looks like the following: 6 8 7 Activity Indicators Figure 5-7.
These menus show only one pod assigned to each analyzer at power up. Any number of pods can be assigned to one analyzer, from none to all five. In the Format menus, only three pods appear at a time in the display. If there are any pods off screen, an additional field will be present. This field is labeled Pods ↔. To view off-screen pods, touch the Pods ↔ field and rotate the KNOB. The pods are always positioned so that the lowest numbered pod is on the right and the highest numbered pod is on the left.
To access one of the Label fields, touch the desired field. You will see a pop-up menu like that shown below. Figure 5-8. Label Pop-up Menu Turn Label On. Selecting this option turns the label on and gives it a default letter name. If you turned all the labels on they would be named POD 1 through T from top to bottom in the timing analyzer and A through T in the state analyzer. When a label is turned on, bit assignment fields for the label appear to the right of the label under the pods. Modify Label.
2 Polarity (Pol) Each label has a polarity assigned to it. The default for all the labels is positive ( + ) polarity. You can change the polarity of a label by touching the polarity field. This toggles the polarity between positive ( + ) and negative ( −). In the state analyzer, negative polarity inverts all the data. In the timing analyzer, negative polarity inverts all the data, but doesn’t change the actual waveforms in the Timing Waveforms Menu.
Assigning one channel per label may be handy in some applications. This is illustrated in chapter 7 of the HP 16510B Getting Started Guide. Also, you can assign a channel to more than one label, but this usually isn’t desired. Labels may have from 1 to 32 channels assigned to them. If you try to assign more than 32 channels to a label, the logic analyzer will beep, indicating an error, and a message will appear at the top of the screen telling you that 32 channels per label is maximum.
If you touch the pod threshold fields you will see the following pop-up menu. Figure 5-11. Pod Threshold Pop-up Menu TTL sets the threshold at +1.6 volts, and ECL sets the threshold at −1.3 volts. The User option lets you set the threshold to a specific voltage between −9.9 V and +9.9 V. If you select this option you will see a numeric entry keypad pop-up menu as shown. Figure 5-12.
You enter a threshold in the pop-up with the keypad by touching the desired value, units and polarity. When the correct threshold voltage is displayed, touch DONE. The pop-up will close and the new threshold will be placed in the pod threshold field. In the state analyzer, the same threshold level applies to a pod’s clock as to its 16 data bits. 5 Specify Symbols The logic analyzer supplies Timing and State Symbol Tables in which you can define a mnemonic for a specific bit pattern of a label.
There are four fields in the Symbol Table menu. They are: • • • • Label Base Symbol Width Symbol name Label. The Label field identifies the label for which you are specifying the symbols. If you select this field you will get a pop-up that lists all the labels that are turned on in that analyzer. Figure 5-14. Label Pop-up Menu Each label has a separate symbol table. This allows you to give the same name to symbols defined under different labels.
To change the base, touch the current base. You will see the following pop-up menu. Figure 5-15. Base Pop-up If more than 20 channels are assigned to a label, the Binary option is not offered in the pop-up. The reason for this is that when a symbol is specified as a range, there is only enough room for 20 bits to be displayed on the screen. When you decide which base you want to work in, choose that option from the number Base pop-up menu.
Symbol Width. The Symbol Width field lets you specify how many characters of the symbol name will be displayed when the symbol is referenced in the Timing and State Trace Specification menus, the Timing Waveforms menu, or the State Listing menu. Selecting this field gives you the following pop-up. Figure 5-16. Symbol Pop-up Menu You can have the logic analyzer display from 1 to all 16 of the characters in the symbol name.
Figure 5-17. Symbol Defined as a Pattern The first of these fields defines the symbol as either a pattern or a range. If you touch this field, it will toggle between pattern and range. When the symbol is defined as a pattern, one field (Pattern/start) appears to specify what the pattern is. Touching this field displays a pop-up with which you can specify the pattern. Use the keypad and the X (Don’t Care) key to enter the pattern. Figure 5-18.
If the symbol is defined as a range, two fields appear in which you specify the upper and lower boundaries of the range. The fields are Pattern/Start and Stop. Figure 5-19. Symbol Defined as a Range Touching either of these fields gives you a pop-up with which you can specify the boundary of the range. Figure 5-20.
You can specify ranges that overlap or are nested within each other. They must be specific. Don’t cares are not allowed. The logic analyzer gives patterns priority over ranges when displaying measurements. This will be covered in more detail in the sections "Timing Waveforms Menus" and "State Listing Menus" later in this chapter. To add more symbols to your symbol table, touch the field of the last symbol defined. A pop-up menu appears as shown. Figure 5-21.
6 Clock The Clock field is present in the Format Specification menu only in the state analyzer. This field displays the clocks that are to be used to clock the logic analyzer. The display will be referred to as the "clocking arrangement." The HP 16510B Logic Analyzer has five clock channels, each of which is on a pod. The clocks are connected through the pods simply for convenience. The clock channels are labeled J, K, L, M, and N and are on pods 1 through 5, respectively.
Figure 5-23. Single Clock Pop-up Menu With this menu you set the condition needed by each clock. You can specify that the logic analyzer looks for the negative edge of the clock, the positive edge, either edge, a high level, or a low level, or you can turn the clock off. The clocks are combined by ORing and ANDing them. Clock edges are ORed to clock edges, clock levels are ORed to clock levels, and clock edges are ANDed to clock levels.
With this arrangement, the logic analyzer will clock the data when there is a negative edge of the J clock OR a positive edge of the K clock, AND when there is a high level on the M clock OR a low level on the N clock. You must always specify at least one clock edge. If you try to use only clock levels, the logic analyzer will display a message telling you that at least one edge is required. 7 Pod Clock Your logic analyzer has the capability of clocking data in three different ways.
Normal. This option specifies that clocking will be done in single phase. That is, the clocking arrangement located in the Clock field above the pods in the State Format Specification menu will be used to clock all data (pods) assigned to this machine. For example, suppose that the Clock field looks like the following: Figure 5-26.
Figure 5-27. Master Clock and Slave Clock Demultiplexing is done on the data lines of the specified pod to read only the lower eight bits. This is two phase clocking, with the Master Clock following the Slave Clock. The analyzer first looks for the clocking arrangement that you specify in the Slave Clock. When it sees that, the analyzer clocks the data present on bits 0-7 of the pod, then waits for the clocking arrangement that you specify in the Master Clock.
Figure 5-28. Bit Assignments for Master and Slave The Master and Slave Clocks can have the same clocking arrangements. The clocking is still done the same way, with the lower eight bits being clocked first on the Slave Clock, then on the Master Clock. Mixed Clocks. The Mixed Clocks option allows you to clock the lower eight bits of a pod separately from the upper eight bits. The state analyzer uses Master and Slave Clocks to do this.
8 Clock Period This field provides greater measurement accuracy when your state input clock period is greater than 60 ns. When you select > 60 ns, the state analyzer provides greater immunity against noise or ringing in the state input clock signal; therefore, the logic analyzer provides greater accuracy when triggering another state or timing analyzer or the BNC trigger out. If your State input clock period is less than 60 ns, you should select < 60 ns.
Timing Trace Specification Menu Fields The fields in the Timing Trace Specification menu are: 1) Run/Trace Mode 2) Armed by 3) Acquisition mode 4) Label 5) Base 6) Find Pattern 7) Pattern Duration (present for ______) 8) Then find Edge These are described in the following sections. 1 Run/Trace Mode You specify the mode in which the timing analyzer will trace data when you touch Run. You have two choices for trace mode: Single and Repetitive.
Single Trace mode acquires data once per trace. Repetitive Trace mode repeats single acquisitions until Stop is touched, or until the time interval between two specified patterns is less than or greater than a specified value, or within or not within a specified range. The Stop Measurement feature is explained in detail in "Markers Pattern" in both the "Timing Waveforms" and "State Listing" sections of Chapter 6 of this manual.
3 Acquisition Mode The Acquisition mode field allows you to specify the mode in which you want the timing analyzer to acquire data. You are given two choices for the mode of acquisition: Transitional and Glitch. When you touch this field, the field toggles from one mode to the other. Transitional Acquisition Mode.
Traditional timing samples and stores data at regular intervals. Transitional timing samples data at regular intervals but stores a sample only when there has been a transition on one or more of the channels. This makes it possible for Transitional timing to store more information in the same amount of memory. Glitch Acquisition Mode. A glitch is defined as any transition that crosses the logic threshold more than once between samples.
With these glitch detection fields you specify on which channel or channels you want the analyzer to look for a glitch. These fields are discussed in more detail in the "Then Find Edge" section later in this chapter. Glitch Acquisition mode causes the storage memory to be cut in half, from 1k to 512. Half of the memory (512) is allocated for storing the data sample, and the other half for storing the second transition of a glitch in a sample. Every sample is stored.
5 Base The Base fields allow you to specify the number base in which you want to define a pattern for a label. The Base fields also let you use a symbol that was specified in the Timing Symbol Table for the pattern. Each label has its own base defined separately from the other labels. If you select one of the Base fields, you will see the following pop-up menu. Decide which base you want to define your pattern in and select that option. One of the options in the Base pop-up is ASCII.
The Symbol option in the Base pop-up allows you to use a symbol that has been specified in the Timing Symbol Tables as a pattern, or specify absolute and enter another pattern. You specify the symbol you want to use in the Find Pattern field. 6 Find Pattern With the Find Pattern fields, you configure your timing analyzer to look for a certain pattern in the data. Each label has its own pattern field that you use to specify a pattern for that label.
As mentioned in the previous section on the Base field, if you specify ASCII as the base for the label, you won’t be able to enter a pattern. You must specify one of the other number bases to enter the pattern, then you can switch the base to ASCII and see what ASCII characters the pattern represents. If you choose Symbols in the Base field, you can use one of the symbols specified in the Timing Symbol Tables as the pattern. The Find Pattern field looks similar to that below: Figure 5-38.
If you select this field you get a pop-up similar to that shown: Figure 5-39. Symbol Selection Pop-up for Find The pop-up lists all the symbols defined for that label. It also contains an option absolute. Placing the blue bar on this option causes another field within the pop-up to appear. This field is labeled offset______. The offset field lets you specify a pattern not given by one of your symbols.
7 Pattern Duration (present for______) There are two fields with which you specify the Pattern Duration. They are located next to present for ______ in the Timing Trace Specification menu. You use these fields to tell the timing analyzer to trigger before or after the specified pattern has occurred for a given length of time. The first field can be set to > (greater than) or < (less than). When you touch this field, it toggles between > and <. The second field specifies the duration of the pattern.
As an example, suppose you configure the present for field as shown: Figure 5-41. Example of Pattern > 50 ns This configuration tells the timing analyzer to look for a certain pattern specified by you that has a duration of greater than 50 ns. Once the timing analyzer has found the pattern, it can look for the trigger. Choosing < (less than) forces glitch and edge triggering off, and the timing analyzer triggers immediately at the end of the pattern that meets the duration requirements.
8 Then Find Edge With the Then find Edge fields you can specify the edges (transitions) of your data on which your timing analyzer triggers. You can specify a positive edge, a negative edge, or either edge. Each label has its own edge trigger specification field so that you can specify an edge on any channel. When you specify an edge on more than one channel, the timing analyzer logically ORs them together to look for the trigger point. That is, it triggers when it sees any one of the edges you specified.
If you want to delete an edge specification, place the cursor on the arrow for that channel and touch the . (period). To clear an entire label, touch CLEAR in the pop-up. When you have finished specifying edges, touch Done to close the pop-up. An example of a positive, negative, and either edge specification is shown below. Figure 5-44. Combination of Edges Specified Note Menus 5-40 When you close the pop-up after specifying edges, you will see ($$..) in the Then find Edge field.
Glitch Triggering. When you set the Acquisition mode on Glitch, a glitch detection field for each label is added to the screen. These fields allow you to specify glitch triggering on your timing analyzer. Selecting one of these fields brings up the following pop-up menu. Figure 5-45. Specify Glitch Pop-up for Then Find Your pop-up may look different depending on the number of channels you have assigned to the label. Each period indicates that the channel has not been specified for glitch triggering.
Figure 5-46. Glitches Specified If you want to delete a glitch specification, place the cursor on the asterisk and touch the period. The asterisk is replaced with a period. Note When you close the pop-up after specifying glitches, you will see dollar signs ($$..) in the Glitch field. These indicate that glitches have been specified; however, the logic analyzer can’t display them correctly unless you have selected Binary for the base.
State Trace Specification Menu The State Trace Specification menu allows you to specify a sequence of states required for trigger. The default setting for the menu looks like that shown below. Figure 5-47. State Trace Specification Menu The menu is divided into three sections: the Sequence Levels in the large center box, the acquisition fields at the right of the screen, and the qualifier and pattern fields at the bottom of the screen.
Qualifier: a term you specify that can be anystate, nostate, a single pattern recognizer, a range recognizer, the complement of a pattern or range recognizer, or a logical combination of pattern and range recognizers. When you select a field to specify a qualifier, you will see the following qualifier pop-up menu. Figure 5-48. Qualifier Pop-up Menu If you select the Combination option in the pop-up, you will see a pop-up similar to that shown below. Figure 5-49.
Note If two multi-pod state analyzers are on, the qualifier pop-up menu will show that only four pattern recognizers are available to each analyzer. Pattern recognizers a-d and the range recognizer go with the first analyzer created, and pattern recognizers e-h go with the second analyzer. In the Full Qualifier Specification pop-up, there will be only one OR gate and one set of pattern recognizers.
Figure 5-51. Patterns Assigned for Logical As shown in the previous figures, the range is included with the first group of patterns (a-d). If you select the range field, you will see the following pop-up menu. Figure 5-52. Range Specification Pop-up Menu Off disconnects the range from the qualifier specification.
When you have specified your combination qualifier, select Done. The Full Qualifier Specification pop-up closes and the Boolean expression for your qualifier appears in the field for which you specified it. Figure 5-53. Boolean Expression for Qualifier Sequence Levels There are eight trigger sequence levels available in the state analyzer. You can add and delete levels so that you have from two to eight levels at a time. Only three levels appear in the Sequence Levels display at one time.
1 Insert Level To insert a level, touch the field labeled Insert Level. You will see the following pop-up menu. Figure 5-55. Insert Level Pop-up Menu Cancel returns you to the sequence level pop-up without inserting a level. Before inserts a level before the present level. After inserts a level after the present level. If there are eight levels, the Insert Level field doesn’t appear in the sequence level pop-ups.
3 Storage Qualifier Each sequence level has a storage qualifier. The storage qualifier specifies the states that are to be stored and displayed in the State Listing. Selecting this field gives you the qualifier pop-up menu shown in figure 5-48, with which you specify the qualifier. As an example, suppose you specify the storage qualifier in a sequence level as shown below. Figure 5-56.
5 Occurrence Counter The primary branching qualifier has an occurrence counter. With the occurrence counter field you specify the number of times the branching qualifier is to occur before moving to the next level. To change the value of the occurrence counter, touch the field. You will see a pop-up similar to that shown below. Figure 5-57. Occurrence Counter Pop-up You can enter the value by touching the appropriate numeric keys. The qualifier can be specified to occur from one to 65535 times.
Selecting the field gives you a pop-up with two options. One option is what the field said previously. The other option is Enable on. If you select this option, the Sequence Level pop-up changes to look similar to that shown below. Figure 5-59. Sequence Level Pop-up with Storage Note Enable on can only be the next to the last term, and when on, the last term is combined with the Enable term. For example, when you close the pop-up in figure 5-59, levels 2 and 3 will be combined.
As an example, suppose you configure the sequence level of figure 5-59 to look like that shown below. Figure 5-60. Storage Macro Sequence Level The logic analyzer will store the state given by pattern recognizer d until it comes across the state given by a. When it sees state a, the logic analyzer starts to store the state given by pattern recognizer e. It stores that state until it sees the state given by f, at which time it disables and starts the process all over again.
Reading the Sequence Level Display Reading the display is fairly straightforward. For example, suppose your display looks like that shown below. Figure 5-61. Sequence Level Display Example In level 1 anystate is stored while the logic analyzer searches for five occurrences of the pattern given by pattern recognizer a. When the five occurrences are found, the sequencer moves on to level 2.
An example of a state listing for the previous State Trace configuration is shown below. The state patterns specified are: a = B03C b = 0000 c = 8930 Figure 5-62. State Listing Example Anystate was stored while the analyzer looked for five occurrences of the state B03C. After the fifth occurrence was found, only state 0000 was stored until state 8930 was found, and the analyzer triggered. After the trigger, no states were stored.
Acquisition Fields The acquisition fields are comprised of the Trace mode, Armed by, Branches, Count, and Prestore fields, as shown below. 1 2 3 4 5 Figure 5-63. State Trace Acquistion Fields 1 Run/Trace Mode You specify the mode in which the timing analyzer will trace when you touch Run. You have two choices for trace mode: Single and Repetitive. When you touch Run and hold your finger on the field, you will see the following pop-up menu: Figure 5-64.
You select the trace mode by touching the Run field, and, without lifting your finger from the screen, move it to the desired trace mode. When you lift your finger, the logic analyzer traces data in the mode you specify. If you wish to abort the trace after you touch Run but before the trace starts, move your finger to Cancel before lifting your finger. Single Trace mode acquires data once per trace.
3 Branches The Branches field allows you to configure the sequencer of your state analyzer to branch from one sequence level to another with secondary branching qualifiers, or to restart when a certain condition is met. Selecting this field gives you the following pop-up menu. Figure 5-66. Branches Pop-up Menu Off. If you select Off, all secondary branching qualifiers are deleted from the sequence levels. Only the primary branches remain. Restart.
Per Level. Selecting the Per level option allows you to define a secondary branching qualifier for each sequence level. A statement is added in each level so that you can configure the analyzer to move to a different level when a specified condition is met. An example of a sequence level with a secondary branching qualifier is shown in the following figure. Secondary Branching Qualifier Figure 5-67.
Figure 5-68. Secondary Branch Qualifier in Last In this example, as the state analyzer stores anystate, it will branch to sequence level 6 if it finds the state given by qualifier e. The trigger sequence level is used as a boundary for branching between levels. This level and the levels that occur before it cannot branch to levels that occur after the trigger level, and vice versa.
Figure 5-69. Branching Between Sequence Levels Each sequence level can branch to only one level through a secondary branching qualifier. However, the number of times to which a level can be branched is limited only by the number of levels present. A level can have only one arrow pointing away from it, but it can have two pointing to it if more than one other level is branching to it. An example of this is shown in the figure below.
4 Count The Count field allows you to place tags on states so you can count them. Counting cuts the acquisition memory in half from 1k to 512, and the maximum clock rate is reduced to 16.67 MHz. Selecting this field gives you the following pop-up menu. Figure 5-71. Count Pop-up Menu Off. If you select Off, the states are not counted in the next measurement. Time. If you select Time counting, the time between stored states is measured and displayed in the State Listing under the label Time.
An example of a state listing with time tagging relative to the previous state is shown below. Figure 5-72. Relative Time Tagging An example of a state listing with time tagging relative to the trigger is shown below. Figure 5-73.
States. State tagging counts the number of qualified states between each stored state. If you select this option, you will see a qualifier pop-up menu like that shown in figure 5-48. You select the qualifier for the state that you want to count. In the State Listing, the state count is displayed under the label States. The count can be relative to the previous stored state or to the trigger. The maximum count is 4.4 × 1012.
An example of a state listing with state tagging relative to the trigger is shown below. Figure 5-75. Absolute State Tagging 5 Prestore Prestore allows you to store two qualified states before each state that is stored. There is only one qualifier that enables prestore for each sequence level. If you select this field, you will see a pop-up with the options Off and On.
Qualifier and Pattern Fields The qualifier and pattern fields appear at the bottom of the State Trace Specification menu. They allow you to specify patterns for the qualifiers that are used in the sequence levels. 1 2 4 3 Figure 5-76. Qualifier and Pattern Fields 1 Label HP 16510B Front-Panel Reference The Label fields display the labels that you specified in the State Format Specification menu. The labels appear in the order that you specified them; however, you can change the order.
2 Base The Base fields allow you to specify the number base in which you want to define a pattern for a label. The base fields also let you use a symbol that was specified in the State Symbol Table for the pattern. Each label has its own base defined separately from the other labels. If you select one of the base fields, you will see the following pop-up menu. When you decide which base you want to define your pattern in, select that option. One of the options in the Base pop-up is ASCII.
3 Qualifier Field If you select the qualifier field, you will see the following pop-up menu. Figure 5-78. Qualifier Field Pop-up Menu Patterns. The pattern recognizers are in two groups of four: a-d and e-h. If you select one of these two options, the qualifier field will contain only those pattern recognizers. For instance, the qualifier field in figure 5-76 contains only the recognizers a-d. Ranges. If you select the range option, the qualifier and pattern fields look similar to that shown below.
Only one range can be defined, and it can be defined over only one label, hence over only 32 channels. The channels don’t have to be adjacent to each other. The logic analyzer selects the label over which the range will be defined by looking at the labels in order and choosing the first one that has channels assigned under only two pods. A label that contains channels from more than two pods cannot be selected for range definition.
6 Interpreting the Display Introduction This chapter describes the Timing Waveforms and State Listing menus and how to interpret them. It also tells you how to use the fields in each of these menus to manipulate the displayed data so you can find your measurement answers. The Timing Waveforms Menu The Timing Waveforms menu is the display menu of the timing analyzer.
The waveforms area displays the data the timing analyzer acquires. The data is displayed in a format similar to an oscilloscope with the horizontal axis representing time and the vertical axis representing amplitude. The basic difference between an oscilloscope display and the timing waveforms are: the vertical axis only displays highs (above threshold) and lows (below threshold); lows are represented by a darker line for easy differentiation. Figure 6-2.
Markers (Timing) The Markers field allows you to specify how the X and O markers will be positioned on the timing data. The options are: • • • • Markers Off/ Sample Period Note Off Time Patterns Statistics When the markers are off they are not visible and the sample rate is displayed. In transitional timing mode, the sample rate will always be 10 ns. In Glitch, the sample period is controlled by the s/Div setting and can be monitored by turning the markers off.
To position the markers, touch the appropriate field for marker selection. The field will turn light blue and can then be set using the knob. The Trig to X field controls the green marker and the Trig to O field controls the yellow marker. The trigger point is displayed with the red marker. To set the markers at a predetermined time relationship, touch the field a second time, the field will turn white and a numeric keypad will appear.
Markers Pattern When the markers are set to pattern you can specify patterns that the logic analyzer will place the markers on. You can also specify how many occurrences of each marker pattern the logic analyzer looks for. This use of the markers allows you to find time between specific patterns in the acquired data. Figure 6-6. Markers Patterns Menu Patterns for each marker (X and O) can be specified.
Markers Statistics When statistics are specified for markers, the logic analyzer displays: • • Number of total runs Number of valid runs (runs where markers were able to be placed on specified patterns) • Minimum time between the X and O markers • Maximum time between the X and O markers • Average time between the X and O markers Statistics are based on the time between markers which are placed on specific patterns.
At ___ marker The At X (or O) marker _______ fields allow you to select either the X or O markers. You can place these markers on the waveforms of any label and have the logic analyzer tell you what the pattern is. For example, in the following timing waveforms display, the number 35 to the right of the field containing ADDR is the pattern in hexadecimal that is marked by the X marker. The base of the displayed field is determined by the base of the specified label you selected in the timing Trace menu.
The next field to the right of the At____ marker field will pop up when selected and show you all the labels assigned to the timing analyzer as shown below. Figure 6-8. Label Option Pop-up s/Div (secondsper-division) Field The seconds-per-division field allows you to change the time window of the Timing Waveforms menu. To activate the s/Div field you must touch the field. The field will turn light blue indicating it can be controlled by the knob.
Delay Field The delay field allows you to enter a delay. The delay can be either positive or negative. Delay allows you to place the time window (selected by s/Div) of the acquired data at center screen. The center tic mark at the horizontal center and top of the waveforms area represents trigger + delay. The red vertical dotted line represents the trigger point (see figure 6-9). Figure 6-9. Trigger and Trace Points If you want to trace after the trigger point, enter a positive delay.
In Glitch mode the maximum delay is 25 seconds, which is controlled by memory and sample period (512 X 50 ms). The sample rate is also dependent on the delay setting.
The listing area shows the data the state analyzer acquires. The data is displayed in a listing format as shown below. Figure 6-10. State Listing Menu This listing display shows you 16 of the possible 1024 lines of data at one time. You can use the knob to roll the listing to the lines of interest. The column of numbers at the far left represent the location of the acquired data in the state analyzer’s memory. The trigger state is always 0.
State Listing Menu Fields The menu area contains fields that allow you to change the display parameters, place markers, and display listing measurement parameters. Figure 6-11. State Listing Menu Fields Markers (State) The two markers (X & O) are horizontal lines that appear crossing the data area of the display when they are turned on. Each marker has a unique color and the border of its respective marker field is the same color.
Markers Off When the markers are off they are not displayed, but are still placed at the specified points in the data. If Stop measurement is on and the Stop measurement criteria are present in the data, the measurement will stop even though the markers are off. Markers Pattern When the markers are set to patterns, you can specify patterns on which the logic analyzer will place the markers. You can also specify how many occurrences of each marker pattern the logic analyzer looks for.
Another feature of markers set to patterns is the Stop measurement when X-O ___ which is found in the Specify Patterns field. The options are: • • • • • Off Less than Greater than In range Not in range This feature is only available when Count is set to Time in the Trace menu. With this feature you can use the logic analyzer to look for a specified time or range of time between the marked patterns and to stop acquiring data when it finds this time between markers. The X marker must precede the O marker.
The Time X to O field will change according to the position of the X and O markers. It displays the total time between the states marked by the X and O markers.
Timing/State Mixed Mode Display When both timing and state analyzers are on, you can display both the State Listing and the Timing Waveforms simultaneously as shown. Figure 6-15. Timing/State Mixed Mode Display The data in both parts of the display can be time correlated as long as Count (State Trace menu) is set to Time. The markers for the State Listing and the Timing Waveform in time-correlated Mixed Mode are different from the markers in the individual displays.
State/State Mixed Mode Display When two state analyzers are on, the logic analyzer can display both state listings as shown in figure 6-16. The acquired data of both machines is interlaced. The State/State mixed mode can be set up in either Listing 1 or Listing 2. For example, the mixed display in figure 6-16 is in Listing 1. The data acquired by machine 1 is displayed with the state location numbers centered in the far left column.
To display a two state mixed mode listing you must start with a single state listing. In this example, Listing 1 is the starting point. The desired display is: • • • • addresses of machine 1 inverse assembled data of machine 1 data on the data bus of machine 2 status of machine 2 Start with the Listing 1 display by touching the STAT field. The following pop-up appears: Figure 6-17.
The pop-up will close and machine 2 will supply data for this label location on screen. Figure 6-18. Machine Selection Pop-up Menu You now must specify what label you want from machine 2. The field to the left of the machine pop-up allows you to select a label from the labels assigned to machine 2. Touch this field to view the labels assigned to machine 2. Figure 6-19.
When the pop-up appears, touch the "DATA" field. Figure 6-20. Machine 2 Labels Pop-up Menu When you are finished selecting the machine and the label, touch Done to close the original pop-up. The data from machine 2 replaces STAT in Listing 1. Time-Correlated Displays The HP 16510B Logic Analyzer can time-correlate data between the timing analyzer and the state analyzer and between two state analyzers.
7 Using The Timing Analyzer Introduction In this chapter you will learn how to use the timing analyzer by setting up the logic analyzer to make a simple measurement. We give you the measurement results as actually measured by the logic analyzer, since you may not have the same circuit available. The exercise in this chapter is organized in a task format. The tasks are ordered in the same way you will most likely use them once you become an experienced user.
What Am I Going to Measure? After configuring the logic analyzer and hooking it up to your circuit under test, you will be measuring the time (x) from when the RAS goes low to when the CAS goes high, as shown below. Figure 7-1. RAS and CAS Signals How Do I Configure the Logic Analyzer? In order to make this timing measurement, you must configure the logic analyzer as a timing analyzer. By following these steps you will configure Analyzer 1 as the timing analyzer.
3. Name Analyzer 1 "DRAM TEST" (optional) a. Touch the field to the right of Name:_______ of Analyzer 1. b. Using the alphanumeric keyboard pop-up, change the name of Analyzer 1 to "DRAM TEST." 4. Assign pod 1 to the timing analyzer. a. Touch the Pod 1 field. b. When the pop-up appears, touch DRAM TEST (or Machine 1) to assign pod 1 to Analyzer 1. Figure 7-2.
Connecting the Probes At this point, if you had a target system with a 4116 DRAM memory IC, you would connect the logic analyzer to your system. Since you will be assigning Pod 1 bit 0 to the RAS label, you hook Pod 1 bit 0 to the memory IC pin connected to the RAS signal. You hook Pod 1 bit 1 to the IC pin connected to the CAS signal.
1. Display the Timing Format Specification menu. a. Touch the field second from the left in the upper left corner. b. When the pop-up appears, touch the Format 1 field. 2. Name two labels, one RAS and one CAS. a. Touch the top field in the label column. b. When the pop-up appears, touch Modify Label. c. Using the alphanumeric keyboard, enter the label RAS and touch DONE. d. Touch the next field down from the RAS label and repeat steps b and c for the CAS label. Figure 7-4.
3. Assign the channels connected to the input signals (Pod 1 bits 0 and 1) to the labels RAS and CAS respectively. a. Touch the bit assignment field below Pod 1 and to the right of RAS. b. Any combination of bits may be assigned to this pod; however, you will want only bit 0 assigned to the RAS label. The easiest way to assign bits is to touch CLEAR to un-assign any assigned bits before you start. c.
Specifying a Trigger Condition To capture the data and then place the data of interest in the center of the display of the timing waveform menu, you need to tell the logic analyzer when to trigger. Since the first event of interest is when the LRAS is asserted (negative-going edge of RAS), you need to tell the logic analyzer to trigger on a negative-going edge of the RAS signal. 1. Display the Timing Trace Specification menu. a. Touch the field second from the left in the upper left corner. b.
Acquiring the Data Now that you have configured and connected the logic analyzer, you acquire the data for your measurement by touching the Run field. The display switches to the Timing Waveforms menu when the logic analyzer starts acquiring data. The logic analyzer will look for a negative edge on the RAS signal and trigger if it sees one. Figure 7-6.
Figure 7-7. RAS and CAS Labels The RAS label shows you the RAS signal and the CAS label shows you the CAS signal. Notice the RAS signal goes low at or near the center of the waveform display area (horizontal center).
The Timing Waveform Menu The timing waveform menu differs from the other menus you have used so far in this exercise. Besides displaying the acquired data, it has menu fields that you use to change the way the acquired data is displayed and fields that give you timing answers. Before you can use this menu to find answers, you need to know some of the special symbols and their functions.
Display Resolution You get the best resolution by changing the seconds per division (s/Div) to a value that displays one negative-going edge of both the RAS and CAS waveforms. Set the s/Div by following these steps. Figure 7-8. RAS and CAS Signals 1. Touch the s/Div field one time (the field will turn light blue) to allow you to adjust the horizontal scaling with the front-panel knob.
Making The Measurement What you want to know is how much time elapses between the time RAS goes low and the time CAS goes high again. You will use the X and O markers to quickly find the answer. Remember you specified the negative-going edge of the RAS to be your trigger point, therefore the X marker (green) should be on this edge if the X to Trig field = 0. If not, follow steps 1 and 2. 1. Touch the Trig to X field. The field will turn light blue.
Finding the Answer Your answer could be calculated by adding the Trig to X and Trig to O times, but you don’t have to. The logic analyzer has already calculated this answer and displays it in the X to O field on the display. This example indicates the time is 710 ns. Since the data book specifies a minimum of 250 ns, it appears your DRAM controller circuit is designed properly. Figure 7-11.
Summary You have just learned how to make a simple timing measurement with the HP 16510B logic analyzer.
8 Using The State Analyzer Introduction In this chapter you will learn how to use the state analyzer by setting up the logic analyzer to make a simple state measurement. We give you the measurement results as actually measured by the logic analyzer, since you may not have the same circuit available. The exercise in this chapter is organized in a task format. The tasks are ordered in the same way you will most likely use once you become an experienced user.
What Am I Going to Measure? You decide to start where the microprocessor starts when power is applied. We will describe a 68000 microprocessor; however, every processor has similar start-up routines. When you power up a 68000 microprocessor it is held in reset for a specific length of time before it starts doing anything to stabilize the power supplies. The time the microprocessor is held in reset ensures stable levels (states) on all the devices and buses in your circuit.
Your measurement, then, requires verification of the sequential addresses the microprocessor looks to and of the data in ROM at these addresses. If the reset vector fetch is correct (in this example), you will see the following list of numbers in HEX (default base) when your measurement results are displayed. +0000 +0001 +0002 +0003 +0004 000000 000002 000004 000006 008048 0000 04FC 0000 8048 3E7C This list of numbers will be explained in detail later in this chapter in "The State Listing.
3. Name Analyzer 1 68000STATE (optional) a. Touch the field to the right of Name: ________. b. When the alphanumeric keyboard pop-up appears, touch the appropriate keys to change the name to 68000STATE. c. Touch DONE when you finish entering the name. 4. Assign pods 1, 2, and 3 to the state analyzer. a. Touch Pod 1 field if it is not already assigned to the state analyzer. b. In the Pod 1 pop-up, touch the field labeled 68000STATE. c. Repeat steps a and b for pods 2 and 3.
Connecting the Probes At this point, if you had a target system with a 68000 microprocessor, you would connect the logic analyzer to your system. Since you have assigned labels ADDR and DATA, you would hook the probes to your system accordingly. • • • • Activity Indicators Pod 1 probes 0 through 15 to the data bus lines D0 through D15. Pod 2 probes 0 through 15 to the address bus lines A0 through A15. Pod 3 probes 0 through 7 to the address bus lines A16 through A23.
Configuring the State Analyzer Now that you have configured the system, you are ready to configure the state analyzer. You will be: • • • • Creating two names (labels) for the input signals Assigning the channels connected to the input signals Specifying the State (J) clock Specifying a trigger condition 1. Display the State Format Specification menu. a. Touch the field second from the left at the top of the screen. b. When the pop-up appears, touch the field labeled Format 1. Figure 8-3.
Figure 8-4. Label Selection b. When the pop-up appears, touch Modify Label. c. With the alphanumeric keypad, change the name of the label to ADDR. d. Touch DONE to close pop-up. e. Name the second label DATA. Figure 8-5.
3. Assign Pod 1 bits 0 through 15 to the label DATA. a. Touch the bit assignment field below Pod E1 and to the right of DATA. You will see the following pop-up. Figure 8-6. Bit Assignment Field Any combination of bits may already be assigned to this pod; however, you will want all 16 bits assigned to the DATA label. b. Using the knob, place the cursor on each un-assigned bit (one at a time and touch the asterisk (*) field. When all 16 bits are assigned, touch DONE to close the pop-up. Figure 8-7.
4. Assign Pod E2 bits 0 through 15 to the label ADDR by repeating step 3. 5. Assign Pod E3 bits 0 through 7 to the label ADDR. 6. Unassign any assigned bits in the ADDR label under Pod E1. The State Format Specification menu should now look like that below. Figure 8-8.
Specifying the J Clock If you remember from "What’s a State Analyzer" in Feeling Comfortable With Logic Analyzers, the state analyzer samples the data under the control of an external clock which is "synchronous" with your circuit under test. Therefore, you must specify which clock probe you will use for your measurement. In this exercise, you will use the J clock which is accessible through pod 1. 1. Display the State Format Specification menu. 2. Set the J Clock to sample on a negative-going edge. a.
b. In the pop-up, touch the field to the right of J. Figure 8-10. J Clock Selection c. Touch the field with the arrow pointing down to select a negative going edge. Figure 8-11. Negative-edge Selection 3. Turn off all other clocks (K-N) if any are on by repeating steps a through c using the Off option and then touch Done to close the pop-up.
The State Format Specification menu should look like that shown below. Figure 8-12.
Specifying a Trigger Condition To capture the data and place the data of interest in the center of the display of the state listing menu, you need to tell the state analyzer when to trigger. Since the first event of interest is address 0000, you need to tell the state analyzer to trigger when it detects address 0000 on the address bus. 1. Display the State Trace Specification menu. a. Touch the field second from the left at the top of the screen. b. Touch the field labeled Trace 1. Figure 8-13.
Figure 8-14. Sequence Levels b. In the pop-up, touch the field to the right of the TRIGGER on field. This field may either contain a or anystate. Another pop-up appears showing you a list of "TRIGGER on" options. Options a through h are qualifiers that allow you to assign a pattern for the trigger specification. c. Touch the field with the "a" option. Figure 8-15.
d. Touch the field labeled Done in the Sequence Levels pop-up. e. Touch the field to the right of "a" under the label ADDR. Figure 8-16. Address Pattern Selection Keypad f. With the pop-up keypad, touch the 0 (zero) key until all zeroes appear in the display space above the keypad. Touch the Done field to close pop-up. Figure 8-17.
Your trigger specification now states: "While storing anystate, trigger on "a" 1 times and then store anystate." Figure 8-18. State Trace Specification When the state analyzer is connected to your circuit and is acquiring data, it continuously stores until it sees 0000 on the address bus, at which time it begins to store anystate until the analyzer memory is filled.
Figure 8-19. Acquiring Data When you touch the Run field a pop-up appears next to it with the options Single, Repetitive, and Cancel. Without lifting your finger from the screen, move it to the field labeled Single. Single will turn white. Figure 8-20.
If you want to go to the state listing menu before taking a measurement, touch the field second from the left at the top of the screen. When the pop-up appears, touch the field labeled Listing 1. Since you want to capture the data when the microprocessor sends address 0000 on the bus after power-up, you touch the Run field to arm the state analyzer and then force a reset of your circuit.
State Locations Figure 8-22. State Listing showing State Locations The State Listing The state listing displays three columns of numbers as shown: The first column of numbers are the state line number locations as they relate to the trigger point. The trigger state is on the line 0 in the vertical center of the list area. The negative numbers indicate states occurring before the trigger and the positive numbers indicate the states occurring after the trigger.
Finding the Answer Your answer is now found in this listing of the states +0000 through +0004. The 68000 always reads address locations 0, 2, 4, and 6 to find the stack pointer location and memory location for the instruction it fetches after power-up. The 68000 uses two words for each of the locations that it is looking for, a high word and a low word. When the software designer programs the ROM he must put the stack pointer location at address locations 0 and 2.
So far you have verified that the microprocessor has performed the correct reset vector search. The next thing you must verify is whether the microprocessor addresses the correct location in ROM that it was instructed to address in state 4 and whether the data is correct in this ROM location. From the listing you see that the address in state 4 is 008048, which is correct, but the instruction found in this location is 2E7C, which is not correct.
Summary You have just learned how to make a simple state measurement with the HP 16510B Logic Analyzer. You have: • • • • • • • • • specified a state analyzer learned which probes to connect assigned pods 1, 2, and 3 assigned labels assigned bits specified the J clock specified a trigger condition acquired the data interpreted the State Listing You have seen how easy it is to use the state analyzer to capture the data on the address and data buses.
9 State Compare Menu Introduction State compare is a software post-processing feature that provides the ability to do a bit by bit comparison between the acquired state data listing and a compare data image. You can view the acquired data and the compare image separately. In addition, there is a separate difference listing that highlights the bits in the acquired data that do not match the corresponding bits in the compare image. Each state machine has its own Compare and Difference listings.
Accessing the Compare Menu The Compare menu is accessed by selecting the field directly to the right of the Module select field in the upper left corner of the screen. When the pop-up appears you will see the options Compare 1, Compare 2 or both depending on which analyzer is a state analyzer. If both analyzers are state analyzers you will see both Compare 1 and Compare 2. You select your desired option by touching the appropriate field in the pop-up.
The controls that roll the list in all three menus, the normal State Listing, the Compare Listing, and the Difference Listing are synchronized. This means that when you change the current row position in the Difference Listing, the logic analyzer automatically updates the current row in the acquired State Listing, Compare Listing and vice-versa. This allows you to view corresponding areas of the two lists, to cross check the alignment, and analyze the bits that do not match.
Bit Editing of the Compare Image Bit editing allows you to modify the values of individual bits in the compare image or specify them as don’t compare bits. The bit editing fields are located in the center of the Compare Listing display to the right of the listing number field (see figure 9-1). A bit editing field exists for every label in the display. You can access any data in the Compare Listing by rolling the desired row vertically until it is located in the bit editing field for that label (column).
Masking Channels in the Compare Image The channel masking function allows you to specify a bit, or bits in each label that you do not want compared. This causes the corresponding bits in all states to be ignored in the comparison. The compare data image itself remains unchanged on the display. The Mask fields are directly above the label and base fields at the top of both the Compare and Difference listings (see figure 9-2).
Specifying a Compare Range The Compare Range function allows you to define a subset of the total number of states in the compare image to be used in the comparison. The range is specified by setting start and stop boundaries. Only bits in states (lines) on or between the boundaries are compared against the acquired data. This function can be accessed by selecting the "Compare Full"/"Compare Partial" field in either the Compare or Difference listing menus (see figure 9-3).
Repetitive Comparisons with a Stop Condition When you do a comparison in the repetitive trace mode, a stop condition should be specified. The stop condition is either "Stop Measurement" when Compare is "Equal," "Not Equal" or "Off." In the case of "Equal", bits in the compare image must match the corresponding bits in the acquired data image for the stop condition to be a TRUE. In the case of "Not Equal", a mismatch on a single bit will cause the stop condition to be TRUE.
Note Locating Mismatches in the Difference Listing You may also specify a stop measurement based on time between the X and O markers in the Compare or Difference Listing menus. This is available only when time tags are on. If the Stop Measurement is specified to run until "Compare Equal" or "Compare Not Equal" in the Compare or Difference Listings, the Stop Measurement on time X to O will not be available in another menu (i.e. State Listing).
10 State Waveform Menu Introduction The State Waveform Menu allows you to view state data in the form of waveforms identified by label name and bit number. Up to 24 waveforms can be displayed simultaneously. Only state data from the current state machine can be displayed as waveforms in the State Waveforms menu. Any intermodule label (i.e., oscilloscope or 1 GHz Timing ) that was selected when the current machine was a timing analyzer will be deleted when selecting the State Waveform menu.
Selecting a Waveform You can display up to 24 waveforms on screen at one time. Each waveform is a representation of a predefined label. To select a waveform, touch the blue bar (field) on the left side of the waveform portion of the display (see figure 10-1). Waveform Selection Field Figure 10-1. Waveform Selection Field A pop-up menu appears in which you select the label, by name, that you want to display (see figure 10-2). Figure 10-2.
Each waveform can display any one or all bits (channels) of a label or it can be turned off. The specific bit or bits of a label that will be displayed depends on what Channel Mode is currently displayed when you select the label. If Sequential is currently displayed, all the label bits will be inserted individually in the display (see figure 10-3). Figure 10-3.
If Overlay is currently displayed, all bits of the label are inserted in a single waveform to form a composite waveform (see figure 10-5). Figure 10-5. Overlay Channel Mode In the above figure, label A has all of its bits specified to be overlaid in the waveform display. The on-screen indication for the Overlay mode is All following the label name.
Replacing Waveforms You can replace a currently displayed waveform (label) with another one of the predefined waveforms (labels). To replace one waveform with another, place the cursor on the waveform you wish to replace using the knob. Touch the Action Insert field to toggle it to Action Replace (see figure 10-6). Then select the label that will replace the old label. Figure 10-6.
Selecting Samples per Division You can specify the samples per division by entering the number of states per division either with a keypad or the knob. The range is from 1 to 104 per division. Delay from Trigger You can specify the delay from trigger by specifying the number of states from the trigger. The minimum is −1023 and the maximum is 1024 independent of trace position in the record. Delay is not limited to the window containing data.
11 State Chart Menu Introduction The State Chart Menu allows you to build X-Y plots of label activity using state data. The Y-axis always represents data values for a specified label. You can select whether the X-axis represents states (i.e., rows in the State List) or the data values for another label. You can scale both the axes for selective viewing of the data of interest. An accumulate mode allows the chart display to build up over several runs.
Scaling the Axes Either axis can be scaled by using the vertical or horizontal min (minimum) or max (maximum) value fields. When you select any one of the min or max fields a pop up appears in which you specify the actual minimum and maximum values that will be displayed on the chart (see figure 11-1). Figure 11-1. Axis Scaling Pop-up Menu When States are plotted on the X-axis the minimum and maximum values range from -1023 to +1024 depending on the trigger point location.
The Label Value vs. States Chart The Label Value vs. State chart is a plot of label activity versus the memory location in which the label data is stored. The label value is plotted against successive analyzer memory locations. For example, in the following figure, label activity of POD 1 is plotted on the Y axis and the memory locations (States) are plotted on the X axis. Figure 11-2. Label vs.
The Label Value vs. Label Value Chart When labels are assigned to both axis, the chart shows how one label varies in relation to the other for a particular state trace record. Label values are always plotted in ascending order from the bottom to the top of the chart and in ascending order from left to right across the chart. Plotting a label against itself will result in a diagonal line from the lower left to upper right corner. X and O markers are disabled when operating in this mode. Figure 11-3.
X & O Markers for Chart When State is specified for the X-axis, X and O markers are available which can be moved horizontally which are synchronized with the X and O markers in the normal State Listing. To select the marker mode for Chart (if it is not presently displayed), select the Range field in the top center of the display. This field will toggle to Markers and the marker selection fields will appear (see figure 11-4). Figure 11-4.
Marker Options The marker options in the State Chart menu depend on what Count is set to in the State Listing menu.
12 Using the Timing/State Analyzer Introduction In this chapter you will learn how to use the timing and state analyzers interactively by setting up the logic analyzer to make a simple measurement. We give you the measurement results as actually measured by the logic analyzer, since you may not have the same circuit available. The exercise in this chapter is organized differently than the two previous chapters.
Problem Solving with the Timing/State Analyzer In this example assume you have designed a microprocessor controlled circuit. You have completed the hardware, and the software designer has completed the software and programmed the ROM. When you turn your circuit on for the first time, your circuit doesn’t work properly. You have checked the power supply voltages and the system clock and they are working properly.
How Do I Configure the Logic Analyzer? In order to make this measurement, you must configure the logic analyzer as a state analyzer because you want to trigger on a specific state (8930). You also want to verify that the addresses and data are correct in the states of this routine. Configure the logic analyzer so that Analyzer 1 is a state analyzer as shown: Figure 12-1.
Configuring the State Analyzer Now that you have configured the system, you are ready to configure the state analyzer. Configure the State Format Specification (Format 1) as shown: Figure 12-2. State Format Specification Menu Configure the State Trace Specification (Trace 1) as shown: Figure 12-3.
Connecting the Probes At this point, if you had a target system with a 68000 microprocessor, you would connect the logic analyzer to your system. Since you have assigned labels ADDR and DATA, you would hook the probes to your system accordingly.
As you compare the state listing (shown below), you notice the data at address 8932 is incorrect. Now you need to find out why. Incorrect Data Figure 12-4. Incorrect Data Your first assumption is that incorrect data is stored in this memory location. Assume this routine is in ROM since it is part of the operating system for your circuit. Since the ROM is programmed by the software designer, you have the software designer verify the data at address 8932 is correct.
Now it’s time to look at the hardware to see if it is causing incorrect data when the microprocessor reads this memory address. You decide you want to see what is happening on the address and data buses during this routine in the time domain. In order to see the time domain, you need the timing analyzer.
How Do I Re-configure the Logic Analyzer? In order to make this measurement, you must re-configure the logic analyzer so Analyzer 2 is a timing analyzer. You leave Analyzer 1 as a state analyzer since you will use the state analyzer to trigger on address 8930. Configure the logic analyzer so Analyzer 2 is a timing analyzer as shown: Figure 12-5.
Configuring the Timing Analyzer Now that you have configured the system, you are ready to configure the timing analyzer. Configure the Timing Format Specification (Format 2) as shown: Figure 12-6. Timing Format Specification Menu Configure the timing Trace specification (Trace 2) as shown: Figure 12-7.
Setting the Timing Analyzer Trigger Your timing measurement requires the timing analyzer to display the timing waveforms present on the buses when the routine is running. Since you triggered the state analyzer on address 8930, you want to trigger the timing analyzer so the timing waveforms can be time correlated with the state listing. To set up the logic analyzer so that the state analyzer triggers the timing analyzer, perform these steps: 1. Display the Timing Trace Specification menu (Trace 2). 2.
Time Correlating the Data In order to time correlate the data, the logic analyzer must store the timing relationships between states. Since the timing analyzer samples asynchronously and the state analyzer samples synchronously, the logic analyzer must use the stored timing relationship of the data to reconstruct a time correlated display. To set up the logic analyzer to keep track of these timing relationships, turn on a counter in the State Trace Specification menu. The following steps show you how: 1.
The Timing Waveform Menu Displaying the Waveforms After pods 4 and 5 are connected, you can re-acquire the data. However, first assign the labels in the Timing Waveform menu. Display the Timing Waveform menu. Touch the long blue field on the left side of the screen. The pop-up should look like that below: Long Light Blue Field Figure 12-10. Timing Waveform Menu Touch the labels CLOCK, AS, UDS, LDS, DTACK, and R/W in that order. They will appear in the blue label area. Figure 12-11.
This is not the order we want them in. We want LDS before UDS. To correct this, follow these steps: 1. Use the knob to place the cursor on the label LDS in the long blue label field. 2. Touch the field labeled Delete. This erases LDS. Figure 12-12. Delete Label 3. Use the knob to place the cursor over the label AS. Touch the LDS field under Labels in the pop-up. Figure 12-13.
LDS appears in the blue label area in the correct position. Figure 12-14. Labels in Correct Position Now we want to put ADDR and DATA in the long blue label area. Position the cursor on R/W in the long blue label field. Touch ADDR under Labels in the pop-up. Since ADDR has eight bits assigned to it, eight labels appear in the label field, one for each bit, as shown. Figure 12-15.
This also occurs for DATA, as shown: Figure 12-16. Individual Data Labels If you want to see the waveforms of each bit, you would leave the display as it is. However, this makes the waveform display very crowded. An easy solution is overlapping the waveforms. Overlapping Timing Waveforms A convenient method of displaying the waveforms of all the bits in ADDR and DATA is to overlap them. To overlap the bits for ADDR and those for DATA, follow these steps. 1.
2. Touch the filed labeled Channel Mode Sequential. Figure 12-17. Channel Mode Sequential Menu 3. In the new pop-up, touch the field labeled Overlay. Figure 12-18.
4. Touch the ADDR label field under Labels. 5. Touch the DATA label field under Labels. The screen should look like that shown below. Figure 12-19. Overlapped Waveforms In the long blue label field ADDR and DATA have "all" next to them to show that the bits are overlapped. Touch the Done field to close the pop-up. Re-acquiring the Data HP 16510B Front-Panel Reference Now you are ready to acquire the data. Touch Run.
Finding the Answer As you look at the overlapping waveforms, you notice there are transitions on the data lines during the read, indicating the data is unstable, which is the probable cause of the problem you’ve been looking for. You have found what is causing the problem in this routine. Additional troubleshooting of the hardware will lead you to the actual cause. Unstable Data Figure 12-20.
13 Using a Printer Setting Printer Configuration All printer parameters are set in the System Configuration menu. If you have just connected your printer and are unsure of how to set the configuration, refer to the HP 16500A Reference Manual chapter entitled Connecting a Printer. The HP 16500A supports HP-IB and selected RS-232C printers. All the pictures in this manual were taken from an HP 16500A with one HP 16510A logic analyzer card.
If you are in the State Listing, a slightly different pop-up will appear, like the one shown in figure 13-2. Figure 13-2. Print Option in Listing Menu The pop-up contains three fields, Cancel, Print Screen, and Print All. Printing OnScreen Data If you want a hardcopy record of the screen, touch the Print field and then the Print Screen field from the pop-up. This will send a copy of the screen to the printer in graphics mode.
14 Microprocessor Specific Measurements Introduction This chapter contains information about the optional accessories available for microprocessor specific measurements. In depth measurement descriptions are in the operating notes that come with each of these accessories. The accessories you will be introduced to in this chapter are the preprocessor modules and the HP 10269C General Purpose Probe Interface.
The inverse assembler file is a software routine that will display captured information in a specific microprocessor’s mnemonics. The DATA field in the state listing is replaced with an inverse assembly field (see Figure 14-1). The inverse assembler software is designed to provide a display that closely resembles the original assembly language listing of the microprocessor’s software. It also identifies the microprocessor bus cycles captured, such as Memory Read, Interrupt Acknowledge, or I/O write.
Z80 CPU Package: 40-pin DIP Accessories Required: HP 10300B Preprocessor HP 10269C General Purpose Probe Interface Maximum Clock Speed: 10 MHz clock input Signal Line Loading: Maximum of one 74LS TTL load + 35 pF on any line Microprocessor Cycles Identified: Maximum Power Required: Memory read/write I/O read/write Opcode fetch Interrupt acknowledge RAM refresh cycles 0.
NSC 800 CPU Package: 40-pin DIP Accessories Required: HP 10304B Preprocessor HP 10269C General Purpose Probe Interface Maximum Clock Speed: 4 MHz clock input Signal Line Loading: Maximum of one HCMOS load + 35 pF on any line Microprocessor Cycles Identified: Maximum Power Required: Memory read/write I/O read/write Opcode fetch Interrupt acknowledge RAM refresh cycles DMA cycles 0.
8085 CPU Package: 40-pin DIP Accessories Required: HP 10304B Preprocessor HP 10269C General Purpose Probe Interface Maximum Clock Speed: 6 MHz clock output (12 MHz clock input) Signal Line Loading: Maximum of one 74LS TTL load + 35 pF on any line Microprocessor Cycle Identified: Maximum Power Required: Memory read/write I/O read/write Opcode fetch Interrupt acknowledge 0.
8086 or 8088 CPU Package: 40-pin DIP Accessories Required: HP 10305B Preprocessor HP 10269C General Purpose Probe Interface Maximum Clock Speed: 10 MHz clock input (at CLK) Signal Line Loading: Maximum of two 74ALS TTL loads + 40 pF on any line Microprocessor Cycles Identified: Memory read/write I/O read/write Code fetch Interrupt acknowledge Halt acknowledge Transfer to 8087 or 8089 co-processors Additional Capabilities: The 8086 or 8088 can be operating in Minimum or Maximum modes.
80186 or 80188 CPU Package: 68-contact LCC Accessories Required: HP 10306B Preprocessor HP 10269C General Purpose Probe Interface Maximum Clock Speed: 8 MHz clock output (16 MHz clock input) Signal Line Loading: Maximum of two 74ALS TTL loads + 40 pF on any line Microprocessor Cycles Identified: Memory read/write (DMA and non-DMA) I/O read/write (DMA and non-DMA) Code fetch Interrupt acknowledge Halt acknowledge Transfer to 8087, 8089, or 82586 co-processors Additional Capabilities: The 80186 or 80188
80286 CPU Package: 68-contact LCC or 68-pin PGA Accessories Required: HP 10312B Preprocessor HP 10269C General Purpose Probe Interface Maximum Clock Speed: 10 MHz clock output (20 MHz clock input) Signal Line Loading: Maximum of two 74ALS TTL loads + 40 pF on any line Microprocessor Cycles Identified: Memory read/write I/O read/write Code fetch Interrupt acknowledge Halt Hold acknowledge Lock Transfer to 80287 co-processor Additional Capabilities: The logic analyzer captures all bus cycles, including p
80386 CPU Package: 132-pin PGA Accessories Required:HP 10314B Preprocessor HP 10269C General Purpose Probe Interface Maximum Clock Speed: 20 MHz clock output (40 MHz clock input) Signal Line Loading: Maximum of two 74ALS TTL loads + 80 pF on any line Microprocessor Cycles Identified: Memory read/write Memory read/write I/O read/write Code fetch Interrupt acknowledge, type 0-255 Halt Shutdown Transfer to 8087, 80287, or 80387 co-processors Additional Capabilities: The logic analyzer captures all bus cycle
6800 or 6802 CPU Package: 40-pin DIP Accessories Required: HP 10307B Preprocessor HP 10269C General Purpose Probe Interface Maximum Clock Speed: 2 MHz clock input Signal Line Loading: Maximum of 1 74LS TTL load + 35 pF on any line Microprocessor Cycle Identified: Maximum Power Required: Memory read/write DMA read/write Opcode fetch/operand Subroutine enter/exit System stack push/pull Halt Interrupt acknowledge Interrupt or reset vector 0.
6809 or 6809E CPU Package: 40-pin DIP Accessories Required: HP 10308B Preprocessor HP 10269C General Purpose Probe Interface Maximum Clock Speed: 2 MHz clock input Signal Line Loading: Maximum of one 74ALS TTL load + 35 pF on any line Microprocessor Cycles Identified: Memory read/write DMA read/write Opcode fetch/operand Vector fetch Halt Interrupt Additional Capabilities: The preprocessor can be adapted to 6809/09E systems that use a Memory Management Unit (MMU).
68008 CPU Package: 40-pin DIP Accessories Required: HP 10310B Preprocessor HP 10269C General Purpose Probe Interface Maximum Clock Speed: 10 MHz clock input Signal Line Loading: Maximum of one 74S TTL load + one 74F TTL load + 35 pF on any line Microprocessor Cycles Identified: User data read/write User program read Supervisor read/write Supervisor program read Interrupt acknowledge Bus grant 6800 cycle Additional Capabilities: The logic analyzer captures all bus cycles, including prefetches Maximum Po
68000 and 68010 (64-pin DIP) CPU Package: 64-pin DIP Accessories Required: HP 10311B Preprocessor HP 10269C General Purpose Probe Interface Maximum Clock Speed: 12.
68000 and 68010 (68-pin PGA) CPU Package: 68-pin PGA Accessories Required: HP 10311G Preprocessor Maximum Clock Speed: 12.5 MHz clock input Signal Line Loading: 100 KΩ + 10 pF on any line Microprocessor Cycles Identified: User data read/write User program read Supervisor read/write Supervisor program read Interrupt acknowledge Bus Grant 6800 cycle Additional Capabilities: The logic analyzer captures all bus cycles, including prefetches.
68020 CPU Package: 114-pin PGA Accessories Required: HP 10313G Maximum Clock Speed: 25 MHz clock input Signal Line Loading: 100 KΩ + 10 pF on any line Microprocessor Cycles Identified: User data read/write User program read Supervisor read/write Supervisor program read Bus Grant CPU space accesses including: Breakpoint acknowledge Access level control Coprocessor communication Interrupt acknowledge Additional Capabilities: The logic analyzer captures all bus cycles, including prefetches.
68030 CPU Package: 128-pin PGA Accessories Required: HP 10316G Maximum Clock Speed: 25 MHz input Signal Line Loading: 100 KΩ plus 18 pF on all lines except DSACK0 and DSACK1. Microprocessor Cycles Identified: User data read/write User program read Supervisor program read Bus grant CPU space accesses including: Breakpoint acknowledge Access level control Coprocessor communication Interrupt acknowledge Additional Capabilities: The logic analyzer captures all bus cycles, including prefetches.
68HC11 CPU Package: 48-pin dual-in-line Accessories Required: HP 10315G Maximum Clock Speed: 8.4 MHz input Signal Line Loading: 100 KΩ plus 12 pF on all lines Microprocessor Cycles Identified: Data read/write Opcode/operand fetches Index offsets Branch offsets Irrelevant cycles Additional Capabilities: The 68HC11 must be operating in the expanded multiplexed mode (addressing external memory and/or peripheral devices) for the logic analyzer to provide inverse assembly.
Loading Inverse Assembler Files You load the inverse assembler file by loading the appropriate configuration file. Loading the configuration file automatically loads the inverse assembler file. Selecting the Correct File Most inverse assembler disks contain more than one file. Each disk usually contains an inverse assembler file for use with the HP 10269C and preprocessor as well as a file for general purpose probing.
Connecting the Logic Analyzer Probes The specific preprocessor and inverse assembler you are using determines how you connect the logic analyzer probes. Since the inverse assembler files configure the State/Timing Configuration, State Format Specification, and State Trace Specification menus, you must connect the logic analyzer probe cables accordingly so that the acquired data is properly grouped for inverse assembly. Refer to the specific inverse assembler operating note for the proper connections.
Some of the preprocessors and/or the microprocessors under test do not provide enough status information to disassemble the data correctly. In this case, you will need to specify additional information (i.e. tell the logic analyzer what state contains the first word of an opcode fetch). When this is necessary an additional field (Invasm) will appear in the top center of the state listing menu (see figure 14-2). This field allows you to point to the first state of an Op Code fetch.
A Installing New Logic Analyzer Boards into the Mainframe Introduction This appendix explains, how to initially inspect the HP 16510B State/Timing Module, how to prepare it for use, storage and shipment. Also included are procedures for module installation. Initial Inspection Inspect the shipping container for damage.
Probe Cable Installation The HP 16510B State/Timing Module comes with probe cables installed by the factory. If a cable is to be switched or replaced, refer to "Probe Cable Replacement" in Section VI of the HP 16510B Service Manual. Installation Caution Do not install, remove or replace the module in the instrument unless the instrument power is turned off. The HP 16510B State/Timing Module will take up one slot in the card cage.
Procedure a. Turn the front and rear panel power switches off, unplug power cord and disconnect any input BNCs. b. Starting from the top, loosen thumb screws on filler panel(s) and card(s). c. Starting from the top, begin pulling card(s) and filler panel(s) out half way. See figure A-1. Figure A-1.
d. Lay the cable(s) flat and pointing out to the rear of the card. See figure A-2. e. Slide the analyzer card approximately half way into the card cage. f. If you have more analyzer cards to install repeat step d and e. Figure A-2.
g. Firmly seat bottom card into backplane connector. Keep applying pressure to the center of card endplate while tightening thumb screws finger tight. h. Repeat for all cards and filler panels in a bottom to top order. See figure A-3. Figure A-3. Endplate Overlap (Installing) i. Any filler panels that are not used should be kept for future use. Filler panels must be installed in all unused card slots for correct air circulation.
Operating Environment The operating environment is listed in "General Characteristics" in Appendix C of this manual. Note should be made of the non-condensing humidity limitation. Condensation within the instrument can cause poor operation or malfunction. Protection should be provided against internal condensation. The HP 16510B State/Timing Card will operate at all specifications within the temperature and humidity range given in Appendix C.
Packaging Tagging for Service HP 16510B Front-Panel Reference The following general instructions should be used for repacking the module with commercially available materials. • Wrap module in anti-static plastic. • Use a strong shipping container. A double-wall carton made of 350 lb. test material is adequate. • Use a layer of shock-absorbing material 70 to 100 mm (3 to 4 inch) thick around all sides of the module to provide firm cushioning and prevent movement inside the container.
B Error Messages This appendix lists the error messages that require corrective action to restore proper operation of the logic analyzer. There are several messages that you will see that are merely advisories and are not listed here. For example, "Load operation complete" is one of these advisories. The messages are listed in alphabetical order and in bold type. Autoscale aborted.
No labels specified. Indicates there are no labels to which to assign symbols. (x) Occurrences Remaining in Sequence (y). Indicates the logic analyzer is waiting for (x) number of occurrences in sequence level (y) of the state trace specification before it can go on to the next sequence level. (x) Secs Remaining in Trace. Indicates the amount of time remaining until acquisition is complete in Glitch mode. Search failed - O pattern not found. Indicates the O pattern does not exist in the acquired data.
exceeds 41.493 ms. It may be possible to add a "dummy" state to the machine’s trigger specification that is closer in time to the arm signal. (x) Transitions Remaining to Post Store. Indicates the number of transitions required until memory is filled and acquisition is complete. Waiting for Arm. Indicates the arming condition has not occurred. Waiting for Prestore. Indicates the prestore condition has not occurred (timing analyzer only). Waiting for Trigger. Indicates the trigger condition has not occurred.
C Specifications and Characteristics Introduction This appendix lists the specifications, operating characteristics, and supplemental characteristics of the HP 16510B Logic Analyzer Module. Specifications Probes Minimum Swing: 600 mV peak-to-peak. Threshold Accuracy: State Mode Voltage Range Accuracy −2.0V to +2.0V −9.9V to −2.1V +2.1V to +9.9V 150 mV 300 mV 300 mV Clock Repetition Rate: Single phase is 35 MHz maximum. With time or state counting, minimum time between states is 60 ns.
Timing Mode Minimum Detectable Glitch: 5 ns wide at the threshold. Operating Characteristics Probes Input RC: 100 KΩ ±2% shunted by approximately 8 pF at the probe tip. TTL Threshold Preset: +1.6 volts. ECL Threshold Preset: −1.3 volts. Threshold Range: −9.9 to +9.9 volts in 0.1V increments. Threshold Setting: Threshold levels may be defined for pods 1, 2, and 3 on an individual basis and one threshold may be defined for pods 4 and 5.
Measurement Configurations Analyzer Configurations: Analyzer 1 Analyzer 2 Timing Off State Off Timing State State Off Off Timing Off State State Timing State Off Channel Assignment: Each group of 16 channels (a pod) can be assigned to Analyzer 1, Analyzer 2, or remain unassigned. The HP 16510B contains 5 pods. State Analysis Memory Trace Specification Data Acquisition: 1024 samples/channel. Clocks: Five clocks are available and can be used by either one or two state analyzers at any time.
Range Recognizers: Recognizes data which is numerically between or on two specified patterns (ANDed combination of 0s and/or 1s). One range term is available and is assigned to the first state analyzer turned on. The maximum size is 32 bits. Qualifier: A user-specified term that can be anystate, nostate, a single pattern recognizer, range recognizer, or logical combination of pattern and range recognizers.
Symbols Pattern Symbols: User can define a mnemonic for the specific bit pattern of a label. When data display is SYMBOL, mnemonic is displayed where the bit pattern occurs. Bit pattern can include 0s, 1s, and don’t cares. Range Symbols: User can define a mnemonic covering a range of values. Bit pattern for lower and upper limits must be defined as a pattern of 0s and 1s. When data display is SYMBOL, values within the specified range are displayed as mnemonic ± offset from base of range.
Waveform Display Sec/div: 10 ns to 100 s; 0.01% resolution. Delay: −2500 s to 2500 s; presence of data dependent on the number of transitions in data between trigger and trigger plus delay (transitional timing). Accumulate: Waveform display is not erased between successive acquisitions. Overlay Mode: Multiple channels can be displayed on one waveform display line. Primary use is to view summary of bus activity.
Measurement and Display Functions Autoscale (Timing Analyzer Only) Acquisition Specifications Autoscale searches for and displays channels with activity on the pods assigned to the timing analyzer. Arming: Each analyzer can be armed by the run key, the other analyzer, or the Intermodule Bus.
Marker Functions Time Interval: The X and 0 markers measure the time interval between one point on a timing waveform and trigger, two points on the same timing waveform, two points on different waveforms, or two states (time tagging on). Delta States: (State Analyzer Only) The X and 0 markers measure the number of tagged states between one state and trigger, or between two states.
Auxiliary Power Power Through Cables: 2/3 amp @ 5V maximum per cable. Current Draw Per Card: 2 amp @ 5V maximum per HP 16510B Operating Environments Temperature: Instrument, 0 to 55° C (+32 to 131° F). Probe lead sets and cables, 0 to 65° C (+32 to 149° F). Humidity: Instrument, up to 95% relative humidity at +40° C (+122° F). Altitude: To 4600 m (15,000 ft). Vibration: Operating: Random vibration 5-500 Hz, 10 minutes per axis, ≈0.3 g (rms).
Index A absolute symbol offset 5-36 Accessing the Compare Menu 9-2 Accessing the State Chart Menu 11-1 Accessing the State Waveform Menu 10-1 Accumulate Mode C-6, 6-6 Acquisition Fields (State Trace) 5-55 acquisition memory 5-30 Acquisition Specifications C-7 Acquistion Mode 5-30 Activity Indicators 5-9, 7-4, 8-5 analyzer configuration capabilities 1-2 type 5-3 analyzers how to switch between 3-3 Armed By 5-56 Arming C-7 ASCII 5-16, 5-33 Autoscale C-7, 5-4 auxiliary power C-9 Axes (State Chart) Scaling the
pulse width C-1 qualifier C-3 D repetition rate C-1 slave 5-25 Specifying the J 8-10 data Clock Period 5-27 Acquiring the (State) 8-16 clocks Acquiring the (Timing) 7-8 state C-3 Acquiring the (Timing/State) 12-5 Compare Image display C-8 Bit Editing of the 9-4 how to roll 3-9 Creating a 9-3 Time Correlating the 12-11 Masking Channels in the 9-5 data entry C-8 Saving the 9-8 alpha 3-7 Compare Listing Display 9-2 numeric 3-6 Compare Menu 9-2 Delay C-6, 6-9 Compare Range 9-6 from Trigger (State) 10-6 configur
F Format Specification 5-8 State 5-8 Timing 5-8 Format Specification menu 5-7 Full Qualification Specification 5-45 G general purpose probing 2-3 Glitch Acquisition Mode C-5, 5-31 minimum detectable glitch C-2 Glitch Triggering 5-41 grabbers 2-6 green dotted line 7-10 grounds 2-6 pod 2-6 probe 2-7 H hold time C-1 logic analyzer module A-2 module A-2 Installing New Logic Analyzer Boards A-1 interface user 3-1 interfaces HP-IB 1-1 RS-232C 1-1 user 1-1 inverse assembled data how to display 14-2, 14-19 inver
Pattern 6-13 States 6-15 Statistics 6-15 Time 6-14 markers (Timing) Off 6-3 Pattern 6-5 Statistics 6-6 Time 6-3 master clock 5-25 / 5-26 maximum input voltage 2-8 measurements microprocessor 14-1 State Analyzer 8-1 Timing Analyzer 7-1 Timing/State 12-1 memory acquisition 5-30 data acquisition C-3 menu fields Armed By 5-56 / 5-57 Armed By (Timing Trace) 5-29 At_____marker 6-7 Base 5-66 Base (Timing Trace) 5-33 Clock 5-21 Count 5-61 Delay 6-9 Delete Level (State Trace) 5-48 Find Pattern 3-13 Find Pattern (Tim
System Level 5-1 Timing Format Specification 5-8 Timing Trace Specification 5-27 Timing Waveforms 6-1, 7-10 Trace Specification 5-7 microprocessor measurements 14-1 microprocessor supported preprocessors 14-2 Mixed Mode Display State/State 6-17 Timing/State 6-16 mouse 3-1 Using the 3-1 N name analyzer 3-7 / 3-8, 5-2 label 5-10 symbol 5-17 normal clock 5-24 numeric entry How to enter 3-6 O Occurrence Counter C-4, 5-50 off-screen pods to view 5-9 operating characteristics C-2 State Analysis C-3 Timing Analy
minimum input overdrive C-2 minimum swing C-1 pod assembly 2-4 threshold accuracy C-1 threshold range C-2 threshold setting C-2 TTL threshold preset C-2 probing general purpose 2-3 HP 16510B System 2-4 options 2-1 termination adapter 2-3 Q qualifier C-4, 5-44 branching 5-49 storage 5-49 Qualifier Field 5-65, 5-67 R range recognizers C-4 State Trace 5-67 red dotted line 7-10 Repetitive State Trace Mode 5-55 Timing Trace Mode 5-28 repetitive comparisons 9-7 Replacing Waveforms (State) 10-5 resolution timing
Storage Qualifier 5-49 Symbol Name 5-17 Symbol Offset 5-36 Symbol Table 5-14 Leaving the 5-20 Symbol Width 5-17 symbols C-5, 5-14 base 5-15 label 5-15 pattern C-5, 5-18 range C-5, 5-18 / 5-19 System Configuration Menu returning to 3-3 T tagging C-4, 5-61, 5-63 termination adapter 2-3 threshold pod 2-8, 5-12 Time Correlating Data 12-11 time counting 5-61 time interval accuracy C-6 time tagging C-4 Time-Correlated Displays 6-20 timing analyzer Making the Measurement 7-12 overlapping waveforms 12-15 Problem S
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