Owner manual

216 HP VMA SAN Gateway User’s Guide AM456-9026A
Unaligned Bounce Buffers for Reads and Writes
An unaligned bounce buffer for reads and writes occurs when the target address on the array for an
I/O is 4K aligned, but the host or gateway buffer of the same size requires splitting the Direct
Memory Access (DMA) into two sub-4K requests. In such a case, a temporary kernel bounce buffer
that is 4K aligned is used.
For writes, the data is byte-copied (bounced) to the temporary buffer, then sent to the array with the
host and target address perfectly aligned. For reads, the DMA from the array occurs in the
temporary buffer. Then it is byte-copied (bounced) to the application I/O request buffer.
Bouncing unaligned buffers results in a significant performance increase over read-modify-writes
that otherwise would have occurred in the write direction. In the read direction, bouncing unaligned
buffers avoids reading 8KB of data of which only 4K is used.
Note: The counters for unaligned bounce buffers are for the entire I/O, not the individual 4K pieces
within.
veeprom
The veeprom utility displays the HP VMA Array hardware information such as the main board
serial number, MAC address of the management interface, and so on.
Unaligned host buf
writes
The total I/O write requests to a HP VMA
Array, but only incremented when an
unaligned host address required special buffer
byte copying to service the DMA request. For
more information, see Unaligned Bounce
Buffers for Reads and Writes on page 216.
Requested DMA reads
Incremented for each read DMA descriptor
added to the descriptor ring.
A single I/O may result in multiple DMA
descriptors to complete a single I/O request.
Requested DMA writes
Incremented for each write DMA descriptor
added to the descriptor ring. Note that a single
I/O may result in multiple DMA descriptors to
complete a single I/O request.
Flash partial page
reads
Incremented when a DMA descriptor for read
is less than a flash page (4kB) in size. On a
DRAM-based system, this will always be 0.
Flash partial page
writes
Incremented when a DMA descriptor for write
is less than a flash page (4kB) in size which
leads to a hardware Read-Modify-Write
operation.