Trusted Execution Technology and Tboot Implementation

7
Appendix A
Sample Tboot serial output captured on 2010 Calpella platform(The actual output may
vary depending on the system configuration):
Intel(r) TXT Configuration Registers:
STS: 0x000188c1
senter_done: TRUE
sexit_done: FALSE
mem_unlock: FALSE
mem_config_lock: TRUE
private_open: TRUE
mem_config_ok: TRUE
ESTS: 0x00
txt_reset: FALSE
txt_wake_error: FALSE
E2STS: 0x0000000000000006
slp_entry_error: FALSE
secrets: TRUE
block_mem: TRUE
reset: FALSE
ERRORCODE: 0x00000000
DIDVID: 0x0000000fa0008086
vendor_id: 0x8086
device_id: 0xa000
revision_id: 0xf
SINIT.BASE: 0x77700000
SINIT.SIZE: 131072B (0x20000)
HEAP.BASE: 0x77720000
HEAP.SIZE: 917504B (0xe0000)
DPR: 0x0000000077800041
lock: TRUE
top: 0x77800000
size: 4MB (4194304B)
***********************************************************
TXT measured launch: TRUE
secrets flag set: TRUE
***********************************************************
ERROR: cannot map heap
TBOOT log:
max_size=7fe4
curr_pos=4ecb
buf:
T: ******************* TBOOT *******************
TBOOT: unavailable
TBOOT: *********************************************