Trusted Execution Technology and TBoot Implementation - White Paper

TBOOT: lcp_policy_hash:

08 b3 27 51 a4 52 21 c5 db 45 15 a9 ae 2e ff f9 f8 df e5 8f

TBOOT: lcp_policy_control: 0x00000000

TBOOT: rlp_wakeup_addr: 0x77701d10

TBOOT: num_mdrs: 7

TBOOT: mdrs_off: 0x98

TBOOT: num_vtd_dmars: 184

TBOOT: vtd_dmars_off: 0x140

TBOOT: sinit_mdrs:

TBOOT: 0000000000000000 - 00000000000a0000 (GOOD)

TBOOT: 0000000000100000 - 0000000000f00000 (GOOD)

TBOOT: 0000000001000000 - 0000000077700000 (GOOD)

TBOOT: 0000000000000000 - 0000000000000000 (GOOD)

TBOOT: 0000000077800000 - 0000000078000000 (SMRAM NON-OVERLAY)

TBOOT: 00000000e0000000 - 00000000f0000000 (PCIE EXTENDED CONFIG)

TBOOT: RSDP (v002 HPQOEM) @ 0x000f2b20

TBOOT: Seek in XSDT...

TBOOT: entry[0] sig = FACP @ 0x773fc000

TBOOT: entry[1] sig = HPET @ 0x773fb000

TBOOT: entry[2] sig = APIC @ 0x773fa000

TBOOT: acpi_table_ioapic @ 773fa06c, .address = fec00000

TBOOT: RSDP (v002 HPQOEM) @ 0x000f2b20

TBOOT: Seek in XSDT...

TBOOT: entry[0] sig = FACP @ 0x773fc000

TBOOT: entry[1] sig = HPET @ 0x773fb000

TBOOT: entry[2] sig = APIC @ 0x773fa000

TBOOT: entry[3] sig = MCFG @ 0x773f9000

TBOOT: acpi_table_mcfg @ 773f9000, .base_address = e0000000

TBOOT: mtrr_def_type: e = 1, fe = 1, type = 0

TBOOT: mtrrs:

TBOOT: base mask type v

TBOOT: 0ffc00 fffc00 05 1

TBOOT: 000000 f80000 06 1

TBOOT: 078000 ff8000 00 1

TBOOT: 000000 000000 00 0

TBOOT: min_lo_ram: 0x0, max_lo_ram: 0x77400000

TBOOT: min_hi_ram: 0x0, max_hi_ram: 0x0

TBOOT: MSR for SMM monitor control on ILP 0 is 0x0.