Datasheet

Rev. 1.1 / May. 2013 10
Registering Clock Driver Specifications
Capacitance Values
Input & Output Timing Requirements
Symbol Parameter Conditions Min Typ Max Unit
C
I
Input capacitance, Data inputs 1.5 - 2.5 pF
Input capacitance, CK, CK, FBIN, FBIN
(up to DDR3-1600)
1.5 - 2.5 pF
C
IR
Input capacitance, RESET, MIRROR,
QCSEN
V
I
= V
DD
or GND; V
DD
= 1.5v
--3pF
Symbol Parameter Conditions
DDR3L-800
1066/1333
DDR3L-1600
Unit
Min Max Min Max
f
clock
Input clock fre-
quency
Application fre-
quency
300 670 300 810 Mhz
f
TEST
Input clock fre-
quency
Test frequency 70 300 70 300 Mhz
t
SU
Setup time
Input valid before
CK/CK
100 - 50 - ps
t
H
Hold time
Input to remain
valid after CK/CK
175 - 125 - ps
t
PDM
Propagation
delay, single-bit
switching
CK/CK
to output 0.65 1.0 0.65 1.0 ns
t
DIS
Output disable
time (1/2-Clock
prelaunch)
Yn/Yn
to output
float
0.5 + tQSK1(min) - 0.5 + tQSK1(min) -
ps
t
EN
Output enable
time (1/2-Clock
prelaunch)
Output driving to
Yn/Yn
0.5 -
tQSK1(max)
- 0.5 - tQSK1(max) -
ps