APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 240pin DDR3 SDRAM Unbeffered DIMM DDR3 SDRAM Unbuffered DIMMs Based on 2Gb B-Die HMT312U6BFR6C HMT325U6BFR8C HMT325U7BFR8C HMT351U6BFR8C HMT351U7BFR8C * Hynix Semiconductor reserves the right to change products or specifications without notice. Rev. 1.0 / Oct. 2010 1 B48614/178.104.2.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Revision History Revision No. History Draft Date 0.1 Initial Release Dec. 2009 0.2 Added IDD Specification Feb. 2010 0.3 Editorial Change Apr. 2010 1.0 DIMM line-up(1Rx16) added Oct. 2010 Rev. 1.0 / Oct. 2010 Remark 2 B48614/178.104.2.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Description Hynix Unbuffered DDR3 SDRAM DIMMs (Unbuffered Double Data Rate Synchronous DRAM Dual In-Line Memory Modules) are low power, high-speed operation memory modules that use Hynix DDR3 SDRAM devices. These Unbuffered SDRAM DIMMs are intended for use as main memory when installed in systems such as PCs and workstations. Feature • VDD=1.5V +/- 0.075V • VDDQ=1.5V +/- 0.075V • VDDSPD=3.0V to 3.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Key Parameters MT/s Grade tCK (ns) CAS Latency (tCK) tRCD (ns) tRP (ns) tRAS (ns) tRC (ns) CL-tRCD-tRP DDR3-1066 -G7 1.875 7 13.125 13.125 37.5 50.625 7-7-7 DDR3-1333 -H9 1.5 9 13.5 13.5 36 49.5 9-9-9 DDR3-1600 -PB 1.25 11 13.75 13.75 35 48.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Pin Descriptions Pin Name Description Pin Name Description I2C serial bus clock for EEPROM A0–A15 SDRAM address bus SCL BA0–BA2 SDRAM bank select SDA I2C serial bus data line for EEPROM SA0–SA2 I2C slave address select for EEPROM RAS SDRAM row address strobe CAS SDRAM column address strobe WE SDRAM write enable VDDQ* SDRAM I/O Driver power supply DIMM Rank Select Lines VREFDQ SDRAM I/O reference supply CKE0–CK
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Input/Output Functional Descriptions Symbol Type Polarity Function CK0–CK1 CK0–CK1 SSTL Differential crossing CK and CK are differential clock inputs. All the DDR3 SDRAM addr/cntl inputs are sampled on the crossing of positive edge of CK and negative edge of CK. Output (read) data is reference to the crossing of CK and CK (Both directions of crossing).
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Symbol Type Polarity DQS0–DQS8 DQS0–DQS8 SSTL Differential crossing Function Data strobe for input and output data. SA0–SA2 — These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range. SDA — This bidirectional pin is used to transfer data into or out of the SPD EEPROM.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Front Side(left 1–60) Back Side(right 121–180) Front Side(left 61–120) Back Side(right 181–240) Pin x64 # Non-ECC x72 ECC Pin x64 # Non-ECC x72 ECC Pin # x64 Non-ECC x72 ECC Pin # x64 Non-ECC x72 ECC 17 VSS VSS 137 DQ14 DQ14 77 ODT1 ODT1 197 VDD VDD 18 DQ10 DQ10 138 DQ15 DQ15 78 VDD VDD 198 NC NC 19 DQ11 DQ11 139 VSS VSS 79 NC NC 199 VSS VSS 20 VSS VSS 140 DQ20 DQ20 80 VSS VSS
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Front Side(left 1–60) Pin x64 # Non-ECC 48 x72 ECC NC NC Back Side(right 121–180) Front Side(left 61–120) Back Side(right 181–240) Pin x64 # Non-ECC x72 ECC Pin # x64 Non-ECC x72 ECC Pin # x64 Non-ECC x72 ECC 168 Reset 108 DQ56 DQ56 228 DQ61 DQ61 109 DQ57 DQ57 229 VSS VSS Reset KEY KEY 49 NC NC 169 CKE1/NC CKE1/NC 110 VSS VSS 230 DM7 DM7 50 CKE0 CKE0 170 VDD VDD 111 DQS7 DQS7 231 N
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 On DIMM Thermal Sensor The DDR3 SDRAM DIMM temperature is monitored by integrated thermal sensor. The integrated thermal sensor comply with JEDEC “TSE2002av, Serial Presence Detect with Temperature Sensor”. Connection of Thermal Sensor EVENT SCL SDA SA0 SPD with SA1 Integrated SA2 TS EVENT SCL SA0 SDA SA1 SA2 Temperature-to-Digital Conversion Performance Parameter Temperature Sensor Accuracy (Grade B) Resolution Rev. 1.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Functional Block Diagram 1GB, 128Mx64 Module(1Rank of x16) S0 DQS0 DQS0 DM0 DQS1 DQS1 DM1 DQS2 DQS2 DM2 DQS3 DQS3 DM3 CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ2
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 2GB, 256Mx64 Module(1Rank of x8) S0 DQS0 DQS0 DM0 DQS1 DQS1 DM1 DQS2 DQS2 DM2 DQS3 DQS3 DM3 DQS4 DQS4 DM4 DM CS DQS DQS 0 1 D0 2 3 4 5 6 ZQ 7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O I/O I/O I/O I/O I/O I/O I/O DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM CS DQS DQS I/O 0 I/O 1 D1 I/O 2 I/O 3 I/O 4 I/O 5 ZQ I/O 6 I/O 7 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 I/O I/O I/O I/O I/O I/O I/O I/O DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 2GB, 256Mx72 Module(1Rank of x8) S0 DQS0 DQS0 DM0 DQS1 DQS1 DM1 DQS2 DQS2 DM2 DQS3 DQS3 DM3 DQS8 DQS8 DM8 BA0–BA2 A0–A15 RAS CAS CKE0 WE ODT0 CK0 CK0 RESET DQS4 DQS4 DM4 DQS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 0 I/O 1 I/O 2 I/O 3
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 4GB, 512Mx64 Module(2Rank of x8) S1 S0 DQS0 DQS0 DM0 DQS4 DQS4 DM4 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS DQS DQS D0 ZQ DQS1 DQS1 DM1 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 D1 ZQ DQS2 DQS2 DM2 DQS3 DQS3 DM3 DM
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 4GB, 512Mx72 Module(2Rank of x8) DQS1 DQS1 DM1 S1 S0 DQS0 DQS0 DM0 DQS4 DQS4 DM4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM CS DQS DQS I/O 0 I/O 1 D0 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Absolute Maximum Ratings Absolute Maximum DC Ratings Absolute Maximum DC Ratings Symbol VDD VDDQ Parameter Rating Units Notes Voltage on VDD pin relative to Vss - 0.4 V ~ 1.975 V V 1, Voltage on VDDQ pin relative to Vss - 0.4 V ~ 1.975 V V 1, - 0.4 V ~ 1.975 V V 1 C 1, 2 VIN, VOUT Voltage on any pin relative to Vss TSTG -55 to +100 Storage Temperature o Notes: 1.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 AC & DC Operating Conditions Recommended DC Operating Conditions Recommended DC Operating Conditions Symbol VDD VDDQ Parameter Rating Units Notes 1.575 V 1,2 1.575 V 1,2 Min. Typ. Max. Supply Voltage 1.425 1.500 Supply Voltage for Output 1.425 1.500 Notes: 1. Under all conditions, VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 AC and DC Input Levels for Single-Ended Signals DDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066 as specified in the table below. DDR3 SDRAM will also support corresponding tDS values (Table 41 and Table 47 in “DDR3 Device Operation”) as well as derating tables in Table 44 of “DDR3 Device Operation” depending on Vih/Vil AC levels.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Vref Tolerances The dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in figure below. It shows a valid reference voltage VRef (t) as a function of time. (VRef stands for VRefCA and VRefDQ likewise). VRef (DC) is the linear average of VRef (t) over a very long period of time (e.g. 1 sec).
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 AC and DC Logic Input Levels for Differential Signals Differential signal definition tDVAC Differential Input Voltage(i.e.DQS - DQS#, CK - CK#) VIL.DIFF.AC.MIN VIL.DIFF.MIN 0 half cycle VIL.DIFF.MAX VIL.DIFF.AC.MAX tDVAC time Definition of differential ac-swing and “time above ac-level” tDVAC Rev. 1.0 / Oct. 2010 20 B48614/178.104.2.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS) Differential AC and DC Input Levels DDR3-800, 1066, 1333, & 1600 Symbol Parameter VIHdiff VILdiff VIHdiff (ac) VILdiff (ac) Differential input high Differential input logic low Differential input high ac Differential input low ac Unit Notes Min Max + 0.200 Note 3 2 x (VIH (ac) - Vref) Note 3 Note 3 - 0.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Single-ended requirements for differential signals Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, of DQSU) has also to comply with certain requirements for single-ended signals. CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH (ac) / VIL (ac)) for ADD/CMD signals) in every half-cycle.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU DDR3-800, 1066, 1333, & 1600 Symbol VSEH VSEL Parameter Unit Notes Single-ended high level for strobes Single-ended high level for Ck, CK Single-ended low level for strobes Single-ended low level for CK, CK Min Max (VDD / 2) + 0.175 (VDD /2) + 0.175 Note 3 Note 3 Note 3 Note 3 (VDD / 2) = 0.175 (VDD / 2) = 0.175 V V V V 1,2 1,2 1,2 1,2 Notes: 1.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Cross point voltage for differential input signals (CK, DQS) DDR3-800, 1066, 1333, & 1600 Symbol Parameter Unit Notes Min Max VIX Differential Input Cross Point Voltage relative to VDD/2 for CK, CK -150 -175 150 175 mV mV VIX Differential Input Cross Point Voltage relative to VDD/2 for DQS, DQS -150 150 mV 1 Notes: 1.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Slew Rate Definitions for Differential Input Signals Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in table and Figure below.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 AC & DC Output Measurement Levels Single Ended AC and DC Output Levels Table below shows the output levels used for measurements of single ended signals. Single-ended AC and DC Output Levels Symbol Parameter VOH(DC) DC output high measurement level (for IV curve linearity) VOM(DC) DC output mid measurement level (for IV curve linearity) VOL(DC) VOH(AC) DDR3-800, 1066, 1333 and 1600 0.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Single Ended Output Slew Rate When the Reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals are shown in table and Figure below.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Differential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff (AC) and VOHdiff (AC) for differential signals as shown in table and Figure below.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Reference Load for AC Timing and Output Slew Rate Figure Below represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements. It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Overshoot and Undershoot Specifications Address and Control Overshoot and Undershoot Specifications AC Overshoot/Undershoot Specification for Address and Control Pins DDR3- DDR3- DDR3- DDR3- Parameter Maximum peak amplitude allowed for overshoot area. (See Figure below) Maximum peak amplitude allowed for undershoot area.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask DDR3- DDR3- DDR3- DDR3- Parameter Maximum peak amplitude allowed for overshoot area. (See Figure below) Maximum peak amplitude allowed for undershoot area.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Refresh parameters by device density Refresh parameters by device density Parameter REF command ACT or REF command time Average periodic refresh interval Rev. 1.0 / Oct. 2010 RTT_Nom Setting 512Mb 1Gb 2Gb 4Gb 8Gb tRFC 90 110 160 300 350 tREFI 0 °C ≤ TCASE ≤ 85 °C 85 °C < TCASE ≤ 95 °C Units Notes ns 7.8 7.8 7.8 7.8 7.8 us 3.9 3.9 3.9 3.9 3.9 us 32 B48614/178.104.2.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Standard Speed Bins DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin. DDR3-800 Speed Bins For specific Notes See “Speed Bin Table Notes” on page 37.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 DDR3-1066 Speed Bins For specific Notes See “Speed Bin Table Notes” on page 37. Speed Bin DDR3-1066F CL - nRCD - nRP Parameter Symbol Unit 7-7-7 min max Internal read command to first data tAA 13.125 20 ns ACT to internal read or write delay time tRCD 13.125 — ns PRE command period tRP 13.125 — ns ACT to ACT or REF command period tRC 50.625 — ns ACT to PRE command period tRAS 37.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 DDR3-1333 Speed Bins For specific Notes See “Speed Bin Table Notes” on page 37. Speed Bin DDR3-1333H CL - nRCD - nRP Parameter Symbol Unit 9-9-9 min max Internal read command to first data tAA 13.5 (13.125)8 20 ns ACT to internal read or write delay time tRCD 13.5 (13.125)8 — ns PRE command period tRP 13.5 (13.125)8 — ns ACT to ACT or REF command period tRC 49.5 (49.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 DDR3-1600 Speed Bins For specific Notes See “Speed Bin Table Notes” on page 37. Speed Bin DDR3-1600K CL - nRCD - nRP Parameter Symbol Unit 11-11-11 min max Internal read command to first data tAA 13.75 (13.125)8 20 ns ACT to internal read or write delay time tRCD 13.75 (13.125)8 — ns PRE command period tRP 13.75 (13.125)8 — ns ACT to ACT or REF command period tRC 48.75 (48.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Speed Bin Table Notes Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V); Notes: 1, The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK (AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting. 2. tCK(AVG).
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Environmental Parameters Symbol Parameter Rating Units Notes 3 TOPR Operating temperature (ambient) 0 to +55 oC HOPR Operating humidity (relative) 10 to 90 % TSTG Storage temperature HSTG Storage humidity (without condensation) PBAR Barometric Pressure (operating & storage) o C 1 5 to 95 % 1 105 to 69 K Pascal 1, 2 -50 to +100 Note: 1.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Pin Capacitance (VDD=1.5V, VDDQ=1.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 IDD and IDDQ Specification Parameters and Test Conditions IDD and IDDQ Measurement Conditions In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure below (Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements) shows the setup and test load for IDD and IDDQ measurements.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 IDDQ (optional) IDD VDD VDDQ RESET CK/CK DDR3 SDRAM CKE CS RAS, CAS, WE DQS, DQS DQ, DM, TDQS, TDQS A, BA ODT ZQ VSS RTT = 25 Ohm VDDQ/2 VSSQ Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements [Note: DIMM level Output test load condition may be different from above Application specific memory channel environment IDDQ Test Load Channel IO Power Simulation IDDQ Simulation IDDQ Simulation Correcti
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns Symbol tCK DDR3-1066 DDR3-1333 DDR3-1600 7-7-7 9-9-9 11-11-11 1.875 1.5 1.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Symbol Description Precharge Standby Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank IDD2N Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 5.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Symbol Description Operating Burst Read Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Command, Address, IDD4R Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst with different data between one burst and the next one according to Table 7; DM: stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Symbol Description Operating Bank Interleave Read Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8a),f); AL: CL-1; CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according to Table IDD7 10; Data IO: read data burst with different data between one burst and the next one according to Table 10; DM: stable at 0; Bank Activity: two times interleaved
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 ACT 0 0 1 1 0 0 00 0 0 0 0 - 1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 - D, D 1 1 1 1 0 0 00 0 0 0 0 - 0 0 0 - Cycle Number Datab) Sub-Loop CKE CK, CK Table 3 - IDD0 Measurement-Loop Patterna) 0 3,4 ... nRAS Static High toggling ... repeat pattern 1...
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 ACT 0 0 1 1 0 0 00 0 0 0 0 - 1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 - D, D 1 1 1 1 0 0 00 0 0 0 0 - 0 0 00000000 0 0 - Cycle Number Datab) Sub-Loop CKE CK, CK Table 4 - IDD1 Measurement-Loop Patterna) 0 3,4 ... nRCD ... nRAS Static High toggling ... repeat pattern 1...
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Static High CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 D 1 0 0 0 0 0 0 0 0 0 0 - 1 D 1 0 0 0 0 0 0 0 0 0 0 - 2 D 1 1 1 1 0 0 0 0 0 F 0 - 3 D 1 1 1 1 0 0 0 0 0 F 0 - Cycle Number Command 0 toggling Datab) Sub-Loop CKE CK, CK Table 5 - IDD2N and IDD3N Measurement-Loop Patterna) 1 4-7 repeat Sub-Loop 0, use BA[2:0] = 1 instead 2 8-11 r
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 RD 0 1 0 1 0 0 00 0 0 0 0 00000000 1 D 1 0 0 0 0 0 00 0 0 0 0 - 2,3 D,D 1 1 1 1 0 0 00 0 0 0 0 - 4 RD 0 1 0 1 0 0 00 0 0 F 0 00110011 5 D 1 0 0 0 0 0 00 0 0 F 0 - D,D 1 1 1 1 0 0 00 0 0 F 0 - Cycle Number Command Static High 0 toggling Datab) Sub-Loop CKE CK, CK Table 7
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 0 REF 0 0 0 1 0 0 0 0 0 0 0 - 1 1.2 D, D 1 0 0 0 0 0 00 0 0 0 0 - D, D 1 1 1 1 0 0 00 0 0 F 0 - Cycle Number Datab) Sub-Loop CKE CK, CK Table 9 - IDD5B Measurement-Loop Patterna) Static High toggling 3,4 2 5...8 repeat cycles 1...4, but BA[2:0] = 1 9...12 repeat cycles 1...4, but BA[2:0] = 2 13.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Table 10 - IDD7 Measurement-Loop Patterna) 2 3 4 Static High 5 6 7 8 9 10 4*nRRD nFAW nFAW+nRRD nFAW+2*nRRD nFAW+3*nRRD nFAW+4*nRRD 2*nFAW+0 2*nFAW+1 2&nFAW+2 11 2*nFAW+nRRD 2*nFAW+nRRD+1 2&nFAW+nRRD+2 12 13 2*nFAW+2*nRRD 2*nFAW+3*nRRD 14 2*nFAW+4*nRRD 15 16 17 18 3*nFAW 3*nFAW+nRRD 3*nFAW+2*nRRD 3*nFAW+3*nRRD 19 3*nFAW+4*nRRD 00110011 - 0 - 0 - 0 0 0 00110011 - 0 0 0 00000000 - 0 - 0 - A[10] 0 0 0 ODT
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 IDD Specifications (Tcase: 0 to 95oC) * Module IDD values in the datasheet are only a calculation based on the component IDD spec. The actual measurements may vary according to DQ loading cap.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 2GB, 256M x 72 U-DIMM: HMT325U7BFR8C Symbol IDD0 IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 DDR3 1066 405 495 225 288 108 135 DDR3 1333 450 540 270 315 108 135 DDR3 1600 495 585 270 360 108 135 Unit mA mA mA mA mA mA IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDD6ET IDD6TC IDD7 225 270 135 720 720 1350 108 135 135 990 270 315 135 855 855 1395 108 135 135 1215 270 360 135 945 990 1440 108 135 135 1305 mA mA mA mA mA mA mA mA mA mA DDR3 1
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 4GB, 512M x 72 U-DIMM: HMT351U7BFR8C Symbol IDD0 IDD1 IDD2N IDD2NT IDD2P0 IDD2P1 DDR3 1066 630 720 450 576 216 270 DDR3 1333 720 810 540 630 216 270 DDR3 1600 855 945 540 720 216 270 Unit mA mA mA mA mA mA IDD2Q IDD3N IDD3P IDD4R IDD4W IDD5B IDD6 IDDET IDD6TC IDD7 450 540 270 945 945 1575 216 270 270 1215 540 630 270 1125 1125 1665 216 270 270 1485 540 720 270 1305 1350 1800 216 270 270 1665 mA mA mA mA mA mA mA mA mA mA Re
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 Module Dimensions 128Mx64 - HMT312U6BFR6C Front 2.10 ± 0.15 Max R0.70 Min 1.45 30.00 SPD 4 x 3.00 ± 0.10 17.30 DETAIL-B DETAIL-A 2 x φ 2.50 ± 0.10 9.50 2 x 2.30 ± 0.10 47.00 5.175 71.00 128.95 133.35 Back Side Detail - A Detail - B 3.18 0.3 ± 0.15 2.50 ± 0.20 3.80 0.35 0.05 1.27 ± 0.10 FULL R 2.50 0.80 ± 0.05 1.00 0.3~1.0 1.50 ± 0.10 5.00 Note: 1. ± 0.13 tolerance on all dimensions unless otherwise stated.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 256Mx64 - HMT325U6BFR8C Front 2.10 ± 0.15 Min 1.45 Max R0.70 30.00 SPD 4 x 3.00 ± 0.10 17.30 DETAIL-B DETAIL-A 2 x φ 2.50 ± 0.10 9.50 2 x 2.30 ± 0.10 47.00 5.175 71.00 128.95 133.35 Back Side Detail - A Detail - B 3.18 0.3 ± 0.15 2.50 ± 0.20 3.80 0.35 0.05 1.27 ± 0.10 FULL R 2.50 0.80 ± 0.05 1.00 0.3~1.0 1.50 ±0.10 5.00 Note: 1. ± 0.13 tolerance on all dimensions unless otherwise stated.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 256Mx72 - HMT325U7BFR8C Front 2.10 ± 0.15 Min 1.45 SPD Max R0.70 30.00 4 x 3.00 ± 0.10 17.30 DETAIL-B DETAIL-A 2 x φ 2.50 ± 0.10 9.50 2 x 2.30 ± 0.10 47.00 5.175 71.00 128.95 133.35 Back Side Detail - A Detail - B 3.18 0.3 ± 0.15 2.50 ± 0.20 3.80 0.35 0.05 1.27 ± 0.10 FULL R 2.50 0.80 ± 0.05 1.00 0.3~1.0 1.50 ±0.10 5.00 Note: 1. ± 0.13 tolerance on all dimensions unless otherwise stated.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 512Mx64 - HMT351U6BFR8C Front 2.10 ± 0.15 Min 1.45 Max R0.70 30.00 SPD 4 x 3.00 ± 0.10 17.30 DETAIL-B DETAIL-A 2 x φ 2.50 ± 0.10 9.50 2 x 2.30 ± 0.10 47.00 5.175 71.00 128.95 133.35 Back Detail - A Detail - B 4.00 2.50 ± 0.20 3.80 0.35 0.05 1.27 ± 0.10 FULL R 2.50 0.80 ± 0.05 0.3 ± 0.15 Side 1.00 0.3~1.0 1.50 ±0.10 5.00 Note: 1. ± 0.13 tolerance on all dimensions unless otherwise stated.
APCPCWM_4828539:WP_0000005WP_000000 APCPCWM_4828539:WP_0000005WP_0000005 512Mx72 - HMT351U7BFR8C Front 2.10 ± 0.15 Min 1.45 Max R0.70 SPD 30.00 4 x 3.00 ± 0.10 17.30 DETAIL-B DETAIL-A 2 x φ 2.50 ± 0.10 9.50 2 x 2.30 ± 0.10 47.00 5.175 71.00 128.95 133.35 Back Detail - A Detail - B 4.00 2.50 ± 0.20 3.80 0.35 0.05 1.27 ± 0.10 FULL R 2.50 0.80 ± 0.05 0.3 ± 0.15 Side 1.00 0.3~1.0 1.50 ±0.10 5.00 Note: 1. ± 0.13 tolerance on all dimensions unless otherwise stated.
