Datasheet

ManualsBrandsHynix Manualscomputer componentsHMT351U7CFR8A-PBT0

Rev. 1.1 / Jul. 2013 1

240pin DDR3L SDRAM Unbuffered DIMM

* SK hynix Semiconductor reserves the right to change products or specifications without notice.

DDR3L SDRAM

Unbuffered DIMMs

Based on 2Gb C-Die

HMT325U7CFR8A

HMT351U7CFR8A

Summary of content (52 pages)

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240pin DDR3L SDRAM Unbuffered DIMM DDR3L SDRAM Unbuffered DIMMs Based on 2Gb C-Die HMT325U7CFR8A HMT351U7CFR8A * SK hynix Semiconductor reserves the right to change products or specifications without notice. Rev. 1.1 / Jul.
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Revision History Revision No. History Draft Date 0.1 Initial Release Aug. 2011 0.2 Added Speed Bin Table Notes Sep. 2011 0.3 JEDEC Spec Updated Mar. 2012 1.0 Module Dimension Updated Jul. 2012 1.1 Changed module maximum thickness to reflect the measured maximum Jul. 2013 Rev. 1.1 / Jul.
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Description SK hynix Unbuffered DDR3L SDRAM DIMMs (Unbuffered Double Data Rate Synchronous DRAM Dual InLine Memory Modules) are low power, high-speed operation memory modules that use DDR3L SDRAM devices. These Unbuffered SDRAM DIMMs are intended for use as main memory when installed in systems such as PCs and workstations.  Feature • Power Supply: VDD=1.35V (1.283V to 1.45V) • VDDQ=1.35V (1.283 to 1.45V) • VDDSPD=3.0V to 3.6V • Backward Compatible with 1.
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Key Parameters MT/s Grade tCK (ns) CAS Latency (tCK) tRCD (ns) tRP (ns) tRAS (ns) tRC (ns) CL-tRCD-tRP DDR3-1066 -G7 1.875 7 13.125 13.125 37.5 50.625 7-7-7 DDR3L-1333 -H9 1.5 9 13.5 13.5 (13.125)* (13.125)* 36 49.5 (49.125)* 9-9-9 DDR3L-1600 -PB 1.25 11 13.75 13.75 (13.125)* (13.125)* 35 48.75 (48.125)* 11-11-11 *SK hynix DRAM devices support optional downbinning to CL9 and CL7.
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Pin Descriptions Pin Name Description Pin Name Description I2C serial bus clock for EEPROM A0–A15 SDRAM address bus SCL BA0–BA2 SDRAM bank select SDA I2C serial bus data line for EEPROM SA0–SA2 I2C slave address select for EEPROM RAS SDRAM row address strobe CAS SDRAM column address strobe WE SDRAM write enable VDDQ* SDRAM I/O Driver power supply DIMM Rank Select Lines VREFDQ SDRAM I/O reference supply CKE0–CKE1 SDRAM clock enable lines VREFCA SDRAM command/address reference suppl
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Input/Output Functional Descriptions Symbol Type Polarity Function CK0–CK1 CK0–CK1 SSTL Differential crossing CK and CK are differential clock inputs. All the DDR3L SDRAM addr/cntl inputs are sampled on the crossing of positive edge of CK and negative edge of CK. Output (read) data is reference to the crossing of CK and CK (Both directions of crossing). CKE0–CKE1 SSTL Active High Activates the SDRAM CK signal when high and deactivates the CK signal when low.
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Symbol Type Polarity DQS0–DQS8 DQS0–DQS8 SSTL Differential crossing Function Data strobe for input and output data. SA0–SA2 — These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range. SDA — This bidirectional pin is used to transfer data into or out of the SPD EEPROM. An external resistor may be connected from the SDA bus line to VDDSPD to act as a pullup on the system board.
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Pin Assignments Front Side(left 1–60) Back Side(right 121–180) Front Side(left 61–120) Back Side(right 181–240) Pin # x72 ECC Pin # x72 ECC Pin # x72 ECC Pin # x72 ECC 1 VREFDQ 121 VSS 61 A2 181 A1 2 VSS 122 DQ4 62 VDD 182 VDD 3 DQ0 123 DQ5 63 CK1 183 VDD 4 DQ1 124 VSS 64 CK1 184 CK0 5 VSS 125 DM0 65 VDD 185 CK0 6 DQS0 126 NC 66 VDD 186 VDD 7 DQS0 127 VSS 67 VREFCA 187 EVENT 8 VSS 128 DQ6 68 NC 188 A0 9 DQ2 129 DQ7 69 VDD 189 V
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Front Side(left 1–60) Back Side(right 121–180) Front Side(left 61–120) Back Side(right 181–240) Pin # x72 ECC Pin # x72 ECC Pin # x72 ECC Pin # x72 ECC 31 DQ25 151 VSS 91 DQ41 211 VSS 32 VSS 152 DM3 92 VSS 212 DM5 33 DQS3 153 NC 93 DQS5 213 NC 34 DQS3 154 VSS 94 DQS5 214 VSS 35 VSS 155 DQ30 95 VSS 215 DQ46 36 DQ26 156 DQ31 96 DQ42 216 DQ47 37 DQ27 157 VSS 97 DQ43 217 VSS 38 VSS 158 CB4 98 VSS 218 DQ52 39 CB0 159 CB5 99 DQ48 219
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On DIMM Thermal Sensor The DDR3L SDRAM DIMM temperature is monitored by integrated thermal sensor. The integrated thermal sensor comply with JEDEC “TSE2002av, Serial Presence Detect with Temperature Sensor”. Connection of Thermal Sensor EVENT SCL SDA SA0 EVENT SPD with SA1 SCL Integrated SA2 SDA TS SA0 SA1 SA2 Temperature-to-Digital Conversion Performance Parameter Temperature Sensor Accuracy (Grade B) Resolution Rev. 1.1 / Jul.
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Functional Block Diagram 2GB, 256Mx72 Module(1Rank of x8) S0 DQS0 DQS0 DM0 DQS1 DQS1 DM1 DQS2 DQS2 DM2 DQS3 DQS3 DM3 DQS8 DQS8 DM8 DQS4 DQS4 DM4 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O
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4GB, 512Mx72 Module(2Rank of x8) DQS1 DQS1 DM1 S1 S0 DQS0 DQS0 DM0 DQS4 DQS4 DM4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM CS DQS DQS I/O 0 I/O 1 D0 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 ZQ DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM CS DQS DQS I/O 0 I/O 1 D2 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 Z
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Absolute Maximum Ratings Absolute Maximum DC Ratings Absolute Maximum DC Ratings Symbol VDD VDDQ Parameter Rating Units Notes Voltage on VDD pin relative to Vss - 0.4 V ~ 1.8 V V 1, 3 Voltage on VDDQ pin relative to Vss - 0.4 V ~ 1.8 V V 1, 3 V 1 VIN, VOUT Voltage on any pin relative to Vss TSTG - 0.4 V ~ 1.8 V -55 to +100 Storage Temperature o C 1, 2 Notes: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
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AC & DC Operating Conditions Recommended DC Operating Conditions Recommended DC Operating Conditions - DDR3L (1.35V) operation Symbol VDD VDDQ Parameter Rating Units Notes 1.45 V 1,2,3,4 1.45 V 1,2,3,4 Min. Typ. Max. Supply Voltage 1.283 1.35 Supply Voltage for Output 1.283 1.35 Notes: 1. Maximum DC value may not be greater than 1.425V. The DC value is the linear average of VDD/VDDQ (t) over a very long period of time (e.g., 1 sec). 2.
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Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk CK,CK# VDD, VDDQ (DDR3) tCKSRX Tmin = 10ns VDD, VDDQ (DDR3L) Tmin = 10ns Tmin = 200us T = 500us RESET# Tmin = 10ns CKE VALID tDLLK tIS COMMAND READ BA READ 1) tXPR tMRD tMRD tMRD tMOD MRS MRS MRS MRS MR2 MR3 MR1 MR0 tZQinit ZQCL 1) VALID tIS ODT READ VALID tIS Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW VALID RTT NOTE 1: From time point “Td” until “Tk” NOP or DES commands must be applied betwe
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AC & DC Input Measurement Levels AC and DC Logic Input Levels for Single-Ended Signals AC and DC Input Levels for Single-Ended Command and Address Signals Single Ended AC and DC Input Levels for Command and Address Symbol Parameter VIH.CA(DC90) VIL.CA(DC90) VIH.CA(AC160) VIL.CA(AC160) VIH.CA(AC135) VIL.CA(AC135) VIH.CA(AC125) VIL.
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AC and DC Input Levels for Single-Ended Signals DDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066s specified in table below. DDR3 SDRAM will also support corresponding tDS values (Table 43 and Table 50 in “DDR3L Device Operation”) as well as derating tables Table 46 in “DDR3L Device Operation” depending on Vih/Vil AC levels. Single Ended AC and DC Input Levels for DQ and DM Symbol Parameter VIH.DQ(DC90) VIL.DQ(DC90) VIH.DQ(AC160) VIL.DQ(AC160) VIH.DQ(AC135) VIL.DQ(AC135) VIH.
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Vref Tolerances The dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in figure below. It shows a valid reference voltage VRef (t) as a function of time. (VRef stands for VRefCA and VRefDQ likewise). VRef (DC) is the linear average of VRef (t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements in the table "Differential Input Slew Rate Definition" on page 24.
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AC and DC Logic Input Levels for Differential Signals Differential signal definition tDVAC Differential Input Voltage(i.e.DQS - DQS#, CK - CK#) VIL.DIFF.AC.MIN VIL.DIFF.MIN 0 half cycle VIL.DIFF.MAX VIL.DIFF.AC.MAX tDVAC time Definition of differential ac-swing and “time above ac-level” tDVAC Rev. 1.1 / Jul.
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Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS) Differential AC and DC Input Levels Symbol Parameter VIHdiff VILdiff Differential input high Differential input logic low Differential input high ac Differential input low ac VIHdiff (ac) VILdiff (ac) DDR3L-800, 1066, 1333, & 1600 Min Max + 0.180 Note 3 2 x (VIH (ac) - Vref) Note 3 Note 3 - 0.180 Note 3 2 x (VIL (ac) - Vref) Unit Notes V V V V 1 1 2 2 Notes: 1. Used to define a differential signal slew-rate. 2.
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Single-ended requirements for differential signals Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, of DQSU) also has to comply with certain requirements for single-ended signals. CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH (ac) / VIL (ac)) for ADD/CMD signals) in every half-cycle.
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Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU Symbol VSEH VSEL Parameter Single-ended high level for strobes Single-ended high level for Ck, CK Single-ended low level for strobes Single-ended low level for CK, CK DDR3L-800, 1066, 1333, & 1600 Min Max (VDD / 2) + 0.175 (VDD /2) + 0.175 Note 3 Note 3 Note 3 Note 3 (VDD / 2) - 0.175 (VDD / 2) - 0.175 Unit Notes V V V V 1,2 1,2 1,2 1,2 Notes: 1.
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Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in table below.
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Slew Rate Definitions for Single-Ended Input Signals See 7.5 “Address / Command Setup, Hold and Derating” in “DDR3L Device Operation” for single-ended slew rate definitions for address and command signals.  See 7.6 “Data Setup, Hold and Slew Rate Derating” in “DDR3L Device Operation” for single-ended slew rate definition for data signals.
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AC & DC Output Measurement Levels Single Ended AC and DC Output Levels Table below shows the output levels used for measurements of single ended signals.
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Single Ended Output Slew Rate When the Reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single ended signals are shown in table and Figure below.
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Differential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff (AC) and VOHdiff (AC) for differential signals as shown in table and figure below.
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Reference Load for AC Timing and Output Slew Rate Figure Below represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements. It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment.
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Overshoot and Undershoot Specifications Address and Control Overshoot and Undershoot Specifications AC Overshoot/Undershoot Specification for Address and Control Pins DDR3L DDR3L DDR3L DDR3L Parameter -800 Maximum peak amplitude allowed for overshoot area. (See Figure below) 0.4 Maximum peak amplitude allowed for undershoot area. (See Figure below) 0.4 Maximum overshoot area above VDD (See Figure below) 0.67 Maximum undershoot area below VSS (See Figure below) 0.
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Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask DDR3L DDR3L DDR3L DDR3L Parameter -800 Maximum peak amplitude allowed for overshoot area. (See Figure below) 0.4 Maximum peak amplitude allowed for undershoot area. (See Figure below) 0.4 Maximum overshoot area above VDD (See Figure below) 0.25 Maximum undershoot area below VSS (See Figure below) 0.
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Refresh parameters by device density Refresh parameters by device density Parameter REF command ACT or REF command time Average periodic refresh interval RTT_Nom Setting 512Mb 1Gb 2Gb 4Gb 8Gb tRFC 90 110 160 260 350 ns 7.8 7.8 7.8 7.8 7.8 us 3.9 3.9 3.9 3.9 3.9 us tREFI 0 C  TCASE  85 C 85 C  TCASE  95 C Units Notes 1 Notes: 1.
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Standard Speed Bins DDR3L SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin. DDR3L-800 Speed Bins For specific Notes See "Speed Bin Table Notes" on page 36. Speed Bin DDR3L-800E CL - nRCD - nRP 6-6-6 Unit Parameter Symbol min max Internal read command to first data tAA 15 20 ns ACT to internal read or write delay time tRCD 15 — ns PRE command period tRP 15 — ns ACT to ACT or REF command period tRC 52.
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DDR3L-1066 Speed Bins For specific Notes See "Speed Bin Table Notes" on page 36. Speed Bin DDR3L-1066F CL - nRCD - nRP Parameter Symbol Unit 7-7-7 min max Note Internal read command to first data tAA 13.125 20 ns ACT to internal read or write delay time tRCD 13.125 — ns PRE command period tRP 13.125 — ns ACT to ACT or REF command period tRC 50.625 — ns ACT to PRE command period tRAS 37.5 9 * tREFI ns CWL = 5 tCK(AVG) 2.5 3.
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DDR3L-1333 Speed Bins For specific Notes See "Speed Bin Table Notes" on page 36. Speed Bin DDR3L-1333H CL - nRCD - nRP Parameter Symbol Unit 9-9-9 min max Note Internal read command to first data tAA 13.5 (13.125)5,9 20 ns ACT to internal read or write delay time tRCD 13.5 (13.125)5,9 — ns PRE command period tRP 13.5 (13.125)5,9 — ns ACT to ACT or REF command period tRC 49.5 (49.125)5,9 — ns ACT to PRE command period tRAS 36 9 * tREFI ns CWL = 5 tCK(AVG) 2.5 3.
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DDR3L-1600 Speed Bins For specific Notes See "Speed Bin Table Notes" on page 36. Speed Bin DDR3L-1600K CL - nRCD - nRP Parameter Symbol Unit 11-11-11 min max 20 ns Note Internal read command to first data tAA 13.75 (13.125)5,9 ACT to internal read or write delay time tRCD 13.75 (13.125)5,9 — ns PRE command period tRP 13.75 (13.125)5,9 — ns ACT to ACT or REF command period tRC 48.75 (48.125)5,9 — ns ACT to PRE command period tRAS 35 9 * tREFI ns CWL = 5 tCK(AVG) 2.5 3.
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Speed Bin Table Notes Absolute Specification (TOPER; VDDQ = VDD = 1.35V +0.100/- 0.067 V); 1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting. 2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed.
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Environmental Parameters Symbol Parameter Rating Units TOPR Operating temperature (ambient) 0 to +55 o HOPR Operating humidity (relative) 10 to 90 % TSTG Storage temperature HSTG Storage humidity (without condensation) PBAR Barometric Pressure (operating & storage) o -50 to +100 C Notes 3 C 1 5 to 95 % 1 105 to 69 K Pascal 1, 2 Note: 1. Stress greater than those listed may cause permanent damage to the device.
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IDD and IDDQ Specification Parameters and Test Conditions IDD and IDDQ Measurement Conditions In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure below (Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements) shows the setup and test load for IDD and IDDQ measurements.
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IDDQ (optional) IDD VDD VDDQ RESET CK/CK DDR3L SDRAM CKE CS RAS, CAS, WE DQS, DQS DQ, DM, TDQS, TDQS A, BA ODT ZQ VSS RTT = 25 Ohm VDDQ/2 VSSQ Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements [Note: DIMM level Output test load condition may be different from above Application specific memory channel environment IDDQ Test Load Channel IO Power Simulation IDDQ Simulation IDDQ Simulation Correction Channel IO Power Number Correlation from simulated Channel IO Power t
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Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns Symbol tCK DDR3L-1333 DDR3L-1600 9-9-9 11-11-11 1.5 1.
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Symbol Description Precharge Standby Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank IDD2N Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 5.
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Symbol Description Operating Burst Read Current CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Command, Address, IDD4R Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst with different data between one burst and the next one according to Table 7; DM: stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...
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Symbol Description Operating Bank Interleave Read Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8a),f); AL: CL-1; CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according to Table IDD7 10; Data IO: read data burst with different data between one burst and the next one according to Table 10; DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...
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Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 ACT 0 0 1 1 0 0 00 0 0 0 0 - 1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 - D, D 1 1 1 1 0 0 00 0 0 0 0 - 0 0 0 - 0 F 0 - Cycle Number Datab) Sub-Loop CKE CK, CK Table 3 - IDD0 Measurement-Loop Patterna) 0 3,4 ... nRAS ... Static High toggling 1*nRC+0 repeat pattern 1...4 until nRAS - 1, truncate if necessary PRE 0 0 1 0 0 0 00 0 repeat pattern 1...
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Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 ACT 0 0 1 1 0 0 00 0 0 0 0 - 1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 - D, D 1 1 1 1 0 0 00 0 0 0 0 - 0 0 00000000 0 0 0 - Cycle Number Datab) Sub-Loop CKE CK, CK Table 4 - IDD1 Measurement-Loop Patterna) 0 3,4 ... nRCD ... nRAS Static High toggling ... repeat pattern 1...4 until nRCD - 1, truncate if necessary RD 0 1 0 1 0 0 00 0 0 repeat pattern 1...
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Static High CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 D 1 0 0 0 0 0 0 0 0 0 0 - 1 D 1 0 0 0 0 0 0 0 0 0 0 - 2 D 1 1 1 1 0 0 0 0 0 F 0 - 3 D 1 1 1 1 0 0 0 0 0 F 0 - Cycle Number Command 0 toggling Datab) Sub-Loop CKE CK, CK Table 5 - IDD2N and IDD3N Measurement-Loop Patterna) 1 4-7 repeat Sub-Loop 0, use BA[2:0] = 1 instead 2 8-11 repeat Sub-Loop 0, use BA[2:0] = 2 instead 3 12-15 repeat Sub-Loop 0, use
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Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 RD 0 1 0 1 0 0 00 0 0 0 0 00000000 1 D 1 0 0 0 0 0 00 0 0 0 0 - 2,3 D,D 1 1 1 1 0 0 00 0 0 0 0 - 4 RD 0 1 0 1 0 0 00 0 0 F 0 00110011 D 1 0 0 0 0 0 00 0 0 F 0 - D,D 1 1 1 1 0 0 00 0 0 F 0 - Cycle Number Datab) Sub-Loop CKE CK, CK Table 7 - IDD4R and IDDQ4R Measurement-Loop Patterna) 0 Static High toggling 5 6,7 1 8-15 repeat Sub-Loop
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Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] 0 0 REF 0 0 0 1 0 0 0 0 0 0 0 - 1 1.2 D, D 1 0 0 0 0 0 00 0 0 0 0 - D, D 1 1 1 1 0 0 00 0 0 F 0 - Cycle Number Datab) Sub-Loop CKE CK, CK Table 9 - IDD5B Measurement-Loop Patterna) Static High toggling 3,4 2 5...8 repeat cycles 1...4, but BA[2:0] = 1 9...12 repeat cycles 1...4, but BA[2:0] = 2 13...16 repeat cycles 1...4, but BA[2:0] = 3 17...20 repeat cycles 1...
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Table 10 - IDD7 Measurement-Loop Patterna) 2 3 4 Static High 5 6 7 8 9 10 4*nRRD nFAW nFAW+nRRD nFAW+2*nRRD nFAW+3*nRRD nFAW+4*nRRD 2*nFAW+0 2*nFAW+1 2&nFAW+2 11 2*nFAW+nRRD 2*nFAW+nRRD+1 2&nFAW+nRRD+2 12 13 2*nFAW+2*nRRD 2*nFAW+3*nRRD 14 2*nFAW+4*nRRD 15 16 17 18 3*nFAW 3*nFAW+nRRD 3*nFAW+2*nRRD 3*nFAW+3*nRRD 19 3*nFAW+4*nRRD 00110011 - 0 - 0 - 0 0 0 00110011 - 0 0 0 00000000 - 0 - 0 - A[10] 0 0 0 ODT 00000000 - WE 0 0 0 CAS ACT 0 0 1 1 0 0 00 0 0 0 RDA 0 1 0 1 0 0 00 1
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IDD Specifications (Tcase: 0 to 95oC) * Module IDD values in the datasheet are only a calculation based on the component IDD spec. The actual measurements may vary according to DQ loading cap.
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Module Dimensions 256Mx72 - HMT325U7CFR8A Front 2.10  0.15 Min 1.45 Max R0.70 30.00 SPD 4 x 3.00  0.10 17.30 DETAIL-B DETAIL-A 2 x  2.50  0.10 9.50 2 x 2.30  0.10 47.00 5.175 71.00 128.95 133.35 Back Detail - A FULL R 2.50 2.50  0.20 3.80 0.80  0.05 0.35 0.05 2.51mm Max Detail - B 0.3  0.15 Side 1.00 0.3~1.0 1.50  0.10 1.27±0.10 5.00 Note: 1.  0.13 tolerance on all dimensions unless otherwise stated. Units: millimeters Rev. 1.1 / Jul.
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512Mx72 - HMT351U7CFR8A Front 2.10  0.15 Min 1.45 Max R0.70 30.00 SPD 4 x 3.00  0.10 17.30 DETAIL-B DETAIL-A 2 x  2.50  0.10 9.50 2 x 2.30  0.10 47.00 5.175 71.00 128.95 133.35 Back Detail - B FULL R 2.50 2.50  0.20 3.80 0.80  0.05 0.35 0.05 3.64mm Max Detail - A 0.3  0.15 Side 1.00 1.27±0.10 0.3~1.0 1.50  0.10 5.00 Note: 1.  0.13 tolerance on all dimensions unless otherwise stated. Units: millimeters Rev. 1.1 / Jul.