Datasheet

Rev. 1.0 / May. 2014 32
Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)
Notes:
1. Used to define a differential signal slew-rate.
2. For CK - CK use VIH/VIL (ac) of AADD/CMD and VREFCA; for DQS - DQS, DQSL, DQSL, DQSU, DQSU use VIH/VIL
(ac) of DQs and VREFDQ; if a reduced ac-high or ac-low levels is used for a signal group, then the reduced level
applies also here.
3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU
need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limita
-
tions for overshoot and undershoot. Refer to "Overshoot and Undershoot Specifications" on page 41.
note : Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become
equal to or less than VIL(ac) level.
Differential AC and DC Input Levels
Symbol Parameter
DDR3L-800, 1066, 1333, 1600
Unit Notes
Min Max
VIHdiff Differential input high + 0.180 Note 3 V 1
VILdiff Differential input logic low Note 3 - 0.180 V 1
VIHdiff (ac) Differential input high ac 2 x (VIH (ac) - Vref) Note 3 V 2
VILdiff (ac) Differential input low ac Note 3 2 x (VIL (ac) - Vref) V 2
Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS
Slew Rate
[V/ns]
DDR3L-800/1066/1333/1600 DDR3L-1866
tDVAC [ps]
@ |VIH/Ldiff
(ac)| = 320mV
tDVAC [ps]
@ |VIH/Ldiff
(ac)| = 270mV
tDVAC [ps]
@ |VIH/Ldiff
(ac)| = 270mV
tDVAC [ps]
@ |VIH/Ldiff
(ac)| = 250mV
tDVAC [ps]
@ |VIH/Ldiff
(ac)| = 260mV
min max min max min max min max min max
> 4.0 189 - 201 - 163 - 168 - 176 -
4.0 189 - 201 - 163 - 168 - 176 -
3.0 162 - 179 - 140 - 147 - 154 -
2.0 109 - 134 95 105 111
1.8 91 - 119 - 80 - 91 - 97 -
1.6 69 - 100 - 62 - 74 - 78 -
1.4 40 - 76 - 37 - 52 - 56 -
1.2 note - 44 - 5 - 22 - 24 -
1.0 note - note - note - note - note -
< 1.0 note - note - note - note - note -