Datasheet

Rev. 1.0 / Aug. 2012 19
16GB, 2Gx72 Module(2Rank of x4) - page3
S0
S1
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
ODT0
CK0
CK0
PAR_IN
RS0A
→ CS0: SDRAMs D[3:0], D[12:8], D17
RS0B → CS0: SDRAMs D[7:4], D[16:13]
RS1A → CS1: SDRAMs D[21:18], D[30:26], D35
RRASB → RAS: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RS1B → CS1: SDRAMs D[25:22], D[34:31]
RBA[N:0]B → BA[N:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RRASA → RAS: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RCASB → CAS: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RCASA → CAS: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RWEB → WE: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RWEA → WE: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RCKE0B → CKE0: SDRAMs D[7:4], D[16:13]
RCKE0A → CKE0: SDRAMs D[3:0], D[12:8], D17
RODT0B → ODT0: SDRAMs D[7:4], D[16:13]
RODT0A → ODT0: SDRAMs D[3:0], D[12:8], D17
PCK0B → CK: SDRAMs D[7:4], D[16:13]
PCK0A → CK: SDRAMs D[3:0], D[12:8], D17
PCK0B → CK: SDRAMs D[7:4], D[16:13]
PCK0A → CK: SDRAMs D[3:0], D[12:8], D17
Err_Out
RESET RST
RST: SDRAMs D[35:0]
1:2
R
E
G
I
S
T
E
R
/
P
RCKE1B → CKE1: SDRAMs D[25:22], D[34:31]
RCKE1A → CKE1: SDRAMs D[21:18], D[30:26], D35
ODT1
RODT1A
→ ODT1: SDRAMs D[25:22], D[34:31]
RODT1A → ODT1: SDRAMs D[21:18], D[30:26], D35
CKE1
RA[N:0]B
→ A[N:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RA[N:0]A → A[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
PCK1B → CK: SDRAMs D[25:22], D[34:31]
PCK1A → CK: SDRAMs D[21:18], D[30:26], D35
PCK1B → CK: SDRAMs D[25:22], D[34:31]
PCK1A → CK: SDRAMs D[21:18], D[30:26], D35
L
L
* S[3:2], CK1 and CK1 are NC
CK1
CK1
120 Ω
±5%