Data Sheet

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Boot[0:7] Boot Mode
0000 0010 Nor Flash
1001 0110 UART0(115200)
0001 1110 JTAG
0000 1010 Nand FLASH
3V3D
3V3D
1V8D
3V3D
3V3D
ACC_UART0_TXD[13,6]
SD1_CLK [11]
SD1_CMD [11]
AK2401_nRST[13]
AP_UART1_RXD[13]
ACC_UART0_RXD[13,6]
GPS_UART2_TXD[12]
GPS_UART2_RXD[12]
TX_EN [9]
AEC_MCASPR_DR[10,6]
AEC_MCASPR_DX[10,6]
CPLD_MCBSP1_CLKX [13]
CPLD_MCBSP1_FSX [13]
AEC_MCASPR_FS[10,6]
AP_SPI0_CLK [15,6]
AP_SPI0_MOSI [15,6]
AP_SPI0_MISO [15,6]
AP_SPI0_nCS0 [15,6]
AEC_MCASPR_CLK [10,6]
AEC_MCASPR_FS [10,6]
CPLD_DSP_nINT [11,6]
AEC_MCASPR_CLK[10,6]
AP_SPI0_nINT[13]
CPLD_PROG[8]
SD1_DAT0 [11]
SD1_DAT1 [11]
SD1_DAT2 [11]
ACC_UART0_TXD [13,6]
ACC_UART0_RXD [13,6]
LCD_SPI_CLK[14]
LCD_SPI_DO[14]
LCD_SPI_nCS[14]
LCD_A[14]
DSP_TIMER_18.4MHz[18]
SYN_ON [9]
AEC_MCASPR_DR [10,6]
DSP_Deep_Sleep[10,6]
CPLD_MCBSP1_DX [13]
AK2401_MCBSP0_DR [13]
AK2401_MCBSP0_CLK [13]
AK2401_MCBSP0_FSX [13]
CPLD_MCBSP1_CLKX [13]
CPLD_MCBSP1_FSX [13]
CPLD_TMS[11,17]
CPLD_TCK[11,17]
CPLD_JTAG_EN[11]
EXT_PTT [11]
CPLD_TDI[11,17]
AP_SPI0_nINT [15,6]
AP_DSP_CTRL [11]
CPLD_DSP_BOOT2 [11]
CPLD_DSP_BOOT3 [11]
CPLD_DSP_BOOT4 [11]
CPLD_DSP_BOOT7 [11]
DSP_1WIRE [11]
SPI1_CLK [15,6]
SPI1_SIMO [15,6]
SPI1_SOMI [15,6]
PWR_CTRL [8]
DSP_CPLD_nINT [11,6]
CPLD_SPI_CS_Extend1 [15,6]
SD1_DAT3 [11]
CPLD_DSP_nINT [11]
CPLD_TDO[11,17]
TONE10
MOTOR_PWM[10,6]
DSP_CPLD_nRST [28]
DSP_ACC_GPIO [28]
AP_SPI0_CLK[15,6]
AP_SPI0_MOSI[15,6]
AP_SPI0_MISO[15,6]
SPI1_CLK[11]
SPI1_SOMI[11]
SPI1_SIMO[11]
AP_SPI0_nCS0[15,6]
CPLD_SPI_CS_Extend1[11]
AK2401_LD_PLL [13]
AP_UART1_TXD
CPLD_MCBSP1_DX
AK2401_AD_CLKR1
AK2401_AD_FSR1
AK2401_AD_DR1
AK2401_TX_nPD
AK2401_RX_nPD
AK2401_AGC_KEEP
LCD_nRST
VCO_ON [28]
RF_SW [25]
CPLD_USB_19.2M[13]
DSP_CPLD_nINT [28]
CPLD_DONE[12]
VCO_SW [28]
IN_PTT [15]
GPS_1PPS [15]
LCD_BL_PWM[15,6]
LCD_ID/DI
LCD_ID/DI
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Hytera Communications Co.,Ltd.
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5 68
Friday, May 10, 2019
PTC680
1.BB_DSP: GPIO/BUS
Model Name:
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Hytera Communications Co.,Ltd.
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5 68
Friday, May 10, 2019
PTC680
1.BB_DSP: GPIO/BUS
Model Name:
Prepare:
File No.:
Rev:
Date:
Page:
of
Part Name:
Hytera Communications Co.,Ltd.
Check:
Approve:
A
5 68
Friday, May 10, 2019
PTC680
1.BB_DSP: GPIO/BUS
R1020
4.7k
TD1040
1
TD1029
1
R1028 33
R1030 10k
R1029 10k
R1025 33
TD1007
1
R1045 33
TD1032
1
R1024 10k
R1023
4.7k
TD1009
1
TD1034
1
R1022 33
R1018 33
TD1035
1
TD1036
1
R1026
1k
R1034
10k
R1051
NC
R1031 33
TD1011
1
R1016 10k
R1052
NC
U1001B
TMS320C6746EZCED4
VP_DIN[15]_VSYNC/UHPI_HD[7]/UPP_D[7]/PRU0_R30[15]/PRU0_R31[15]
V18
VP_DIN[14]_HSYNC/UHPI_HD[6]/UPP_D[6]/PRU0_R30[14]/PRU0_R31[14]
V19
VP_DIN[13]_FIELD/UHPI_HD[5]/UPP_D[5]/PRU0_R30[13]/PRU0_R31[13]
U19
VP_DIN[12]/UHPI_HD[4]/UPP_D[4]/PRU0_R30[12]/PRU0_R31[12]
T16
VP_DIN[11]/UHPI_HD[3]/UPP_D[3]/PRU0_R30[11]/PRU0_R31[11]
R18
VP_DIN[10]/UHPI_HD[2]/UPP_D[2]/PRU0_R30[10]/PRU0_R31[10]
R19
VP_DIN[9]/UHPI_HD[1]/UPP_D[1]/PRU0_R30[9]/PRU0_R31[9]
R15
VP_DIN[8] / UHPI_HD[0] / UPP_D[0] / GP6[5] / PRU1_R31[0]
P17
VP_DIN[7] / UHPI_HD[15] / UPP_D[15] / RMII_TXD[1] / PRU0_R31[29]
U18
VP_DIN[6] / UHPI_HD[14] / UPP_D[14] / RMII_TXD[0] / PRU0_R31[28]
V16
VP_DIN[5] / UHPI_HD[13] / UPP_D[13] / RMII_TXEN / PRU0_R31[27]
R14
VP_DIN[4] / UHPI_HD[12] / UPP_D[12] / RMII_RXD[1] /PRU0_R31[26]
W16
VP_DIN[3] / UHPI_HD[11] / UPP_D[11] / RMII_RXD[0] / PRU0_R31[25]
V17
VP_DIN[2] / UHPI_HD[10] / UPP_D[10] / RMII_RXER / PRU0_R31[24]
W17
VP_DIN[1] / UHPI_HD[9] / UPP_D[9] / RMII_MHZ_50_CLK / PRU0_R31[23]
W18
VP_DIN[0] / UHPI_HD[8] / UPP_D[8] / RMII_CRS_DV / PRU1_R31[29]
W19
VP_CLKIN3 / MMCSD1_DAT[1] / PRU1_R30[1] / GP6[2] / PRU1_R31[2]
J3
VP_CLKIN2 / MMCSD1_DAT[3] / PRU1_R30[3] / GP6[4] / PRU1_R31[4]
H3
VP_CLKIN1 / UHPI_HDS1n / PRU1_R30[9] / GP6[6] / PRU1_R31[16]
V15
VP_CLKIN0 / UHPI_HCSn / PRU1_R30[10] GP6[7] / UPP_2xTXCLK
W14
SPI0_CLK / EPWM0A / GP1[8] / MII_RXCLK
D19
SPI0_SOMI / EPWMSYNCI / GP8[6] / MII_RXER
C16
SPI0_SIMO / EPWMSYNCO / GP8[5] / MII_CRS
C18
SPI0_ENAn / EPW M0B / PRU0_R30[6] / MII_RXDV
C17
SPI0_SCSn[5] / UART0_RXD / GP8[4] / MII_RXD[3]
C19
SPI0_SCSn[4] / UART0_TXD / GP8[3] / MII_RXD[2]
D18
SPI0_SCSn[3] / UART0_CTSn / GP8[2] / MII_RXD[1] / SATA_MP_SWITCH
E17
SPI0_SCSn[2] / UART0_RTSn / GP8[1] / MII_RXD[0] /SATA_CP_DET
D16
SPI0_SCSn[1] / TM64P0_OUT12 / GP1[7] / MDIO_CLK / TM64P0_IN12
E16
SPI0_SCSn[0] / TM64P1_OUT12 / GP1[6] / MDIO_D / TM64P1_IN12
D17
SPI1_CLK / GP2[13]
G19
SPI1_SOMI / GP2[11]
H17
SPI1_SIMO / GP2[10]
G17
SPI1_ENAn / GP2[12]
H16
SPI1_SCSn[7] / I2C0_SCL / TM64P2_OUT12 / GP1[5]
G16
SPI1_SCSn[6] / I2C0_SDA / TM64P3_OUT12 / GP1[4]
G18
SPI1_SCSn[5] / UART2_RXD / I2C1_SCL / GP1[3]
F17
SPI1_SCSn[4] / UART2_TXD / I2C1_SDA / GP1[2]
F16
SPI1_SCSn[3] / UART1_RXD / SATA_LED / GP1[1]
E18
SPI1_SCSn[2] / UART1_TXD / SATA_CP_POD / GP1[0]
F19
SPI1_SCSn[1] / EPW M1A / PRU0_R30[8] / GP2[15] / TM64P2_IN12
F18
SPI1_SCSn[0] / EPW M1B / PRU0_R30[7] / GP2[14] / TM64P3_IN12
E19
RTC_ALARM / UART2_CTSn / GP0[8] / DEEPSLEEPn
F4
AMUTE / PRU0_R30[16] / UART2_RTSn / GP0[9] / PRU0_R31[16]
D5
AXR7 / EPWMN1_TZ[0] / PRU0_R30[17] / GP1[15] / PRU0_R31[7]
D2
AXR15 / EPW M0TZ[0] / ECAP2_APWM2 / GP0[7]
A4
AFSX / GP0[12] / PRU0_R31[19]
B2
AFSR / GP0[13] / PRU0_R31[20]
C2
AHCLKX / USB_REFCLKIN / UART1_CTSn / GP0[10] / PRU0_R31[17]
A3
AHCLKR / PRU0_R30[18] / UART1_RTSn / GP0[11] / PRU0_R31[18]
A2
ACLKX / PRU0_R30[19] / GP0[14] / PRU0_R31[21]
B1
ACLKR / PRU0_R30[20] / GP0[15] / PRU0_R31[22]
A1
VP_DOUT[15] / LCD_D[15] / UPP_XD[7] / GP7[7] / BOOT[7]
P4
VP_DOUT[14] / LCD_D[14] / UPP_XD[6] / GP7[6] / BOOT[6]
R3
VP_DOUT[13] / LCD_D[13] / UPP_XD[5] / GP7[5] / BOOT[5]
R2
VP_DOUT[12] / LCD_D[12] / UPP_XD[4] / GP7[4] / BOOT[4]
R1
VP_DOUT[11] / LCD_D[11] / UPP_XD[3] / GP7[3] / BOOT[3]
T3
VP_DOUT[10] / LCD_D[10] / UPP_XD[2] / GP7[2] / BOOT[2]
T2
VP_DOUT[9] / LCD_D[9] / UPP_XD[1] / GP7[1] / BOOT[1]
T1
VP_DOUT[8] / LCD_D[8] / UPP_XD[0] / GP7[0] / BOOT[0]
U3
VP_DOUT[7] / LCD_D[7] / UPP_XD[15] / GP7[15] / PRU1_R31[15]
U2
VP_DOUT[6] / LCD_D[6] / UPP_XD[14] / GP7[14] / PRU1_R31[14]
U1
VP_DOUT[5] / LCD_D[5] / UPP_XD[13] / GP7[13] / PRU1_R31[13]
V3
VP_DOUT[4] / LCD_D[4] / UPP_XD[12] / GP7[12] / PRU1_R31[12]
V2
VP_DOUT[3] / LCD_D[3] / UPP_XD[11] / GP7[11] / PRU1_R31[11]
V1
VP_DOUT[2] / LCD_D[2] / UPP_XD[10] / GP7[10] / PRU1_R31[10]
W3
VP_DOUT[1] / LCD_D[1] / UPP_XD[9] / GP7[9] / PRU1_R31[9]
W2
VP_DOUT[0] / LCD_D[0] / UPP_XD[8] / GP7[8] / PRU1_R31[8]
W1
MMCSD1_DAT[5] / LCD_HSYNC / PRU1_R30[5] / GP8[9] / PRU1_R31[6]
H4
MMCSD1_DAT[4] / LCD_VSYNC / PRU1_R30[4] / GP8[8] / PRU1_R31[5]
G4
MMCSD1_DAT[6] / LCD_MCLK / PRU1_R30[6] / GP8[10] / PRU1_R31[7]
F2
MMCSD1_DAT[7] / LCD_PCLK / PRU1_R30[7] / GP8[11]
F1
LCD_AC_ENB_CSn / GP6[0] / PRU1_R31[28]
R5
VP_CLKOUT3 / PRU1_R30[0] / GP6[1] / PRU1_R31[1]
K4
VP_CLKOUT2 / MMCSD1_DAT[2] / PRU1_R30[2] / GP6[3] / PRU1_R31[3]
K3
PRU0_R30[25] / MMCSD1_DAT[0] / UPP_CHB_CLOCK / GP8[15] / PRU1_R31[27]
G1
PRU0_R30[24] / MMCSD1_CLK / UPP_CHB_START / GP8[14] / PRU1_R31[26]
G2
PRU0_R30[23] / MMCSD1_CMD / UPP_CHB_ENABLE / GP8[13] / PRU1_R31[25]
J4
PRU0_R30[22] / PRU1_R30[8] / UPP_CHB_WAIT / GP8[12] / PRU1_R31[24]
G3
PRU0_R30[29] / UHPI_HCNTL0 / UPP_CHA_CLOCK / GP6[11]
U17
PRU0_R30[28] / UHPI_HCNTL1 / UPP_CHA_START / GP6[10]
W15
PRU0_R30[27] / UHPI_HHWIL / UPP_CHA_ENABLE / GP6[9]
U16
PRU0_R30[26] / UHPI_HRWn / UPP_CHA_WAIT/GP6[8] / PRU1_R31[17]
T15
PRU0_R30[30] / UHPI_HINTn / PRU1_R30[11] / GP6[12]
R16
PRU0_R30[31] / UHPI_HRDYn / PRU1_R30[12] / GP6[13]
R17
AXR6 / CLKR0 / GP1[14] / MII_TXEN / PRU0_R31[6]
C1
AXR5 / CLKX0 / GP1[13] / MII_TXCLK
D3
AXR0 / ECAP0_APWM0 / GP8[7]/ MII_TXD[0] / CLKS0
F3
AXR4 / FSR0 / GP1[12] / MII_COL
D1
AXR3 / FSX0 / GP1[11] / MII_TXD[3]
E3
AXR2 / DR0 / GP1[10] / MII_TXD[2]
E2
AXR1 / DX0 / GP1[9] / MII_TXD[1]
E1
AXR14 / CLKR1 / GP0[6]
B4
AXR13 / CLKX1 / GP0[5]
B3
AXR8 / CLKS1 / ECAP1_APWM1 / GP0[0] / PRU0_R31[8]
E4
AXR12 / FSR1 / GP0[4]
C4
AXR11 / FSX1 / GP0[3]
C5
AXR10 / DR1 / GP0[2]
D4
AXR9 / DX1 / GP0[1]
C3
SATA_REFCLKN
N1
SATA_REFCLKP
N2
SATA_TXN
J2
SATA_TXP
J1
SATA_RXN
L2
SATA_RXP
L1
NC[SATA_AMUX]
M3
R1013 10k
TD1014
1
R1053
10K
TP1033
1
R1054
NC
TD1010
1
TP1016
1
TD1008
1
TD1017
1
TD1041
1
R1055
10k
R1014 10k
TD1013
1
R1048 NC
TD1037
1
TD1021
1
R1049
NC
TD1005
1
R1050
10k
TD1038
1
TD1027
1
TD1006
1
TD1039
1
Mode1 Mode2 Mode3
Mode1
Mode2
Mode3
DSP_CPLD_nRST
IN_PTT
GND
IN_PTT
DSP_CPLD_nRST