Intel® Xeon® Processor 7200 Series and 7300 Series Datasheet September 2008 Notice: The Intel® Xeon® Processor 7200 Series and 7300 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.
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Contents 1 Introduction .............................................................................................................. 9 1.1 Terminology ..................................................................................................... 11 1.2 State of Data .................................................................................................... 13 1.3 References .......................................................................................................
6.3 6.2.3 Thermal Monitor 2 ................................................................................ 104 6.2.4 On-Demand Mode ................................................................................. 105 6.2.5 PROCHOT# Signal ................................................................................ 106 6.2.6 FORCEPR# Signal ................................................................................. 106 6.2.7 THERMTRIP# Signal ....................................................
Figures 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 2-27 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 6-1 6-2 6-3 6-4 6-5 6-6 6-7 Quad-Core Intel® Xeon® L7345 Processor Load Current versus Time ..................... 27 Dual-Core Dual-Core Intel® Xeon® Processor 7200 Series Load Current versus Time......................................................................................................
-8 7-1 7-2 Conceptual Fan Control Diagram For a PECI-Based Platform .................................. 108 Stop Clock State Machine.................................................................................. 114 Logical Schematic of SMBus Circuitry..................................................................
-2 7-3 7-4 7-5 7-6 7-7 Extended HALT Maximum Power........................................................................ 113 Memory Device SMBus Addressing..................................................................... 118 Read Byte SMBus Packet .................................................................................. 118 Write Byte SMBus Packet ................................................................................. 118 Processor Information ROM Data Sections ...................
Revision History Document Number Revision 318080 -001 • Initial Release September 2007 318080 -002 • Changed Product Name to Intel® Xeon® Processor 7200 Series and 7300 Series Updated Power Specifications The character byte ordering was reversed for the following fields: SQNUM: S-Spec QDF Number PREV: Package Revision PPN: Processor Part Number Updated the Processor Mechanical drawings to add an optional small shallow depression in the top right-hand side corner of the integrated heat spreader (IH
Introduction 1 Introduction ALL INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE. The Intel® Xeon® Processor 7200 Series and 7300 Series are multi-processor servers utilizing four Intel® CoreTM microarchitecture cores. These processors are based on Intel’s 65 nanometer process technology combining high performance with the power efficiencies of a low-power microarchitecture. The Quad-Core Intel® Xeon® 7300 Series consists of two die, each die containing two processor cores.
Introduction The Intel® Xeon® Processor 7200 Series and 7300 Series support Intel® Virtualization Technology for hardware-assisted virtualization within the processor. Intel Virtualization Technology is a set of hardware enhancements that can improve virtualization solutions. Intel Virtualization Technology is used in conjunction with Virtual Machine Monitor software enabling multiple, independent software environments inside a single platform.
Introduction Signals on the FSB use Assisted Gunning Transceiver Logic (AGTL+) level voltages. Section 2.1 contains the electrical specifications of the FSB while implementation details are fully described in the appropriate platform design guidelines (refer to Section 1.3). 1.1 Terminology A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the asserted state when driven to a low level. For example, when RESET# is low, a reset has been requested.
Introduction • Processor Information ROM (PIROM) — A memory device located on the processor and accessible via the System Management Bus (SMBus) which contains information regarding the processor’s features. This device is shared with the Scratch EEPROM, is programmed during manufacturing, and is write-protected.
Introduction 1.2 State of Data This document contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design 1.
Introduction 14 Document Number: 318080-002
Electrical Specifications 2 Electrical Specifications 2.1 Front Side Bus and GTLREF Most Intel® Xeon® Processor 7200 Series and 7300 Series FSB signals use Assisted Gunning Transceiver Logic (AGTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. AGTL+ buffers are open-drain and require pull-up resistors to provide the high logic level and termination.
Electrical Specifications remains within the specifications listed in Table 2-9. Failure to do so can result in timing violations or reduced lifetime of the component. For further information and guidelines, refer to the appropriate platform design guidelines. 2.2.1 VCC Decoupling Vcc regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR). Bulk decoupling must be provided on the baseboard to handle large current swings.
Electrical Specifications Table 2-1. Core Frequency to FSB Multiplier Configuration Core Frequency to FSB Multiplier Core Frequency with 266 MHz FSB Clock Notes 1/6 1.60 GHz 1, 2, 3, 4 1/7 1.86 GHz 1, 2, 3 1/8 2.13 GHz 1, 2, 3 1/9 2.40 GHz 1, 2, 3 1/10 2.66 GHz 1, 2, 3 1/11 2.93 GHz 1, 2, 3 Notes: 1. Individual processors operate only at or below the frequency marked on the package. 2. Listed frequencies are not necessarily committed production frequencies. 3.
Electrical Specifications outputs. Please refer to Table 2-12 for the DC specifications for these signals. A voltage range is provided in Table 2-3 and changes with frequency. The specifications have been set such that one voltage regulator can operate with all supported frequencies. Individual processor VID values may be calibrated during manufacturing such that two devices at the same core frequency may have different default VID settings. This is reflected by the VID range values provided in Table 2-3.
Electrical Specifications Table 2-3. Voltage Identification Definition VID6 VID5 VID4 VID3 VID2 VID1 12.5 mV VCC_MAX HEX 7A 1 1 1 1 0 1 0.8500 78 1 1 1 1 0 0 76 1 1 1 0 1 1 74 1 1 1 0 1 72 1 1 1 0 0 HEX 400 mV 200 mV 100 mV 50 mV 25 mV VID6 VID5 VID4 VID3 VID2 VID1 12.5 mV VCC_MAX 3C 0 1 1 1 1 0 1.2375 0.8625 3A 0 1 1 1 0 1 1.2500 0.8750 38 0 1 1 1 0 0 1.2625 0 0.8875 36 0 1 1 0 1 1 1.2750 1 0.
Electrical Specifications 2.5 Reserved, Unused, or Test Signals All Reserved signals must remain unconnected. Connection of these signals to VCC, VTT, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Section 4 for a pin listing of the processor and the location of all Reserved signals. For reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level.
Electrical Specifications Table 2-4. FSB Signal Groups Signal Group Signals1 Type AGTL+ Common Clock Input Synchronous to BCLK[1:0] BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#; AGTL+ Common Clock Output Synchronous to BCLK[1:0] BPM4#, BPM[2:1]#, BPMb[2:1]# AGTL+ Common Clock I/O Synchronous to BCLK[1:0] ADS#, AP[1:0]#, BINIT#2, BNR#2, BPM5#, BPM3#, BPM0#, BPMb3#, BPMb0#, BR[1:0]#, DBSY#, DP[3:0]#, DRDY#, HIT#2, HITM#2, LOCK#, MCERR#2 AGTL+ Source Synchronous I/O Synchronous to assoc.
Electrical Specifications Table 2-5 outlines the signals which include on-die termination (RTT). Table 2-6 outlines non AGTL+ signals including open drain signals. Table 2-7 provides signal reference voltages. Table 2-5.
Electrical Specifications 2.9 Mixing Processors Intel supports and validates multi-processor configurations only in which all processors operate with the same FSB frequency, core frequency, number of cores, and have the same internal cache sizes. Mixing components operating at different internal clock frequencies or number of cores is not supported and will not be validated by Intel.
Electrical Specifications 2.11 Processor DC Specifications The following notes apply: • The processor DC specifications in this section are defined at the processor die and not at the package pins unless noted otherwise. • The notes associated with each parameter are part of the specification for that parameter. • Unless otherwise noted, all specifications in the tables apply to all frequencies and cache sizes. See Section 5 for the pin signal definitions.
Electrical Specifications 2.11.1 Flexible Motherboard Guidelines (FMB) The Flexible Motherboard (FMB) guidelines are estimates of the maximum values the Dual-Core Intel® Xeon® Processor 7200 Series and Quad-Core Intel® Xeon® Processor 7300 Series will have over certain time periods. The values are only estimates and actual specifications for future processors may differ. Processors may or may not have specifications equal to the FMB value in the foreseeable future.
Electrical Specifications Table 2-9. Voltage and Current Specifications (Sheet 2 of 2) Symbol Min Typ Notes Max Unit ICC for VTT supply before VCC stable ICC for VTT supply after VCC stable 8.
Electrical Specifications 9. 10. 11. 12. 13. 14. 15. 16. 17. Figure 2-1. Minimum VCC and maximum ICC are specified at the maximum processor case temperature (TCASE) shown in Figure 6-2. This specification refers to the total reduction of the load line due to VID transitions below the specified VID. Individual processor VID values may be calibrated during manufacturing such that two devices at the same frequency may have different VID settings. This specification applies to the VCCPLL pin.
Electrical Specifications Figure 2-2. Dual-Core Dual-Core Intel® Xeon® Processor 7200 Series Load Current versus Time Sustained Current (A) 10 0 95 90 85 80 75 70 65 60 0 .0 1 0 .1 1 10 10 0 10 0 0 Tim e Duration (s) Notes: 1. Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than ICC_TDC. 2. Not 100% tested. Specified by design characterization Figure 2-3.
Electrical Specifications Figure 2-4. Quad-Core Intel® Xeon® X7350 Processor Load Current versus Time Sustained Current (A) 13 0 12 5 12 0 115 110 10 5 10 0 0 .0 1 0 .1 1 10 10 0 10 0 0 Tim e Duration (s) Notes: 1. Processor or Voltage Regulator thermal protection circuitry should not trip for load currents greater than ICC_TDC. 2. Not 100% tested. Specified by design characterization.
Electrical Specifications Table 2-10. VCC Static and Transient Tolerance ICC (A) VCC_Max (V) VCC_Typ (V) VCC_Min (V) Notes 0 VID - 0.000 VID - 0.015 VID - 0.030 1, 2, 3 5 VID - 0.006 VID - 0.021 VID - 0.036 1, 2, 3 10 VID - 0.013 VID - 0.028 VID - 0.043 1, 2, 3 15 VID - 0.019 VID - 0.034 VID - 0.049 1, 2, 3 20 VID - 0.025 VID - 0.040 VID - 0.055 1, 2, 3 25 VID - 0.031 VID - 0.046 VID - 0.061 1, 2, 3 30 VID - 0.038 VID - 0.053 VID - 0.068 1, 2, 3 35 VID - 0.
Electrical Specifications Figure 2-5. Quad-Core Intel® Xeon® Processor 7200 Series and 7300 Series VCC Static and Transient Tolerance Load Lines Icc [A] 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 VID - 0.000 VID - 0.020 VCC Maximum VID - 0.040 Vcc [V] VID - 0.060 VID - 0.080 VID - 0.100 VID - 0.120 VID - 0.140 VCC Typical VCC Minimum VID - 0.160 Notes: 1. The VCC_MIN and VCC_MAX loadlines represent static and transient limits. Please see Section 2.11.
Electrical Specifications Figure 2-6. Quad-Core Intel® Xeon® X7350 Processor VCC Static and Transient Tolerance Load Lines Icc [A ] 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 V ID - 0.000 VCC M ax im um V ID - 0.050 Vcc [V] V ID - 0.100 V ID - 0.150 VCC Ty pic al V ID - 0.200 VCC M inim um V ID - 0.250 Notes: 1. The VCC_MIN and VCC_MAX loadlines represent static and transient limits. Please see Section 2.11.
Electrical Specifications Figure 2-7. Quad-Core Intel® Xeon® L7345 Processor VCC Static and Transient Tolerance Load Lines Icc [A] 0 5 10 15 20 25 30 35 40 45 50 55 60 VID - 0.000 VID - 0.010 VCC Maximum VID - 0.020 VID - 0.030 Vcc [V] VID - 0.040 VID - 0.050 VID - 0.060 VID - 0.070 VCC Typical VID - 0.080 VID - 0.090 VCC Minimum VID - 0.100 Notes: 1. The VCC_MIN and VCC_MAX loadlines represent static and transient limits. Please see Section 2.11.
Electrical Specifications Figure 2-8. Dual-Core Intel® Xeon® Processor 7200 Series VCC Static and Transient Tolerance Load Lines Icc [A] 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 VID - 0.000 VID - 0.020 VCC Maximum VID - 0.040 Vcc [V] VID - 0.060 VID - 0.080 VID - 0.100 VCC Typical VID - 0.120 VCC Minimum VID - 0.140 VID - 0.160 Notes: 1. The VCC_MIN and VCC_MAX loadlines represent static and transient limits. Please see Section 2.11.
Electrical Specifications Table 2-12. CMOS Signal Input/Output Group DC Specifications Symbol Parameter Min Typ Max Units Notes1 VIL Input Low Voltage -0.10 0.00 0.3*VTT V 2,3 VIH Input High Voltage 0.7*VTT VTT VTT+0.1 V 2 VOL Output Low Voltage -0.10 0 0.1*VTT V 2 VOH Output High Voltage 0.9*VTT VTT VTT+0.1 V 2 IOL Output Low Current 1.70 N/A 4.70 mA 4 IOH Output High Current 1.70 N/A 4.
Electrical Specifications 7300 Series contains Digital Thermal Sensors (DTS) distributed throughout the die. These sensors are implemented as analog-to-digital converters calibrated at the factory for reasonable accuracy to provide a digital representation of relative processor temperature. PECI provides an interface to relay the highest DTS temperature within a die to external management devices for thermal/fan speed control. 2.11.2.
Electrical Specifications Figure 2-9. Input Device Hysteresis VTT Maximum VP PECI High Range Minimum VP Minimum Hysteresis Valid Input Signal Range Maximum VN Minimum VN PECI Low Range PECI Ground 2.11.3 VCC Overshoot Specification Processors can tolerate short transient overshoot events where VCC exceeds the VID voltage when transitioning from a high-to-low current load condition. This overshoot cannot exceed VID + VOS_MAX (VOS_MAX is the maximum allowable overshoot above VID).
Electrical Specifications Figure 2-10. VCC Overshoot Example Waveform Example Overshoot Waveform VOS Voltage [V] VID + 0.050 VID - 0.000 TOS 0 5 10 15 20 25 Time [us] TOS: Overshoot time above VID VOS: Overshoot above VID Notes: 1. VOS is the measured overshoot voltage. 2. TOS is the measured time duration above VID. 2.11.3.
Electrical Specifications Table 2-17. AGTL+ Bus Voltage Definitions Parameter Min Typ Max Units Notes1 GTLREF_DATA_MID GTLREF_DATA_END Data Bus Reference Voltage 0.98 * 0.67 * VTT 0.67 * VTT 1.02 * 0.67 * VTT V 2, 3 GTLREF_ADD_MID GTLREF_ADD_END Address Bus Reference Voltage 0.98 * 0.67 * VTT 0.67 * VTT 1.02 * 0.67 * VTT V 2, 3 RTT Termination Resistance (pull up) 45 50 55 Ω 4 COMP COMP Resistance 49.4 49.9 50.4 Ω 5 Symbol Notes: 1.
Electrical Specifications 2.12 Front Side Bus AC Specifications The processor FSB timings specified in this section are defined at the processor core (pads). Therefore, proper simulation of the FSB is the only means to verify proper timing and signal quality. See Table 4-1 for the pin listing and Table 5-1 for signal definitions. Table 2-19 through Table 2-24 list the AC specifications associated with the processor FSB.
Electrical Specifications 5. 6. 7. 8. Specification is for a minimum swing is specified into the test circuit described in Figure 2-11 and defined between AGTL+ VIL_MAX to VIH_MIN. This assumes an edge rate of 2.0 V/ns to 3.0 V/ns. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously. This should be measured after VTT and BCLK[1:0] become stable. Maximum specification applies only while PWRGOOD is asserted. . Table 2-21.
Electrical Specifications Table 2-22. Miscellaneous GTL+ AC Specifications T# Parameter Min T35: Asynchronous GTL+ input pulse width Unit 10 ms 2-24 10 BCLKs 2-24 6,12 500 µs 2-20 7 8 30 T36: PWRGOOD assertion to RESET# de-assertion 1 T37: BCLK stable to PWRGOOD assertion T38: PROCHOT# pulse width T39: THERMTRIP# assertion until VCC removed 5 500 ms 2-21 5 BCLKs 2-25 0.
Electrical Specifications Table 2-24. TAP Signal Group AC Specifications (Sheet 2 of 2) T# Parameter T57: TDI, TMS Hold Time Min Max 7.5 T58: TDO Clock to Output Delay 0 T59: TRST# Assert Time 2 7.5 Unit Figure Notes 1, 2, 8 ns 2-19 4,7 ns 2-19 5 TTCK 2-20 6 Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Not 100% tested. Specified by design characterization. 3.
Electrical Specifications Table 2-25. VID Signal Group AC Specifications T # Parameter Min T80: VID Step Time T81: VID Dwell Time at 266.666 MHz FSB Max 5 500 Unit Figure µs 2-27 µs 2-27 0 µs 2-26,2-27 T83: VID Up Transition to Valid VCC (min) 50 µs 2-26,2-27 T84: VID Down Transition to Valid VCC (max) 50 µs 2-26,2-27 0 µs 2-26,2-27 T82: VID Down Transition to Valid VCC (min) T85: VID Up Transition to Valid VCC (max) Notes1, 2 Notes: 1.
Electrical Specifications 2.13 Processor AC Timing Waveforms The following figures are used in conjunction with the AC timing tables, Table 2-19 through Table 2-25. Note: For Figure 2-12 through Figure 2-25, the following apply: 1. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (VCROSS) of the BCLK[1:0] at rising edge of BCLK0.
Electrical Specifications Figure 2-11. Electrical Test Circuit Figure 2-12. TCK Clock Waveform V2 TCK V3 V1 Tp Tp = T55: Period V1, V2: For rise and fall times, TCK is measured between 20% and 80% points on the waveform. V3: TCK is referenced to 0.
Electrical Specifications Figure 2-13. Differential Clock Waveform Overshoot BCLK1 VH Rising Edge Ringback Crossing Voltage Threshold Region Crossing Voltage Ringback Margin Falling Edge Ringback, BCLK0 VL Undershoot Tp Tp = T1: BCLK[1:0] period Figure 2-14. Differential Clock Crosspoint Specification 650 Crossing Point (mV) 600 550 550 mV 500 450 550 + 0.5 (VHavg - 700) 400 250 + 0.
Electrical Specifications Figure 2-15. BCLK Waveform at Processor Pad and Pin Notes: 1. Waveform at pin is non-monotonic. Waveform at pad is monotonic. 2. Differential Edge Rate (DER) measured zero +/- 200mv. 3. g indicates V/ns units and meg indicates mv/ns units. 4. Waveform at pad has faster edge rate than at pin. Figure 2-16.
Electrical Specifications Figure 2-17. FSB Source Synchronous 2X (Address) Timing Waveform T0 Tp/4 Tp/2 T1 3Tp/4 T2 BCLK1 BCLK0 TR ADSTB# (@ driver) TJ TH A# (@ driver) valid TJ TH valid TK TS ADSTB# (@ receiver) A# (@ receiver) valid TM valid TN TP = T1: BCLK[1:0] Period TH = T23: Source Sync. Address Output Valid Before Address Strobe TJ = T24: Source Sync. Address Output Valid After Address Strobe TK = T27: Source Sync. Address Strobe Setup Time to BCLK TM = T25: Source Sync.
Electrical Specifications Figure 2-18. FSB Source Synchronous 4X (Data) Timing Waveform T0 Tp/4 Tp/2 T1 3Tp/4 T2 BCLK1 BCLK0 TD DSTBp# (@ driver) DSTBn# (@ driver) TA TB TA TB D# (@ driver) TC DSTBp# (@ receiver) TJ DSTBn# (@ receiver) D# (@ receiver) TE TG TE TG TP = T1: BCLK[1:0] Period TA = T21: Source Sync. Data Output Valid Delay Before Data Strobe TB = T22: Source Sync. Data Output Valid Delay After Data Strobe TC = T28: Source Sync.
Electrical Specifications Figure 2-19. TAP Valid Delay Timing Waveform V TCK Tx Ts Th V Valid Signal Tx = T58: TDO Clock to Output Delay Ts = T56: TDI, TMS Setup Time Th = T57: TDI, TMS Hold Time V = 0.5 * VTT Note: Please refer to Table 2-12 for TAP Signal Group DC specifications and Table 2-24 for TAP Signal Group AC specifications. Figure 2-20. Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform V Tq T = T59 (TRST# Pulse Width), V = 0.
Electrical Specifications Figure 2-22. SMBus Timing Waveform t t LOW tF R t HD;STA Clk t HD;STA t t HD;DAT t SU;DAT HIGH t SU;STA t SU;STO Data t BUF P STOP S S START START t LOW = T93 t HD;STA = T100 t SU;STA = T101 t HIGH = T92 t HD;DAT = T98 t SU;STD = T102 tR = T94 t BUF = T95 t SU;DAT = T97 tF P STOP = T99 Figure 2-23.
Electrical Specifications Figure 2-24.
Electrical Specifications Figure 2-25. FERR#/PBE# Valid Delay Timing BCLK SG Ack System bus STPCLK# Ta FERR#/PBE# FERR# undefined PBE# undefined FERR# Notes: 1. Ta = T40 (FERR# Valid Delay from STPCLK# Deassertion). 2. FERR# / PBE# is undefined from STPCLK# assertion until the Stop-Grant acknowledge is driven on the FSB. FERR# / PBE# is also undefined for a period of Ta from STPCLK# deassertion. Inside these undefined regions, the PBE# signal is driven. FERR# is driven at all other times.
Electrical Specifications Figure 2-27.
Electrical Specifications 56 Document Number: 318080-002
Mechanical Specifications 3 Mechanical Specifications The Intel® Xeon® Processor 7200 Series and 7300 Series is packaged in a FC-mPGA6 package that interfaces with the motherboard via a mPGA604 socket. The package consists of two processor dies mounted on a substrate pin-carrier. An IHS is attached to the package substrate and die and serves as the mating surface for processor component thermal solutions, such as a heatsink.
Mechanical Specifications Figure 3-2.
Mechanical Specifications Figure 3-3.
Mechanical Specifications 3.2 Processor Component Keepout Zones The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keepout zones. Decoupling capacitors are typically mounted to either the topside or pin-side of the package substrate. See Figure 3-4 and Figure 3-5 for keepout zones.
Mechanical Specifications Figure 3-4.
Mechanical Specifications Figure 3-5.
Mechanical Specifications Figure 3-6.
Mechanical Specifications Figure 3-7.
Mechanical Specifications Figure 3-8.
Mechanical Specifications 3.3 Package Loading Specifications Table 3-1 provides dynamic and static load specifications for the processor package. These mechanical load limits should not be exceeded during heatsink assembly, shipping conditions, or standard use condition. Also, any mechanical system or component testing should not exceed the maximum limits. The processor package substrate should not be used as a mechanical reference or load-bearing surface for thermal and mechanical solutions.
Mechanical Specifications 3.4 Package Handling Guidelines Table 3-2 includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate. These package handling loads may be experienced during heatsink removal. Table 3-2. Package Handling Guidelines Parameter Maximum Recommended Notes Shear 356 N [80 lbf] 1, 2 Tensile 156 N [35 lbf] 3, 2 Torque 8 N-m [70 lbf-in] 4, 2 Notes: 1. 2. 3. 4. 3.
Mechanical Specifications 3.8 Processor Markings Figure 3-9 shows the topside markings and Figure 3-10 shows the bottom-side markings on the processor. These diagrams are to aid in the identification of the Intel® Xeon® Processor 7200 Series and 7300 Series. Please note that the figures in this section are not to scale. Figure 3-9. Processor Topside Markings INTEL® XEON® i{M}©’YY {PbFree symbol} 2D Matrix FPO – Serial # Pin 1 Indicator Notes: 1.
Mechanical Specifications 3.9 Processor Pin-Out Coordinates Figure 3-11 shows the top view of the processor pin coordinates. The coordinates are referred to throughout the document to identify processor pins. Figure 3-11.
Mechanical Specifications 70 Document Number: 318080-002
Pin Listing 4 Pin Listing 4.1 Pin Assignments Section 2.6 contains the front side bus signal groups for the Intel® Xeon® Processor 7200 Series and 7300 Series (see Table 2-4). This section provides a sorted pin lists in Table 4-1 and Table 4-2. Table 4-1 is a listing of all processor pins ordered alphabetically by pin name. Table 4-2 is a listing of all processor pins ordered by pin number. 4.1.1 Pin Listing by Pin Name Table 4-1. Pin Listing by Pin Name (Sheet 1 of 16) Pin Name Pin No.
Pin Listing Table 4-1. Pin Listing by Pin Name (Sheet 3 of 16) Table 4-1. Pin Listing by Pin Name (Sheet 4 of 16) Pin No. Signal Buffer Type BPMb3# AE3 Common Clk Input/Output D29# AD21 BPRI# D23 Common Clk Input D30# AD19 Source Sync Input/Output BR0# D20 Common Clk Input/Output D31# AB17 Source Sync Input/Output Pin Name Direction Pin Name Pin No.
Pin Listing Table 4-1. Pin Listing by Pin Name (Sheet 5 of 16) Pin Name DEFER# Pin No. Signal Buffer Type C23 Common Clk Direction Table 4-1. Pin Listing by Pin Name (Sheet 6 of 16) Pin Name Pin No.
Pin Listing Table 4-1. Pin Listing by Pin Name (Sheet 7 of 16) Pin Name SM_WP Pin No. AD29 Signal Buffer Type Direction Table 4-1. Pin Listing by Pin Name (Sheet 8 of 16) Pin Name Pin No.
Pin Listing Table 4-1. Pin Listing by Pin Name (Sheet 9 of 16) Pin Name Pin No. Signal Buffer Type Direction Table 4-1. Pin Listing by Pin Name (Sheet 10 of 16) Pin Name VCC M1 Power/Other VCC VCC M3 Power/Other VCC M5 Power/Other VCC M7 VCC M9 Pin No.
Pin Listing Table 4-1. Pin Listing by Pin Name (Sheet 11 of 16) Pin Name Pin No. Signal Buffer Type Direction Table 4-1. Pin Listing by Pin Name (Sheet 12 of 16) Pin Name Pin No.
Pin Listing Table 4-1. Pin Listing by Pin Name (Sheet 13 of 16) Pin Name Pin No. Signal Buffer Type Direction Table 4-1. Pin Listing by Pin Name (Sheet 14 of 16) Pin Name Pin No.
Pin Listing Table 4-1. Pin Listing by Pin Name (Sheet 15 of 16) Pin Name Pin No. Signal Buffer Type Table 4-1. Pin Listing by Pin Name (Sheet 16 of 16) Direction Pin Name VSS V9 Power/Other VSS Pin No.
Pin Listing 4.1.2 Pin Listing by Pin Number Table 4-2. Pin Listing by Pin Number (Sheet 1 of 14) Pin No. Pin Name A1 VID5 A2 VTT_SEL A3 SKTOCC# Signal Buffer Type Direction Table 4-2. Pin Listing by Pin Number (Sheet 2 of 14) Pin No.
Pin Listing Table 4-2. Pin Listing by Pin Number (Sheet 3 of 14) Pin No. 80 Pin Name Signal Buffer Type Direction Table 4-2. Pin Listing by Pin Number (Sheet 4 of 14) Pin No.
Pin Listing Table 4-2. Pin Listing by Pin Number (Sheet 5 of 14) Pin No. Pin Name Signal Buffer Type F18 DBSY# Common Clk F19 VSS Power/Other F20 BNR# Common Clk F21 RS2# F22 A37# F23 Direction Input/Output Table 4-2. Pin Listing by Pin Number (Sheet 6 of 14) Pin No.
Pin Listing Table 4-2. Pin Listing by Pin Number (Sheet 7 of 14) Pin No. 82 Pin Name Signal Buffer Type Direction Table 4-2. Pin Listing by Pin Number (Sheet 8 of 14) Pin No.
Pin Listing Table 4-2. Pin Listing by Pin Number (Sheet 9 of 14) Pin No. Pin Name Signal Buffer Type Direction Table 4-2. Pin Listing by Pin Number (Sheet 10 of 14) Pin No.
Pin Listing Table 4-2. Pin Listing by Pin Number (Sheet 11 of 14) Pin No. Signal Buffer Type Direction Pin No.
Pin Listing Table 4-2. Pin Listing by Pin Number (Sheet 13 of 14) Pin No. Pin Name Signal Buffer Type Table 4-2. Pin Listing by Pin Number (Sheet 14 of 14) Direction Pin No.
Pin Listing 86 Document Number: 318080-002
Signal Definitions 5 Signal Definitions 5.1 Signal Definitions. Table 5-1. Signal Definitions (Sheet 1 of 8) Name A[39:3]# Type Description Notes 40 I/O A[39:3]# (Address) define a 2 -byte physical memory address space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction. In subphase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of all agents on the Intel® Xeon® Processor 7200 Series and 7300 Series FSB.
Signal Definitions Table 5-1. Name Signal Definitions (Sheet 2 of 8) Type Description BINIT# I/O BINIT# (Bus Initialization) may be observed and driven by all processor FSB agents and if used, must connect the appropriate pins of all such agents. If the BINIT# driver is enabled during power on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future operation. If BINIT# observation is enabled during power-on configuration (see Section 7.
Signal Definitions Table 5-1. Name D[63:0]# Signal Definitions (Sheet 3 of 8) Type Description I/O D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor FSB agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals, and will thus be driven four times in a common clock period.
Signal Definitions Table 5-1. Signal Definitions (Sheet 4 of 8) Name DSTBN[3:0]# DSTBP[3:0]# Type I/O I/O Description Notes Data strobe used to latch in D[63:0]#. Signals Associated Strobes D[15:0]#, DBI0# DSTBN0# D[31:16]#, DBI1# DSTBN1# D[47:32]#, DBI2# DSTBN2# D[63:48]#, DBI3# DSTBN3# Data strobe used to latch in D[63:0]#.
Signal Definitions Table 5-1. Name Signal Definitions (Sheet 5 of 8) Type Description IGNNE# I IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.
Signal Definitions Table 5-1. Name Signal Definitions (Sheet 6 of 8) Type Description PWRGOOD I PWRGOOD (Power Good) is an input. The processor requires this signal to be a clean indication that all processor clocks and power supplies are stable and within their specifications. “Clean” implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification.
Signal Definitions Table 5-1. Name Signal Definitions (Sheet 7 of 8) Type Description SMI# I SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, processors save the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler. If SMI# is asserted during the deassertion of RESET# the processor will tri-state its outputs. See Section 7.
Signal Definitions Table 5-1. Name Signal Definitions (Sheet 8 of 8) Type Description Notes VID[6:1] O VID[6:1] (Voltage ID) pins are used to support automatic selection of power supply voltages (VCC). These are CMOS signals that are driven by the processor and must be pulled up through a resistor. Conversely, the voltage regulator output must be disabled prior to the voltage supply for these pins becomes invalid. The VID pins are needed to support processor voltage specification variations.
Thermal Specifications 6 Thermal Specifications 6.1 Package Thermal Specifications The Intel® Xeon® Processor 7200 Series and 7300 Series requires a thermal solution to maintain temperatures within its operating limits. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems.
Thermal Specifications Additionally, utilization of a thermal solution that does not meet the Thermal Profile will violate the thermal specifications and may result in permanent damage to the processor. Refer to the Dual-Core Intel® Xeon® Processor 7200 Series and QuadCore Intel® Xeon® Processor 7300 Series Thermal / Mechanical Design Guide for details on system thermal solution design, thermal profiles and environmental considerations.
Thermal Specifications Figure 6-1.Quad-Core Intel® Xeon® E7300 Processor Thermal Profile Therm al Profile 70.0 Temperature (C) 60.0 50.0 T case= 0.263 x Pow er + 45 40.0 30.0 20.0 0 10 20 30 40 50 60 70 80 Pow er(W) Notes: 1. Please refer to Table 6-2 for discrete points that constitute the thermal profile. 2. Implementation of Thermal Profile should result in virtually no TCC activation.
Thermal Specifications Table 6-3. Quad-Core Intel® Xeon® X7350 Processor Thermal Specifications Core Frequency Thermal Design Power (W) Minimum TCASE (°C) Maximum TCASE (°C) 130 5 See Figure 6-2; Table 6-4; Launch to FMB Notes 1, 2, 3, 4, 5, 6 Notes: 1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at specified ICC.
Thermal Specifications Table 6-4. Table 6-5. Quad-Core Intel® Xeon® X7350 Processor Thermal Profile Table Power (W) TCASE_MAX (° C) 0 45.0 10 46.6 20 48.2 30 49.9 40 51.5 50 53.1 60 54.7 70 56.3 80 58.0 90 59.6 100 61.2 110 62.8 120 64.4 130 66.0 Quad-Core Intel® Xeon® L7345 Processor Thermal Specifications Core Frequency Launch to FMB Thermal Design Power (W) Minimum TCASE (°C) Maximum TCASE (°C) 50 5 See Figure 6-3; Table 6-6 Notes 1, 2, 3, 4, 5, 6 Notes: 1.
Thermal Specifications Figure 6-3. Quad-Core Intel® Xeon® L7345 Processor Thermal Profile Thermal P rofile 70.0 65.0 60.0 Temperature (C) 55.0 50.0 Tcase = 0.420 x Pow er + 45 45.0 40.0 35.0 30.0 25.0 20.0 0 5 10 15 20 25 30 35 40 45 50 Pow er (W) Notes: 1. Please refer to Table 6-6 for discrete points that constitute the thermal profile. 2.
Thermal Specifications Table 6-7. Dual-Core Intel® Xeon® Processor 7200 Series Thermal Specifications Core Frequency Thermal Design Power (W) Minimum TCASE (°C) Maximum TCASE (°C) 80 5 See Figure 6-4; Table 6-8; Launch to FMB Notes 1, 2, 3, 4, 5, 6 Notes: 1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at specified ICC.
Thermal Specifications 3. 4. 5. 6. Table 6-8. Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the maximum power that the processor can dissipate. TDP is measured at maximum TCASE. These specifications are based pre-silicon estimates and simulations. These specifications will be updated with characterized data from silicon measurements in a future release of this document. Power specifications are defined at all VIDs found in Table 2-3.
Thermal Specifications Figure 6-5. Case Temperature (TCASE) Measurement Location 19.25 mm [0.76 in] Measure T CASE at this point (geometric center of IHS) 19.25 mm [0.76 in] 53.34 mm FC-mPGA6 Package Thermal grease should cover entire area of IHS Note: Figure is not to scale and is for reference only. 6.2 Processor Thermal Features 6.2.
Thermal Specifications speed dependent and will decrease as processor core frequencies increase. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the TCC goes inactive and clock modulation ceases.
Thermal Specifications to reach the target operating voltage. Each step will be one VID table entry (see Table 2-3). The processor continues to execute instructions during the voltage transition. Operation at the lower voltage reduces the power consumption of the processor. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near its maximum operating temperature.
Thermal Specifications 6.2.5 PROCHOT# Signal An external signal, PROCHOT# (processor hot) is asserted when the temperature of either processor die has reached its factory configured trip point. If Thermal Monitor is enabled (note that Thermal Monitor must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or de-assertion of PROCHOT#.
Thermal Specifications 6.3 Platform Environment Control Interface (PECI) 6.3.1 Introduction PECI offers an interface for thermal monitoring of Intel processor and chipset components. It uses a single wire, thus alleviating routing congestion issues. Figure 6-7 shows an example of the PECI topology in a system with Intel® Xeon® Processor 7200 Series and 7300 Series. PECI uses CRC checking on the host side to ensure reliable transfers between the host and client devices.
Thermal Specifications Figure 6-8. Conceptual Fan Control Diagram For a PECI-Based Platform TCONTROL Setting TCC Activation Temperature Max PECI = 0 Fan Speed (RPM) PECI = -10 Min PECI = -20 Temperature (not intended to depict actual implementation) 6.3.1.2 Processor Thermal Data Sample Rate and Filtering The DTS (Digital Thermal Sensors) provide an improved capability to monitor device hot spots, which inherently leads to more varying temperature readings over short time intervals.
Thermal Specifications Table 6-9. BREQ# signal assertion during power on BREQ0# BREQ1# Asserted Not asserted 00 01 Asserted Asserted 10 11 Not asserted Asserted Not asserted Not asserted AgentID[1:0] Die 0 AgentID[1:0] Die 1 This combination is not supported by the processor Table 6-10 shows how the PECI address is assigned to each of the processors based on the ClusterID[1:0] and AgentID[1] setting at power on. Table 6-10.
Thermal Specifications Prior to a power on RESET# and during RESET# assertion, PECI is not guaranteed to provide reliable thermal data. System designs should implement a default power-on condition that ensures proper processor operation during the time frame when reliable data is not available via PECI. To protect platforms from potential operational or safety issues due to an abnormal condition on PECI, the Host controller should take action to protect the system from possible damaging states.
Features 7 Features 7.1 Power-On Configuration Options Several configuration options can be configured by hardware. The Intel® Xeon® Processor 7200 Series and 7300 Series sample its hardware configuration at reset, on the active-to-inactive transition of RESET#. For specifics on these options, please refer to Table 7-1. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset.
Features processor. The chipset needs to account for a variable number of processors asserting the Stop Grant SBC on the bus before allowing the processor to be transitioned into one of the lower processor power states. 7.2.1 Normal State This is the normal operating state for the processor. 7.2.2 HALT or Extended HALT State The Extended HALT state (C1E) is enabled via the BIOS. The Extended HALT state must be enabled for the processor to remain within its specifications.
Features Table 7-2. Extended HALT Maximum Power Symbol Parameter Min Typ Max Unit Notes PEXTENDED_HALT QuadCore Intel® Xeon® E7300 Processor Extended HALT State Power 34 W 2,3 PEXTENDED_HALT QuadCore Intel® Xeon® X7350 Processor Extended HALT State Power 50 W 2 PEXTENDED_HALT QuadCore Intel® Xeon® L7345 Processor Extended HALT State Power 24 W 1 Notes: 1. The specification is at TCASE = 50°C and nominal VCC.
Features Figure 7-1.
Features While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal state. Only one occurrence of each event will be recognized upon return to the Normal state. While in Stop-Grant state, the processor will process snoops on the front side bus and it will latch interrupts delivered on the front side bus. The PBE# signal can be driven when the processor is in Stop-Grant state.
Features Enhanced Intel SpeedStep Technology creates processor performance states (P-states) or voltage/frequency operating points. P-states are lower power capability states within the Normal state as shown in Figure 7-1. Enhanced Intel SpeedStep Technology enables real-time dynamic switching between frequency and voltage points. It alters the performance of the processor by changing the bus to core frequency ratio and voltage.
Features Figure 7-2. Logical Schematic of SMBus Circuitry SM_VCC VCC SM_EP_A0 SM_EP_A1 SM_EP_A2 SM_WP DATA Processor Information ROM and Scratch EEPROM (1Kbit each) CLK VSS SM_CLK SM_DAT Note: 7.4.1 Actual implementation may vary. This figure is provided to offer a general understanding of the architecture. All SMBus pull-up and pull-down resistors are 10 kΩ and located on the processor.
Features Table 7-3. Memory Device SMBus Addressing Address (Hex) Upper Address1 Device Select R/W bits 7-4 SM_EP_A2 bit 3 SM_EP_A1 bit 2 SM_EP_A0 bit 1 bit 0 A0h/A1h 1010 0 0 0 X A2h/A3h 1010 0 0 1 X A4h/A5h 1010 0 1 0 X A6h/A7h 1010 0 1 1 X A8h/A9h 1010 1 0 0 X AAh/ABh 1010 1 0 1 X ACh/ADh 1010 1 1 0 X AEh/AFh 1010 1 1 1 X Note: 1. This addressing scheme will support up to 8 processors on a single SMBus. 7.4.
Features 7.4.3 Processor Information ROM (PIROM) The lower half (128 bytes) of the SMBus memory component is an electrically programmed read-only memory with information about the processor. This information is permanently write-protected. Table 7-6 shows the data fields and Section 7.4.3 provides the formats of the data fields included in the Processor Information ROM (PIROM).
Features Table 7-6.
Features Table 7-6.
Features 7.4.3.1.2 PISIZE: PIROM Size This location identifies the PIROM size. Writes to this register have no effect. Offset: 01h-02h Bit 15:0 Description PIROM Size The PIROM size provides the size of the device in hex bytes. The MSB is at location 01h, the LSB is at location 02h. 0000h - 007Fh: Reserved 0080h: 128 byte PIROM size 0081- FFFFh: Reserved 7.4.3.1.3 PDA: Processor Data Address This location provides the offset to the Processor Data Section. Writes to this register have no effect.
Features 7.4.3.1.6 PDA: Package Data Address This location provides the offset to the Package Data Section. Writes to this register have no effect. Offset: 06h Bit 7:0 Description Package Data Address Byte pointer to the Package Data section 00h: Package Data section not present 01h - 31h: Reserved 32h: Package Data section pointer value 33h-FFh: Reserved 7.4.3.1.7 PNDA: Part Number Data Address This location provides the offset to the Part Number Data Section. Writes to this register have no effect.
Features 7.4.3.1.9 FDA: Feature Data Address This location provides the offset to the Feature Data Section. Writes to this register have no effect. Offset: 09h Bit 7:0 Description Feature Data Address Byte pointer to the Feature Data section 00h: Feature Data section not present 01h - 73h: Reserved 74h: Feature Data section pointer value 75h-FFh: Reserved 7.4.3.1.10 ODA: Other Data Address This location provides the offset to the Other Data Section. Writes to this register have no effect.
Features 7.4.3.2 Processor Data This section contains two pieces of data: • The S-spec of the part in ASCII format • (1) 2-bit field to declare if the part is a pre-production sample or a production unit 7.4.3.2.1 SNUM: S-Spec Number This location provides the S-SPec number of the processor. The S-spec field is six ASCII characters wide and is programmed with the same S-spec value as marked on the processor.
Features 7.4.3.2.2 SAMPROD: Sample/Production This location contains the sample/production field, which is a two-bit field and is LSB aligned. All S-spec material will use a value of 01b. All other values are reserved. Writes to this register have no effect. Example: A processor with an Sxxxx mark (production unit) will use 01h at offset 14h.
Features Offset: 16h-19h Bit Description 31:30 Reserved 00b-11b: Reserved 29:21 Extended Family 00h-0Fh: Extended Family 21:18 Extended Model 0h-Fh: Extended Model 17:16 Reserved 00b-11b: Reserved 15:14 Processor Type 00b-11b: Processor Type 13:10 Processor Family 0h-Fh: Processor Family 9:6 Processor Model 0h-Fh: Processor Model 5:2 Processor Stepping 0h-Fh: Processor Stepping 1:0 Reserved 00b-11b: Reserved 7.4.3.3.
Features 7.4.3.3.3 MPSUP: Multiprocessor Support This location contains 2 bits for representing the supported number of physical processors on the bus. These two bits are MSB aligned where 00b equates to singleprocessor operation, 01b is a dual-processor operation, and 11b represents multiprocessor operation. The Intel® Xeon® Processor 7200 Series and 7300 Series is an MP processor. The remaining six bits in this field are reserved for the future use. Writes to this register have no effect.
Features 7.4.3.3.6 MINV: Minimum Core Voltage This location contains the minimum Processor Core voltage. This field, rounded to the next thousandth, is in mV and is reflected in hex. The minimum VCC reflected in this field is the minimum allowable voltage assuming the FMB maximum current draw. Writes to this register have no effect. Note: The minimum core voltage value in offset 21 - 22h is a single value that assumes the FMB maximum current draw.
Features 7.4.3.4.1 RES3: Reserved 3 These locations are reserved. Writes to this register have no effect. Offset: 25h-26h Bit 15:0 Description RESERVED 3 0000h-FFFFh: Reserved 7.4.3.4.2 L2SIZE: L2 Cache Size This location contains the size of the level two cache in kilobytes. Writes to this register have no effect. Example: The Intel® Xeon® Processor 7200 Series and 7300 Series has a 2x4MB (8192 KB) L2 cache total. Thus, offset 27 - 28h would contain 2000h.
Features 7.4.3.4.5 MINV: Minimum Cache Voltage This location contains the minimum Cache voltage. This field, rounded to the next thousandth, is in mV and is reflected in hex. The minimum VCACHE reflected in this field is the minimum allowable voltage assuming the FMB maximum current draw for two processors. Writes to this register have no effect. Example: The Intel® Xeon® Processor 7200 Series and 7300 Series does not utilize a Cache VID. Offset 2D - 2Eh will contain 0000h (0 decimal).
Features Offset: 32h-35h Bit 7:0 Description Character 4 ASCII character or 20h 00h-0FFh: ASCII character 15:8 Character 3 ASCII character 00h-0FFh: ASCII character 23:16 Character 2 ASCII character 00h-0FFh: ASCII character 31:24 Character 1 ASCII character 00h-0FFh: ASCII character 7.4.3.5.2 RES5: Reserved 5 This location is reserved. Writes to this register have no effect. Offset: 36h Bit 7:0 Description RESERVED 5 00h-FFh: Reserved 7.4.3.5.
Features Offset: 38h-3Eh Bit 7:0 Description Character 7 ASCII character or 20h 00h-0FFh: ASCII character 15:8 Character 6 ASCII character or 20h 00h-0FFh: ASCII character 23:16 Character 5 ASCII character or 20h 00h-0FFh: ASCII character 31:24 Character 4 ASCII character 00h-0FFh: ASCII character 39:32 Character 3 ASCII character 00h-0FFh: ASCII character 47:40 Character 2 ASCII character 00h-0FFh: ASCII character 4F:48 Character 1 ASCII character 00h-0FFh: ASCII character 7.4.3.6.
Features 7.4.3.6.4 RES7: Reserved 7 This location is reserved. Writes to this register have no effect. Offset: 55h-6Eh Bit 207:0 7.4.3.6.5 Description RESERVED 7 PNDCKS: Part Number Data Checksum This location provides the checksum of the Part Number Data Section. Writes to this register have no effect. Offset: 6F Bit 7:0 Description Part Number Data Checksum One Byte Checksum of the Part Number Section 00h- FFh: See Section 7.4.4 for calculation of the value 7.4.3.
Features 7.4.3.8 Feature Data This section provides information on key features that the platform may need to understand without powering on the processor. 7.4.3.8.1 Processor Core Feature Flags This location contains a copy of results in EDX[31:0] from Function 1 of the CPUID instruction. These details provide instruction and feature support by product family. A decode of these bits is found in the AP-485 Intel® Processor Identification and CPUID Instruction application note.
Features Offset: 79h Bit 7.4.3.8.4 Description 7:2 Number of cores 1:0 Number of threads per core Additional Processor Feature Flags This location contains additional feature information for the processor. This field is defined as follows: Writes to this register have no effect.
Features Offset: 7Fh Bit 7:0 Description Feature Data Checksum One Byte Checksum of the Feature Data Section 00h- FFh: See Section 7.4.4 for calculation of the value 7.4.4 Checksums The PIROM includes multiple checksums. Table 7-7 includes the checksum values for each section defined in the 128 byte ROM. Table 7-7. 128 Byte ROM Checksum Values Section Checksum Address Header 0Dh Processor Data 15h Processor Core Data 24h Cache Data 31h Package Data 37h Part Number Data 6Fh Thermal Ref.
Features 138 Document Number: 318080-002
Boxed Processor Specifications 8 Boxed Processor Specifications 8.1 Introduction The Intel® Xeon® Processor 7200 Series and 7300 Series is also offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed processor will not be supplied with a cooling solution. Future revisions may have solutions that differ from those discussed here. 8.
Boxed Processor Specifications 140 Document Number: 318080-002
Debug Tools Specifications 9 Debug Tools Specifications 9.1 Debug Port System Requirements The Intel® Xeon® Processor 7200 Series and 7300 Series debug port is the command and control interface for the In-Target Probe (ITP) debugger. The ITP enables run-time control of the processors for system debug. The debug port, which is connected to the FSB, is a combination of the system JTAG and execution signals.
Debug Tools Specifications 9.2.2 Electrical Considerations The LAI will also affect the electrical performance of the FSB, therefore it is critical to obtain electrical load models from each of the logic analyzer vendors to be able to run system level simulations to prove that their tool will work in the system. Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution they provide.
