User Manual

Thermal Specifications
140 Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 1
command responses are prepended with a completion code that includes additional
pass/fail status information. Refer to Section 7.3.4.2 for details regarding completion
codes.
Note that the 4-byte PCI configuration address defined above is sent in standard PECI
ordering with LSB first and MSB last.
7.3.2.4.2 Supported Responses
The typical client response is a passing FCS, a passing Completion Code (CC) and valid
Data. Under some conditions, the client’s response will indicate a failure.
7.3.2.5 PCIConfigWr()
The PCIConfigWr() command gives sideband write access to the PCI configuration
space maintained in the processor. The exact listing of supported devices, functions is
defined below in Table 7-23. PECI originators may conduct a device/function/register
enumeration sweep of this space by issuing reads in the same manner that BIOS
would.
Figure 7-21. PCIConfigRd()
Byte #
Byte
Definition
0
Client Address
1
Write Length
0x05
2
Read Length
{0x02,0x03,0x05}
8
FCS
3
Cmd Code
0xc1
9
Completion
Code
10
Data 0 ...
8+RL
Data N
9+RL
FCS
4 5 6 7
LSB MSBPCI Configuration Address
Table 7-22. PCIConfigRd() Response Definition
Response Meaning
Abort FCS Illegal command formatting (mismatched RL/WL/Command Code)
CC: 0x40 Command passed, data is valid
CC: 0x80 Error causing a response timeout. Either due to a rare, internal timing condition or a
processor RESET or processor S1 state. Retry is appropriate outside of the RESET or
S1 states.
Table 7-23. PCIConfigWr() Device/Function Support (Sheet 1 of 2)
Writable
Description
Device Function
21Intel®
QuickPath Interconnect Link 0 Intel IBIST
25Intel®
QuickPath Interconnect Link 1 Intel IBIST
3 4 Memory Controller Intel IBIST
1