Front cover Draft Document for Review April 7, 2004 6:15 pm SG24-6947-01 IBM eServer zSeries 990 Technical Guide Structure and design - A scalable server for an on demand world Processor Unit, Memory, Multiple Logical Channel Subsystems Capacity upgrade options Bill White Mario Almeida Dick Jorna ibm.
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6947edno.fm Draft Document for Review April 7, 2004 6:15 pm Note: Before using this information and the product it supports, read the information in “Notices” on page ix. Second Edition (April 2004) This edition applies to the IBM ^zSeries 990 server at hardware Driver Level 55. This document created or updated on April 7, 2004. © Copyright International Business Machines Corporation 2004. All rights reserved. Note to U.S.
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Draft Document for Review April 7, 2004 6:15 pm 6947TOC.fm Contents Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .x Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6947TOC.fm Draft Document for Review April 7, 2004 6:15 pm 2.2.8 Storage operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.9 Reserved storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.10 LPAR storage granularity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.11 LPAR Dynamic Storage Reconfiguration (DSR) . . . . . . . . . . . . . . . . . . . . . .
Draft Document for Review April 7, 2004 6:15 pm 6947TOC.fm 6.2 z/OS software support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.1 Compatibility support for z/OS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.2 Exploitation support for z/OS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.3 HCD support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6947TOC.fm Draft Document for Review April 7, 2004 6:15 pm 8.5 Capacity BackUp (CBU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6 Nondisruptive upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6.1 Upgrade scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6.2 Planning for nondisruptive upgrades . . . . . . . . . . . . . . . . . . . . . . . . .
Draft Document for Review April 7, 2004 6:15 pm 6947spec.fm Notices This information was developed for products and services offered in the U.S.A. IBM may not offer the products, services, or features discussed in this document in other countries. Consult your local IBM representative for information on the products and services currently available in your area.
6947spec.fm Draft Document for Review April 7, 2004 6:15 pm Trademarks The following terms are trademarks of the International Business Machines Corporation in the United States, other countries, or both: Balance® CICS® DB2® DFS™ DRDA® ECKD™ Enterprise Storage Server® Enterprise Systems Architecture/390® ES/9000® ESCON® Eserver® FICON® FlashCopy® GDDM® GDPS® Geographically Dispersed Parallel Sysplex™ HiperSockets™ HyperSwap™ ibm.
Draft Document for Review April 7, 2004 6:15 pm 6947pref.fm Preface The IBM Eserver zSeries® 990 scalable server provides major extensions to existing zSeries architecture and capabilities. The concept of Logical Channel Subsystems is added, and the maximum number of processor units and logical partitions is increased. These extensions provide the base for much larger zSeries servers.
6947pref.fm Draft Document for Review April 7, 2004 6:15 pm Become a published author Join us for a two- to six-week residency program! Help write an IBM Redbook dealing with specific products or solutions, while getting hands-on experience with leading-edge technologies. You'll team with IBM technical professionals, Business Partners and/or customers. Your efforts will help increase product acceptance and customer satisfaction.
Draft Document for Review April 7, 2004 6:15 pm 6947ch01.fm 1 Chapter 1. IBM zSeries 990 overview This chapter gives a high-level view of the IBM Eserver zSeries 990. All the topics mentioned in this chapter are discussed in greater detail later in this book. The legacy of zSeries goes back more than 40 years. Actually, on April 7th, 2004 it was 40 years ago that IBM introduced it’s S/360.
6947ch01.fm Draft Document for Review April 7, 2004 6:15 pm The z990 servers can be configured in numerous ways to offer outstanding flexibility in deployment of e-business on demand™ solutions. Each z990 server can operate independently, or as part of a Parallel Sysplex cluster of servers. In addition to z/OS, the z990 can host tens to hundreds of Linux images running identical or different applications in parallel, based on z/VM® virtualization technology.
6947ch01.fm Draft Document for Review April 7, 2004 6:15 pm 1.1 Introduction The z990 further extends and integrates key platform characteristics. Dynamic and flexible partitioning, resource management in mixed and unpredictable workload environments, availability, scalability, clustering, and systems management with emerging e-business on demand application technologies (for example, WebSphere®, Java, Linux).
6947ch01.fm Draft Document for Review April 7, 2004 6:15 pm 4-port ESCON cards OSA-2 cards OSA-Express ATM cards Pre-FICON Express cards PCICC cards The logical partitioning facility, PR/SM, provides the ability to configure and operate as many as 30 logical partitions. PR/SM manages all the installed and enabled resources (processors, memory) of the installed books as a single large SMP.
6947ch01.fm Draft Document for Review April 7, 2004 6:15 pm change the PU characterization of the server they are upgrading. In addition, customers who are consolidating may not be increasing total capacity, and/or they may wish to take advantage of the multiple Logical Channel Subsystems offered. z990-to-z990 model upgrades and feature adds may be completed concurrently. Model downgrades There are no model downgrades offered. Customers may purchase unassigned CPs or IFLs for future use.
6947ch01.fm Draft Document for Review April 7, 2004 6:15 pm A System Assist Processor (SAP) An Internal Coupling Facility (ICF) An Integrated Facility for Linux (IFL) A zSeries Application Assist Processor (zAAP) The number of CPs and SAPs assigned for particular general purpose models depends on the configuration. The number of spare PUs is dependent on how many CPs, SAPs, ICFs, zAAPs, and IFLs are present in a configuration. 1.3.2 Memory The minimum system memory on any model is 16 GB.
6947ch01.fm Draft Document for Review April 7, 2004 6:15 pm 1.3.5 Physical Channel IDs (PCHIDs) and CHPID Mapping Tool A z990 can have up to 1024 physical channels, or PCHIDs. In order for an operating system to make use of that PCHID, it must be mapped to a CHPID within the IOCDs. Each CHPID is uniquely defined with an LCSS and mapped to an installed PCHID. A PCHID is eligible for mapping to any CHPID in any LCSS.
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6947ch01.fm Draft Document for Review April 7, 2004 6:15 pm zSeries supports FCP channels, switches and FCP/SCSI devices with full fabric connectivity under Linux on zSeries. Support for FCP devices means that z990 servers will be capable of attaching to select FCP/SCSI devices, and may access these devices from Linux on zSeries.
6947ch01.fm Draft Document for Review April 7, 2004 6:15 pm IBM TotalStorage SAN Switches 2109-F16, S16, and S08 IBM TotalStorage Director 2109-M12 FICON Cascaded Directors have the added value of ensuring high integrity connectivity. Transmission data checking, link incidence reporting, and error checking are integral to the FICON architecture, thus providing a true enterprise fabric. For more information on Cascaded Directors, consult the I/O Connectivity Web page: http://www.ibm.
6947ch01.fm Draft Document for Review April 7, 2004 6:15 pm (when operating at 1000 Mbps (1 Gbps)) features by offloading checksum processing to OSA-Express (in QDIO mode, CHPID type OSD)) for most IPv4 packets. This support is available with z/OS V1R5 and later as well as Linux on zSeries. Token Ring The OSA-Express Token Ring feature has two independent ports, each supporting attachment to either a 4 Mbps, 16 Mbps, or 100 Mbps Token Ring Local Area Network (LAN).
6947ch01.fm Draft Document for Review April 7, 2004 6:15 pm These cryptographic functions are implemented in every PU; the affinity problem of pre-z990 systems is eliminated. The Crypto Assist Architecture includes DES and T-DES data en/decryption, MAC message authentication, and SHA-1 secure hashing. These functions are directly available to application programs (zSeries Architecture instructions).
6947ch01.fm Draft Document for Review April 7, 2004 6:15 pm ICB-2 (Integrated Cluster Bus 2) The Integrated Cluster Bus-2 (ICB-2) link is a member of the family of Coupling Link options available on z990. Like the ISC-3 link, it is used by coupled systems to pass information back and forth over high speed links in a Parallel Sysplex environment. ICB-2 or ISC-3 links are used to connect 9672 G5/G6 to z990 servers.
6947ch01.fm Draft Document for Review April 7, 2004 6:15 pm For those CF structures that support use of System-Managed CF Structure Duplexing, customers have the ability to dynamically enable or disable, selectively by structure, the use of System-Managed CF Structure Duplexing.
6947ch01.fm Draft Document for Review April 7, 2004 6:15 pm The z990 server implements two fully redundant interfaces, known as the Power Service Control Network (PSCN), between the two Support Elements and the CPC. Error detection and automatic switch-over between the two redundant Support Elements provides enhanced reliability and availability. 1.3.12 Concurrent upgrades The z990 servers have concurrent upgrade capability via the Capacity Upgrade on Demand (CUoD) function.
6947ch01.fm Draft Document for Review April 7, 2004 6:15 pm Note: The CBU capability can coexist with On/Off CoD enablement. Both On/Off CoD and CBU LIC-CC can be installed on a z990 server, but the On/Off CoD activation and CBU activation are mutually exclusive. The proper number of CBU features, one for each “backup” CP, must be ordered and installed to restore the required capacity under disaster situations. The CBU activation can be tested for disaster/recovery procedures validation and testing.
6947ch01.fm Draft Document for Review April 7, 2004 6:15 pm http://www.ibm.com/servers/eserver/zseries/library/swpriceinfo 1.3.14 Reliability, Availability, Serviceability (RAS) The z990 RAS strategy is a building-block approach developed to meet the customer's stringent requirements of achieving Continuous Reliable Operation (CRO). Those building blocks are: Error Prevention, Error Detection, Recovery, Problem Determination, Service Structure, Change Management, and Measurement and Analysis.
6947ch01.fm Draft Document for Review April 7, 2004 6:15 pm ERP Transaction Transaction The z990 Generation: Appl.+DB Business appl.
6947ch01.fm Draft Document for Review April 7, 2004 6:15 pm Linux on zSeries (and Linux for S/390) Linux on zSeries offers a number of advantages compared to other platforms. First, it puts the Linux applications close to the enterprise data and applications, thus reducing the chance for bottlenecks. And since a Linux application runs in its own partition, with its own dedicated resources, it does not impact the availability or security of the rest of the system.
6947ch01.fm Draft Document for Review April 7, 2004 6:15 pm Note: z/OS 1.1 is not supported on z990 nor on any zSeries server participating in a sysplex that includes a z990 server. Linux Linux for S/390 is available in 31-bit mode and will support Exploitation mode. Linux on zSeries is available in 64-bit mode and will support Exploitation mode. z/VM All versions of z/VM support both 31-bit and 64-bit mode. z/VM 4.4, and z/VM 5.
6947ch01.fm Draft Document for Review April 7, 2004 6:15 pm 1.3.17 Summary On a physical resource level, z990 is a S/390 architecture server with a maximum of 48 PUs and 256 GBytes of main memory structured in a four-book configuration. The books are interconnected by a high speed memory coherence ring, thus building a large and very efficient SMP. The I/O adapters are housed in three I/O cages, and provide a maximum of 1024 (maximum 256 per LCSS) channel ports. The z900 to z990 is a “Frame Roll” MES.
Draft Document for Review April 7, 2004 6:15 pm 6947ch02.fm 2 Chapter 2. System structure and design This chapter introduces the IBM eServer™ zSeries 990 system structure. Significant functions and features are described, along with their characteristics and options. The goal is to explain how the z990 is structured, what its main components are and how these components interconnect from a physical and logical point of view.
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm 2.1 System structure The z990 structure and design are the result of the continuous evolution of S/390 and zSeries since CMOS servers were introduced in 1994. The structure and design have been continuously improved, adding more capacity, performance, functionality, and connectivity.
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm Power Each book get its power from two Distributed Converter Assemblies (DCA) that reside on the opposite side of the CEC board. The DCAs provide the required power for the book. Each book is supported by two DCAs. The N+1 power supply design means that there is more DCA capacity than is required for the book. If one DCA fails, the power requirement for a book can still be satisfied from the remaining DCA.
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm 2. The Motor Scroll Assembly (MSA) 3. The Motor Drive Assembly (MDA) – MDAs are found throughout the frames to provide air cooling where required. They are located at the bottom front of each cage, and in between the CEC cage and I/O cage 1 in combination with the MSAs. Hybrid cooling system The z990 has a hybrid cooling system that is a breakthrough in lowering power consumption.
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm The IBM 2084 model D32 has four books (D) with 12 PUs in each book for a total of 48 PUs, of which 32 can be characterized by the customer. The remaining PUs are eight system assist processors (SAPs) and eight spares, two of each in each book. The last two digits of the model number reflect the maximum number of PUs that can be characterized for installation use. The PUs can be characterized as CPs, IFLs, ICFs, zAAPs or additional SAPs.
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm A book may have more memory installed than enabled. The excess amount of memory can be installed by a Licensed Internal Code code load (sometimes called “dial-a-Gig”), when required by the installation. On initial installation, the amount of physical memory in a given model is nearest to the smallest possible size. Memory upgrades are satisfied from already installed unused memory capacity until exhausted.
Draft Document for Review April 7, 2004 6:15 pm 6947ch02.fm When activated, a logical partition can use memory resources located in any book. No matter in which book the memory resides, a logical partition has access to that memory if so allocated. Despite the book structure, the z990 is a Symmetric Multi-Processor (SMP). Each memory card has two memory ports, and each port can access 128 bits (16 bytes).
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm Book 3 Book 0 Book 1 Book 2 Figure 2-4 Concentric ring structure A memory-coherent director optimizes ring traffic and filters out cache traffic by not looking on the ring for cache hits in other books if it is certain that the resources for a given logical partition exist in the same book. The Level 2 (L2) cache is implemented on four cache (SD) chips. Each SD chip holds 8 MB, resulting in a 32 MB L2 cache per book.
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6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm MBA LEDs STI connectors FGA MBA SEEP VHDM 6-ROW (720 Signal Pins ) STI STI STI STI STI STI STI STI MBA STI STI STI STI MBA card Book front view Figure 2-8 STI connectors and MBA card Each book has three MBAs, each driving four STIs, resulting in 12 STIs per book. All 12 STIs per book have a data rate of 2.0 GB/sec, resulting in a sustained bandwidth of 24 GB/sec per book.
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm availability purposes. Reports from the CHPID Mapping tool can help you validate your I/O configuration. Book upgrades with substantial additions of I/O cards may require the additional STIs to be used. In that case it is good practice to consider rebalancing the STI configuration (FC 2400). More information about I/O balancing, see “Balancing I/O connections” on page 79.
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm A frame As shown in Figure 2-9, the main components in the A-frame are: 1. Two Internal Battery Features (IBFs) The optional Internal Battery Feature provides the function of a local uninterrupted power source. The IBF further enhances the robustness of the power design, increasing Power Line Disturbance immunity. It provides battery power to preserve processor data in case of a loss of power on both of the AC feeders from the utility company.
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm – 1000BASE-T Ethernet – High Speed Token Ring PCI Cryptographic Accelerator (PCICA, 2 processors per feature). PCIX Cryptographic Coprocessor (PCIXCC, 1 processor per feature). The STI-2 card provides two output ports to support the ICB-2 links. The STI-3 card converts the output into two 333 MB/sec links The STI-3 card provides two output ports to support the ICB-3 links. The STI-3 card converts the output into two 1GB/sec links.
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm MSC PU PU MSC PU SD SD PU PU SC SD PU PU SD PU CLK Figure 2-11 MCM chip layout 2.1.8 The PU, SC, and SD chips All chips use CMOS 9SG technology, except for the clock chip (CMOS 8S). CMOS 9SG is state-of-the-art microprocessor technology based on eight-layer Copper Interconnections and Silicon-On Insulator technologies. The chip’s lithography line width is 0.125 micron. The eight PU chips come in two versions.
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm The dual-core PU chips share the path to the SC chip (L2 control) and the clock chip (CLK). 2.1.9 Summary Table 2-2 summarizes all aspects of the z990 system structure.
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm design has been adapted to the changing requirements dictated by the shift towards e-business applications that customers are becoming more and more dependent on. The z990, with its superscalar processor and flexible configuration options, is the next implementation to address this ever-changing environment. 2.2.
Draft Document for Review April 7, 2004 6:15 pm 6947ch02.fm The following sections describe the z990 system structure, showing a logical representation of the data flow from PUs, L2 cache, memory cards, and MBAs, which connect I/O through Self-Timed Interconnect (STI). 2.2.2 Book design A book has 12 PUs, two memory cards and three MBAs connected by the System Controller (SC). Each memory card has a capacity of 8 GB, 16 GB or 32 GB, resulting in up to 64 GB of memory Level 3 (L3) per book.
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Draft Document for Review April 7, 2004 6:15 pm 6947ch02.fm Data transfer between the CEC memory and attached I/O devices or CPCs is done through the Memory Bus Adapter. The physical path includes the Channel card (except for STI connected CPCs), the Self-Timed Interconnect bus and possibly a STI extender card, the Storage Control, and the Storage Data chips. More detailed information about I/O connectivity and channel types can be found in “I/O subsystem” on page 71.
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm under way to update the C++ compiler and Java Virtual Machine for z/OS to better exploit the z990 microprocessor superscalar implementation. The intent is improve the performance advantage for e-business workloads such as WebSphere and Java applications. By the time the Java Virtual Machine (JVM) and compilers are available, more improvement in the throughput of the superscalar processor is expected.
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm From L2 Cache From E-Unit I-Unit From E-Unit B-Unit I-Unit L1 Cache E-Unit To L2 Cache E-Unit Processing Unit (PU) Dual processor I-Unit E-Unit Floating Point function Simple yet complete error detection mechanism Data flow - parity checked Address paths - parity checked L1 Cache - parity checked Processor logic (I - E - F) Duplicated, then compared output.
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm Processor Branch History Table (BHT) The Branch History Table (BHT) implementation on processors has a key performance improvement effect. The BHT was originally introduced on the IBM ES/9000® 9021 in 1990 and has been improved ever since. The z990 server BHT offers significant branch performance benefits. The BHT allows each CP to take instruction branches based on a stored BHT, which improves processing times for calculation routines.
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm IEEE Floating Point The inclusion of the IEEE Standard for Binary Floating Point Arithmetic (IEEE 754-1985) in S/390 was made to further enhance the value of this platform for this type of calculation. The initial implementation had 121 floating-point instructions over prior S/390 CMOS models (Hexadecimal Floating Point had 54 instructions).
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm and SOAP technologies are used. The High Level Assembler will be the first to support the Extended Translation Facility instructions. 2.2.4 Processor unit functions One of the key components of the z990 server is the processor unit (PU). This is the microprocessor chip where instructions are executed and the related data resides. The instructions and the data are stored in the PU’s high-speed buffer, called the Level 1 cache.
Draft Document for Review April 7, 2004 6:15 pm 6947ch02.fm An Internal Coupling Facility (ICF) The number of CPs, IFLs, ICFs, zAAPs, or SAPs assigned to particular models depends on the configuration. The z990 12-PU MCMs have two SAPs as standard. The standard number of SAPs in a model A08 is two; there are four in a B16; six in a C24; and eight in a D32. Optional additional SAPs may be purchased, up to two per book. The z990 12-PU MCMs have two spares PUs as standard.
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm Within the limit of all non-characterized PUs available in the installed configuration, IFLs can be concurrently added to an existing configuration via Capacity Upgrade on Demand (CUoD), Customer Initiated Upgrade (CIU), On/Off Capacity on Demand (On/Off CoD), but IFLs cannot be assigned via CBU. For more information about CUoD, CIU or On/Off CoD see Chapter 8, “Capacity upgrades” on page 185.
Draft Document for Review April 7, 2004 6:15 pm 6947ch02.fm zSeries Application Assist Processors The zSeries Application Assist Processor (zAAP) is a PU that is used exclusively for running Java application workloads under z/OS. One CP must be installed with or prior to any zAAP are installed. The number of zAAPs in a machine cannot exceed the number of CPs plus unassigned CPs in that machine.
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm Java application code can either run on a CP or an zAAP. The user can manage the use of CPs such that Java application code runs only on a CP, only on an zAAP, or on both when zAAPs are busy. For the logical flow of a Java code execution on a zAAP, see Figure 6-3 on page 139. Software support zAAPs do not change the software model number of the z990 server.
Draft Document for Review April 7, 2004 6:15 pm 6947ch02.fm Optionally assignable SAPs Assigned CPs may be optionally reassigned as SAPs instead of CPs, using the Reset Profile on the Hardware Management Console (HMC). This reassignment increases the capacity of the Channel Subsystem to perform I/O operations, usually for some specific workloads or I/O intensive testing environments.
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm Additional SAPs are characterized first, then CPs, followed by IFLs, ICFs and zAAPs. For performance reasons, CPs for a logical partition are grouped together as much as possible. Having all CPs grouped in as few books as possible limits memory and cache interference to a minimum.
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm Table 2-3 PU chip allocation Core Core 0 - X - 2 - X - 4 - X - 6 - X - 8 9 X Spare A B X Spare C D X SAP E F X SAP Single core Dual core X = CP, IFL, ICF, or zAAP On a single-book configuration, model A08: – When a PU failure occurs on a dual-core chip, the two standard spares PUs are used to recover the failing chip, even though only one of the PUs has failed.
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm Partial Memory Restart In the rare event of a memory card failure, Partial Memory Restart enables the system to be restarted with only part of the original memory. In a one-book system, the failing card will be deactivated, after which the system can be restarted with the memory on the remaining memory card.
47ch02.fm Draft Document for Review April 7, 2004 6:15 pm on page 29. For more information about CUoD for memory, refer to “CUoD for memory” on page 191. Processor memory, even though physically the same, can be configured as both Central storage and Expanded storage. Central storage (CS) Central storage (CS) consists of main storage, addressable by programs, and storage not directly addressable by programs. Non-addressable storage includes the Hardware System Area (HSA).
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm Activation of logical partitions as well as dynamic storage reconfiguration will cause the storage to be assigned to the type needed (CS or ES). This does not require a Power-on Reset. No new software support is required to take advantage of this function. Hardware System Area (HSA) The Hardware System Area (HSA) is a non-addressable storage area that contains the CPC Licensed Internal Code and configuration-dependent control blocks.
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm z990 Mode Image Modes Addressing Modes Operating Systems z/OS Linux on zSeries ESA/390 Mode CPs CPs and zAAPs (z/OS 1.
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm PR/SM enables z990 servers to be initialized for logically partitioned operation, supporting up to 30 logical partitions. Each logical partition can run its own operating system image in any image mode, independently from the other logical partitions. A logical partition can be activated or deactivated at any time, but changing the number of defined logical partitions is disruptive, as it requires a Power-on Reset (POR).
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm Figure 2-16 Logical processor assignment (HMC- Image Profile) On the z990, the sum of defined and reserved logical processors for an ESA/390 mode logical partition is limited to 32. However, z/OS 1.6 and z/VM 5.1 operating systems are planned to support up to 24 processors. For z/OS, the 24 processors limit applies to the sum of CPs and zAAPs logical processors.
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm IOCP is available on z/OS, OS/390, z/VM, VM/ESA, z/VSE, and VSE/ESA operating systems, and as a standalone program on the z990 hardware console. HCD is available on z/OS, z/VM, and OS/390 operating systems. ESCON channels (CHPID type CNC or FCV) can be managed by the Dynamic CHPID Management (DCM) function of the Intelligent Resource Director.
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm Table 2-4 LPAR mode and PU usage LPAR mode ESA/390 PU type Operating systems PUs usage z/Architecture operating systems ESA/390 operating systems Linux CPs DED or CPs SHR z/OS (1.
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm IBM 2084 model B16 - 16 PUs are available for characterization as CPs, IFLs, ICFs, zAAPs (up to 8), or additional SAPs IBM 2084 model C24 - 24 PUs are available for characterization as CPs, IFLs, ICFs, zAAPs (up to 12), or additional SAPs IBM 2084 model D32 - 32 PUs are available for characterization as CPs, IFLs, ICFs, zAAPs (up to 16), or additional SAPs When a z990 order is configured, PUs are selected according to their intended usage.
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm Table 2-5 z990 upgrade paths z990 Models 2084-A08 2084-B16 2084-C24 2084-D32 2084-A08 - X X X 2084-B16 - - X X 2084-C24 - - - X 2084-D32 - - - - Upgrade paths from IBM 2064 models (z900) offer a virtually unrestricted upgrade capability. Upgrades from any z900 to any z990 server are supported (with the exception of the IBM 2064 model 100, which can only can be upgraded to another z900 model).
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm Table 2-6 z990 software models z990 Models Software Models IBM 2084-A08 301 - 308 IBM 2084-B16 301 - 316 IBM 2084-C24 301 - 324 IBM 2084-D32 301 - 332 Note: Software model number 300 is used for IFL or ICF only models. This structure enables a different approach to downgrading the system in cases where a larger system is installed on which, for software charging reasons, temporarily less CP capacity must be assigned.
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm Conversion of feature code 0517 to 0516, for conversion of an unassigned IFL to an IFL Conversion of feature code 0518 to 0516 or 0716, for conversion of an ICF to an IFL or a CP All listed conversions are usually non-disruptive. In exceptional cases the conversion may be disruptive, e.g. when an IBM 2084 model A08 with eight CPs is converted to an all IFL system.
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Draft Document for Review April 7, 2004 6:15 pm 6947ch02.fm Note: The z990 (and the z890) are the last zSeries servers offering Token Ring adapters on the Hardware Management Consoles and Support Elements.Timely planning is advised in preparation of migration to the Ethernet environment. Note: Hardware Management Consoles are to become closed platforms with the next zSeries server and will only support the HMC application.
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6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm Some z/Architecture operating systems, like z/OS, will always change this addressing mode and operate in 64-bit mode. The z/OS Bimodal Migration Accommodation Offering allows for a limited amount of time to run z/OS in 31-bit mode. This offering provides fallback support to 31-bit mode in the event it is required during migration to z/OS in 64-bit mode. Beginning with z/OS V1.
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm z/VM can be configured to use 64-bit addressing and operate in the z/Architecture mode, or to use 31-bit addressing and operate in the ESA/390 architecture mode. 2.2.9 Reserved storage Reserved storage can optionally be defined to a logical partition allowing a non-disruptive image memory upgrade for this partition. Reserved storage can be defined to both central and expanded storage, and to any image mode except the Coupling Facility mode.
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm Remember that logical partitions are currently limited to a maximum size of 128 GB of storage. 2.2.11 LPAR Dynamic Storage Reconfiguration (DSR) Dynamic Storage Reconfiguration (DSR) on z990 servers allows an operating system running in a logical partition to add non-disruptively its reserved storage amount to its configuration, if any unused storage exists.
6947ch02.fm Draft Document for Review April 7, 2004 6:15 pm For detailed information about the I/O system structure, see“I/O system structure” on page 73. 2.2.13 Channel Subsystem The representation of all connections and devices is called the Channel Subsystem. The z990 introduces the concept of Multiple Logical Channel Subsystems. Up to two Logical Channel Subsystems (LCSSs) can be defined in the IOCDS, and this allows for the definition of up to 512 channels.
Draft Document for Review April 7, 2004 6:15 pm 6947ch03.fm 3 Chapter 3. I/O system structure This chapter describes the I/O system structure, the connectivity and the cryptographic options available on the zSeries 990 server. The z990 server I/O and cryptographic features are also discussed, including configuration options for each feature.
6947ch03.fm Draft Document for Review April 7, 2004 6:15 pm 3.1 Overview The z990 I/O system design provides great flexibility, high availability and performance, allowing: High bandwidth The z990 I/O system can handle up to 96 GB/sec, which is four times the z900 server’s bandwidth. Individual channels can have up to 2 Gb/sec and individual Coupling Facility links up to 2 GB/sec data rates.
6947ch03.fm Draft Document for Review April 7, 2004 6:15 pm The following cryptographic feature cards are supported in the zSeries 990 server: Up to 4 Peripheral Component Interconnect X Cryptographic Coprocessor (PCIXCC) Up to 12 Peripheral Component Interconnect Cryptographic Accelerator (PCICA) All z990 servers have two frames. The A frame holds the CEC cage on top and one I/O cage on the bottom.
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6947ch03.fm Draft Document for Review April 7, 2004 6:15 pm Domain I/O slots in domain 5 20, 22, 25, 27 6 29, 30, 31, 32 Each eSTI-M card is connected to an STI jack located in a book’s Memory Bus Adapter (MBA) via an STI cable. As each eSTI-M card requires one STI, up to seven STIs are required to support one I/O cage. A fully populated three-I/O cage system requires 21 STIs.
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Draft Document for Review April 7, 2004 6:15 pm 6947ch03.fm Depending on the number of I/O slots plugged into the cage, there may be from one to seven eSTI-M cards plugged into a z990 I/O cage. The eSTI-M card can be installed or replaced concurrently. STI-2 Extender card The STI-2 Extender card (Feature Code 3992) takes the 2 GB/sec link from an MBA’s STI and creates two secondary 333 MB/sec STI links, which are used to connect ICB-2 links.
6947ch03.fm Draft Document for Review April 7, 2004 6:15 pm STI links balancing across books and MBAs Figure 3-4 on page 80 shows a 2084-B16 server’s initial configuration example with two fully populated I/O cages (7 I/O domains on each one). 2084-B16 CEC Cage Book 0 Book 1 MBAMBAMBAMBAMBAMBA 0 1 2 0 1 2 STIs STI Links I/O Cards I/O Cage 1 I/O Cage 2 I/O Domains Figure 3-4 2084-B16 initial configuration example The 2084-B16 server has two books in the CEC cage.
6947ch03.fm Draft Document for Review April 7, 2004 6:15 pm 2084-D32 CEC Cage Book 3 Book 0 Book 1 Book 2 MBA MBA MBA MBA MBA MBA MBA MBA MBA MBA MBA MBA 1 2 0 1 2 0 1 2 0 1 2 0 STIs STI Links I/O Cards I/O Cage 1 I/O Cage 2 I/O Domains Figure 3-5 2084-B16-to-D32 upgrade example This upgrade adds, concurrently, two more books in the CEC cage, and the standard upgrade configuration will not change the STI links’ original distribution and connections.
6947ch03.fm Draft Document for Review April 7, 2004 6:15 pm 2084-D32 CEC Cage Book 3 Book 0 Book 1 Book 2 MBA MBA MBA MBA MBA MBA MBA MBA MBA MBA MBA MBA 0 1 2 0 1 2 0 1 2 0 1 2 STIs STI Links I/O Cards I/O Cage 1 I/O Cage 2 I/O Domains Figure 3-6 Upgrade example with the STI Rebalance feature (FC 2400) Now you can see that the required number of STI links is spread across all books MBAs, including the two newly installed books 2 and 3, and redistributed across the existing I/O cages.
6947ch03.fm Draft Document for Review April 7, 2004 6:15 pm possible to see any places where a control unit, or group of control units, have single points of failure (SPOF); in this case, books and MBAs are of interest. For the next step, use the CFReport for FC2400 along with the same IOCP statements and repeat the availability option in the CMT. This will potentially show a different set of SPOFs.
6947ch03.fm Draft Document for Review April 7, 2004 6:15 pm The z990 CHPID Mapping Tool (CMT) can help you to plan for the best I/O port selection for high availability purposes. For more information about the z990 CMT, see “IBM z990 CHPID Mapping Tool (CMT)” on page 116. 3.3 I/O and cryptographic feature cards I/O cards have the I/O port(s) to connect the z990 server to external devices, networks, or to other servers.
6947ch03.fm Draft Document for Review April 7, 2004 6:15 pm – Optica Technologies 34600 FXBT ESCON Converter. For more information, check the Optica Technologies Web site: http://www.opticatech.com/34600.asp ESCON 4-port channel cards (z900 FC 2313) ESCON 4-port channel cards are not offered as a new build option and are replaced with new 16-Port ESCON cards (FC 2323) during an upgrade from z900. The 16-Port ESCON card has MT-RJ connectors.
6947ch03.fm Draft Document for Review April 7, 2004 6:15 pm Cryptographic Coprocessor Facility used by known applications have also been implemented in the PCIXCC feature. 3.3.3 Physical Channel IDs (PCHIDs) A Physical Channel ID (PCHID) is the number assigned to a port of an I/O or cryptographic card. Each enabled port has its own PCHID number, which is based on its I/O slot location in the I/O cage (except for ESCON sparing).
6947ch03.fm Draft Document for Review April 7, 2004 6:15 pm Machine: 2084-A08 NEW1 ----------------------------------------------------------Book/Jack/MBA Cage Slot F/C PCHID/Ports Comment 0/J.00/0 A01B D101 0218 100/J00 101/J01 0/J.08/2 A01B D102 0218 110/J00 111/J01 0/J.00/0 A01B 03 1364 120/J00 121/J01 0/J.
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Draft Document for Review April 7, 2004 6:15 pm 6947ch03.fm IOCP. The CHPID assignment associates the CHPID number to a physical channel port location (PCHID). HiperSockets (IQD) and IC links (ICP) do not have PCHIDs, as they are virtual and not physical links, but they do require CHPID numbers. The PCIX Cryptographic Coprocessor (PCIXCC) and PCI Cryptographic Accelerator (PCICA) features do not require CHPID numbers but are assigned PCHIDs.
6947ch03.fm Draft Document for Review April 7, 2004 6:15 pm Table 3-7 I/O and cryptographic features support Number of Feature codes I/O feature Ports Ports per card increments Max. number of I/O slots PCHID Ports CHPID definition Config.
6947ch03.fm Draft Document for Review April 7, 2004 6:15 pm – Feature code 0218 is for the ISC Daughter card (ISC-D). One ISC Mother card supports up to two ISC Daughter cards, and each ISC Daughter card contains two ports. Port activation must be ordered using feature code 0219. RPQ 8P2197 is available to extend the distance of ISC-3 links to 20 km at 1Gb/sec. When RPQ 8P2197 is ordered, both ports (links) in the card are activated. 10.
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6947ch03.fm Draft Document for Review April 7, 2004 6:15 pm Feature code 2366 4 2367 Feature name OSA-E Fast Ethernet 6 OSA-E Token Ring Connector type Cable type RJ-45 Category 5 UTP RJ-45 UTP or STP 8 Table notes: 1. SM is single mode fiber. 2. MM is multimode fiber. 3. OSA-E refers to OSA-Express. 4. Brought forward to z990 on an upgrade only. 5. The OSA-Express GbE features brought forward from an upgrade have a different connector (SC Duplex) than the new OSA-E GbE features. 6.
6947ch03.fm Draft Document for Review April 7, 2004 6:15 pm ESCON channel port enablement feature The 15 active ports on each 16-port ESCON feature are activated in groups of 4 ports via Licensed Internal Code - Control Code (LIC-CC), by using the ESCON channel port feature (feature code 2324). The first group of 4 ESCON ports requires two 16-port ESCON features.
6947ch03.fm Draft Document for Review April 7, 2004 6:15 pm A maximum of 1024 ESCON ports can be activated on a z990 server. This maximum requires sixty-nine16-port ESCON channel cards to be installed. The z990 model A08 can have up to 720 ESCON ports, on 48 channel cards, which is limited by the number of STIs available on the A08 model. 16-port ESCON channel sparing The last ESCON port on a 16-port ESCON channel card (normally J15) is assigned as a spare port.
6947ch03.fm Draft Document for Review April 7, 2004 6:15 pm FQC supports all of the ESCON channels in the I/O cage. FQC cannot be ordered for selected channels. 3.4.3 FICON channel Following are connectivity options in the FICON I/O interface environment.
6947ch03.fm Draft Document for Review April 7, 2004 6:15 pm Note: Mode Conditioning Patch (MCP) cables are for use with 1 Gbit/sec (100 MB/sec) links only. Multimode (62.5 or 50 micron) fiber optic cable may be used with the z990 FICON Express LX feature for 1 Gbps only. The use of this multimode cable type requires a Mode Conditioning Patch (MCP) cable to be used at each end of the fiber optic link, or at each optical port in the link.
6947ch03.fm Draft Document for Review April 7, 2004 6:15 pm Adapter interruptions apply to a z990 FICON Express channel when in FCP mode (FCP CHPID type), which supports attachment of SCSI devices in a Linux for zSeries environment. z990 FCP SCSI IPL feature enabler (FC 9904) This optional z990 feature (FC 9904) allows Linux on zSeries operating system IPL from a SCSI or FCP disk. Both IPL of logical partition images and z/VM guests are supported.
6947ch03.fm Draft Document for Review April 7, 2004 6:15 pm Number of I/O feature Feature codes Ports Ports per card increments Maximum number Ports I/O slots PCHID CHPID definition Config. rules notes OSA-E Fast Ethernet 2366 2 2 24 12 yes OSE, OSD 1, 2, 3 OSA-E Token Ring 2 2 48 24 yes OSE, OSD 1, 2 2367 Notes: 1. The total number of FICON Express, OSA-Express, PCIXCC, and PCICA cards cannot exceed 20 per I/O cage. 2.
6947ch03.fm Draft Document for Review April 7, 2004 6:15 pm The z990 OSA-Express GbE LX feature occupies one slot in the z990 I/O cage and has two independent ports with one PCHID associated with each port. This feature supports the 1000BASE-SX standard transmission scheme. Each port supports connection to a 1 Gbps Ethernet LAN via 9 micron single-mode fiber optic cable terminated with an SC Duplex connector. Multimode (62.5 or 50 micron) fiber cable may be used with the z990 OSA-Express GbE LX feature.
6947ch03.fm Draft Document for Review April 7, 2004 6:15 pm 10 Mbps half-duplex or full-duplex 100 Mbps half-duplex or full-duplex 1000 Mbps/1Gbps full-duplex LAN speed and duplexing mode default to auto negotiation. The OSA-Express 1000BASE-T feature port and the attached switch automatically negotiate these settings. If the attached switch does not support auto-negotiation, the port enters the LAN at the default speed of 1000 Mbps and full duplex mode.
6947ch03.fm Draft Document for Review April 7, 2004 6:15 pm The OSA-Express FENET feature supports auto-negotiation with its attached Ethernet hub, router, or switch. If you allow the LAN speed to default to auto-negotiation, the FENET OSA-Express and the attached hub, router, or switch auto-negotiates the LAN speed setting between them. If the attached Ethernet hub, router, or switch does not support auto-negotiation, the OSA enters the LAN at the default speed of 100 Mbps in half-duplex mode.
6947ch03.fm Draft Document for Review April 7, 2004 6:15 pm This function does not apply to IPv6 packets. TCP/IP will continue to perform all checksum processing for IPv6 packets. This function also does not apply to ICMP checksum processing. TCP/IP will continue to perform processing for ICMP checksum. Checksum offload is supported by the OSA-Express GbE features (FC 1364, FC 1365) and the 1000BASE-T Ethernet feature (FC 1366) when operating at 1000 Mbps (1 Gbps).
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6947ch03.fm Draft Document for Review April 7, 2004 6:15 pm This RPQ card supports Peer mode and Compatibility mode at 1Gbps only. It extends the maximum distance of the ISC-3 link to 20 km. For Peer mode, one RPQ Daughter card is required at each end of the link between the z990, z900, z890 or z800 servers. For Compatibility mode, the equivalent G5/G6 server extended distance RPQ Daughter card is required on the G5/G6 server end of the link. Table 3-11 lists the various ISC-3 link characteristics.
6947ch03.fm Draft Document for Review April 7, 2004 6:15 pm output ports to support the ICB-2 connections. The STI-2 card converts the 2.0 GByte/sec input into two 333 MB/sec ICB-2s. One ICB-2 feature is required for each end of the link. Each ICB-2 link at the z990 end has a PCHID number. ICB-2 only support connection to 9672 G5/G6 servers. The ICB-2 cable (feature code 0226) is a unique 10 meter (33 feet) 333 MB copper cable to be used with ICB-2 links.
6947ch03.fm Draft Document for Review April 7, 2004 6:15 pm Important: The z990 timer support has been enhanced and requires a customer to assign a timer netID that must match the Sysplex Timer (9037) netID before the CPC clock will step to the 9037 time signals; refer to 7.2.1, “Sysplex configurations and Sysplex Timer considerations” on page 157 for more information. The port cards support concurrent maintenance.
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Draft Document for Review April 7, 2004 6:15 pm 6947ch04.fm 4 Chapter 4. Channel Subsystem This chapter describes how the Channel Subsystem (CSS) is implemented on the z990. Each server has a Channel Subsystem. Its role is to control communication of internal and external channels to control units and devices. The configuration definitions of the CSS define the operating environment for the correct execution of all system Input/Output (I/O) operations.
6947ch04.fm Draft Document for Review April 7, 2004 6:15 pm 4.1 Multiple Logical Channel Subsystem (LCSS) The concept of Logical Channel Subsystem (LCSS) is new to the z990. The z990 supports up to four Logical Channel Subsystems, hence the term multiple Logical Channel Subsystem. The design of the z990 offers a considerable increase in processing power, memory sizes, and I/O connectivity.
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6947ch04.fm Draft Document for Review April 7, 2004 6:15 pm number of partitions defined in the RESOURCE statements in the IOCDS. It is unique for each logical partition. Logical partition identifier The logical partition identifier is a number in the range from ‘00’ to ‘3F’. It is assigned by the user on the image profile through the Support Element (SE) or the Hardware Management Console. It is unique across the z990 and may also be referred to as the User Logical Partition ID (UPID).
6947ch04.fm Draft Document for Review April 7, 2004 6:15 pm We suggest you establish a naming convention for the logical partition identifiers. As shown in Figure 4-2, you could use the LCSS number concatenated to the MIF Image ID, which means logical partition ID 3A is in LCSS 3 with MIF ID A. This fits within the allowed range of logical partition IDs and conveys useful information to the user.
6947ch04.fm Draft Document for Review April 7, 2004 6:15 pm In each LCSS, the CHPIDs are shared across all logical partitions. The CHPIDs in each LCSS can be mapped to their designated PCHIDs using the CHPID Mapping Tool (CMT), or manually using HCD or IOCP. The output of the CMT is used as input to HCD or the IOCP to establish the CHPID to PCHID assignments. See 4.2.1, “z990 configuration management” on page 116 for further details on the CMT.
6947ch04.fm Draft Document for Review April 7, 2004 6:15 pm Channel spanning is supported for internal links (HiperSockets, and Internal Coupling (IC) links), and for some external links (FICON Express channels, OSA-Express, and coupling links). For a complete list of supported spanned channels, see Table 3-8, “Spanned and shared channels” on page 91. Note: Spanning of ESCON channels, FICON converter (FCV) channels and receiver coupling links are not supported.
6947ch04.fm Draft Document for Review April 7, 2004 6:15 pm IBM z990 CHPID Mapping Tool (CMT) The z990 CHPID Mapping Tool provides a mechanism to map CHPIDs onto PCHIDs as required on a z990. Additional enhancements have been built into the CMT to cater for the new requirements of the z; it provides the best availability recommendations for the installed z990 features and defined configuration.
6947ch04.fm Draft Document for Review April 7, 2004 6:15 pm HCD 1. Create IODF for z990 without PCHIDs H/W Config file or CFreport for your order (CCN) IODF No PCHIDs 2. Create Validated Work IODF HCD option 2.12 = Build validated work I/O definition file CHPID Mapping Tool 3. Create IOCP deck HCD option 2.3 = Build IOCP input data set IOCP Deck 5. Import IOCP deck with PCHIDs into IODF - HCD option 5.1 = Migrate IOCP/OS data, Migrate option 3 (PCHIDs) IOCP Deck No PCHIDs 6.
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Draft Document for Review April 7, 2004 6:15 pm 6947ch05.fm 5 Chapter 5. Cryptography This chapter describes the Cryptography functions of the z990. On the z990 the Cryptographic Assist Architecture (CAA), along with the CP Assist for Cryptographic Function, offers a balanced use of resources and unmatched scalability.
6947ch05.fm Draft Document for Review April 7, 2004 6:15 pm 5.1 Cryptographic function support The z990 includes both standard cryptographic hardware and optional cryptographic features, to give flexibility and growth capability.
6947ch05.fm Draft Document for Review April 7, 2004 6:15 pm • Import and export of DES keys under an RSA key, up to 2048-bit – Public Key Encrypt (PKE) Public Key Encrypt service is provided for the Mod_Raised_to Power (MRP) function. MRP is used to offload compute intensive portions of the Diffie-Hellman protocol onto the PCICA, or PCIXCC features of the z990 – Public Key Decrypt (PKD) Public Key Decrypt supports a zero-pad option for clear RSA private keys.
6947ch05.fm Draft Document for Review April 7, 2004 6:15 pm The Web site will direct the customer's request to an IBM Global Services (IGS) location appropriate for the customer's geographic location. A special contract will be negotiated between IGS and the customer, covering development of the UDX by IGS per the customer's specifications, as well as an agreed-upon level of the UDX.
6947ch05.fm Draft Document for Review April 7, 2004 6:15 pm The CP Assist for Cryptographic Function complements but does not execute public key (PKA) functions and is a prerequisite for the secure cryptographic operations provided by the PCIX Cryptographic Coprocessor (PCIXCC) feature, and the PCI Cryptographic Accelerator (PCICA) feature.
6947ch05.fm Draft Document for Review April 7, 2004 6:15 pm IBM Processor Resource/System Manager (PR/SM) fully supports the PCIX Cryptographic Coprocessor features to establish a logically partitioned environment in which multiple logical partitions can use the cryptographic functions. A 128-bit data-protection master key, and one 192-bit Public Key Algorithm (PKA) master keys are provided for each of 16 cryptographic domains.
6947ch05.fm Draft Document for Review April 7, 2004 6:15 pm In the z990, there can be a maximum of six PCI Cryptographic Accelerator (PCICA) features (two per I/O cage), along with a maximum of four PCIX Cryptographic Coprocessor features. The combined number of PCIXCC and PCICA features on a z990 cannot exceed eight. Within these parameters, the PCXICC and PCICA features can coexist in any combination.
6947ch05.fm Draft Document for Review April 7, 2004 6:15 pm 5.3.2 The PCICA feature Each PCI Cryptographic Accelerator feature contains up to two cryptographic accelerator cards. The physical layout of the PCICA card is illustrated in Figure 5-2 on page 126. PCI Accelerator Card FLASH FLASH PCI Accelerator Card Figure 5-2 PCI Cryptographic Accelerator feature Each PCICA feature has up to two cryptographic accelerator cards embedded in an adapter package for installing in I/O slots of the z990 cage.
6947ch05.fm Draft Document for Review April 7, 2004 6:15 pm Table 5-1 PCI Cryptography features Maximum number of features per z990 server Number of cryptographic coprocessors per feature Maximum number of cryptographic coprocessors per z990 server Number of cryptographic domains per coprocessora Number of logical partitions per z990 server (Defined/Active) PCICA 6 2 12 16 30/30 PCIXCC 4 1 4 16 30/30 a.
6947ch05.fm Draft Document for Review April 7, 2004 6:15 pm 5.3.5 TKE workstation feature A TKE workstation is part of a customized solution for using the Integrated Cryptographic Service Facility for z/OS program product to manage cryptographic keys of a z990 that has PCIX Cryptographic Coprocessor features installed and configured for using Data Encryption Standard (DES) and Public Key Algorithm (PKA) cryptographic keys.
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6947ch05.fm Draft Document for Review April 7, 2004 6:15 pm Double length Derived Unique Key Per Translation (DUKPT), on PCIXCC EMV 2000 Standard on PCIXCC Public Key Decrypt (PKD) enhancements on PCICA, and PCIXCC Public Key Encrypt (PKE) enhancements on PCICA, and PCIXCC The Web deliverable is found on URL: http://www.ibm.
6947ch05.fm Draft Document for Review April 7, 2004 6:15 pm Table 5-3 Software requirements to support cryptographic features Operating system CPACF PCIXCC PCICA OS/390 V2.10 and z/OS V1.2 and later with z990 Cryptographic Support or z990 and z890 Enhancements to Cryptographic Support Y Y Y z//VM V3.1 and V4.3 and later Y z/VM V4.3 and later for Linux guests Y z/VM V5.1 for z/OS and Linux guests Y Y Y Linux on zSeries Y Y Y Y z/VSE V3.1 Y VSE/ESA V2.7 and later Y Chapter 5.
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Draft Document for Review April 7, 2004 6:15 pm 6947ch06.fm 6 Chapter 6. Software support This chapter describes the software support available on the z990 including z/OS, OS/390, z/VM, z/VSE, VSE/ESA, TPF, and Linux operating systems. Addressing software migration considerations and workload license charges are also discussed.
6947ch06.fm Draft Document for Review April 7, 2004 6:15 pm 6.1 Operating system support There are many significant changes in the z990 architecture and hardware features when compared to the z900 processor. Extensive software support has been made available to existing OS levels via compatibility and exploitation support to accommodate these changes in the OS/390, z/OS, z/VSE, VSE/ESA, TPF, z/VM and Linux on zSeries operating systems. Table 6-1 summarizes supported software on the z990.
6947ch06.fm Draft Document for Review April 7, 2004 6:15 pm z990 Compatibility for selected OS/390, and z/OS releases OS/390 V2.10, z/OS V1.2, and z/OS V1.3 require the Web delivered Compatibility support to run on a z990. Attention: Compatibility nor Exploitation support is not available for z/OS 1.1 Compatibility support allows these releases to: Define a z990 environment with HCD Run on a z990 processor in a logical partition in LCSS-0, using an LPAR id equal to or less than x’F’.
6947ch06.fm Draft Document for Review April 7, 2004 6:15 pm Compatibility support required on all z990 logical partitions Compatibility support NOT required G5, G6, z800, or z900 OS/390 R10 z/OS 1.2 z/OS 1.3 z990 z/OS 1.
6947ch06.fm Draft Document for Review April 7, 2004 6:15 pm z/OS with Compatibility support must be IPLd in a partition that has an LPAR identifier in the range 0-F. If the LPAR identifier is outside of this range, then z/OS will terminate with a 07C-02 wait state. Dynamic activates for hardware changes can only be done for LCSS 0. A Power-on Reset is required for changes to other Logical Channel Subsystems.
6947ch06.fm Draft Document for Review April 7, 2004 6:15 pm 24 processors (sum of CPs and zAAPs) within a single logical partition. zSeries Application Assist Processors (zAAPs). Dynamic addition and deletion of a logical partition name z/OS V1.6 supports dynamic naming of a reserved logical partition. Reserved logical partitions are defined with a name placeholder ‘ * ’ and can be dynamically named or removed from the list of named logical partitions.
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6947ch06.fm Draft Document for Review April 7, 2004 6:15 pm Option 1: Java dispatching by priority (honor_priority=yes) Option 1 is the default option and specifies that standard CPs execute both Java and non-Java work in priority order when zAAPs are not configured. When zAAPs are configured they only execute Java work in priority order while the CPs execute normal tasks and JVM tasks in priority order.
Draft Document for Review April 7, 2004 6:15 pm 6947ch06.fm of logical partitions and logical CPs, these records could potentially increase in size beyond the 32 KB limit. To accommodate this, each record is now broken into pieces where each piece is shorter than 32KB. Each piece is self-containing; that is, the record can be processed without re-assembling the broken pieces.
6947ch06.fm Draft Document for Review April 7, 2004 6:15 pm Important: The need for ICKDSF Release 17 applies even to systems that are not part of the same sysplex, or that are running a non-MVS™ based operating system, such as z/VM. 6.2.8 ICSF support If you use z990 cryptographic hardware functions with ICSF, then you must install Compatibility support for this feature. Important: The ICSF Compatibility support is available for OS/390 V2.10, z/OS V1.3 and V1.4.
Draft Document for Review April 7, 2004 6:15 pm 6947ch06.fm D M=CPU IEE174I 14.45.55 DISPLAY M 159 PROCESSOR STATUS ID CPU SERIAL 0 + 1293052084 1 + 1293052084 2 + 1293052084 CPC ND = 002084.R01.IBM.02.000000049305 CPC SI = 2084.R01.IBM.02.0000000000049305 CPC ID = 00 CPC NAME = XXXXXXXX LP NAME = SC66, LP ID = 12 CSS ID = 1 MIF ID = D + ONLINE - OFFLINE .
6947ch06.fm Draft Document for Review April 7, 2004 6:15 pm D M=CHP(58) IEE174I 17.00.35 DISPLAY M 263 CHPID 58: TYPE=1B, DESC=FICON SWITCHED, ONLINE DEVICE STATUS FOR CHANNEL PATH 58 0 1 2 3 4 5 6 7 8 9 A B C D E F 022 + . . . . . . . . . . . . . . . 023 + . . . . . . . . . . . . . . . 098 . + + . . . . . . . . . . . . . SWITCH DEVICE NUMBER = B000 DEFINED ENTRY SWITCH - LOGICAL SWITCH ID = 03 ATTACHED ND = 006064.001.MCD.01.
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6947ch06.fm Draft Document for Review April 7, 2004 6:15 pm Adapter Interruption applying to performance assist for FICON Express features (type FCP), and OSA-Express features (type OSD) V=V guest support applying to performance assist for FICON Express features (type FCP), OSA-Express features (type OSD), and HiperSockets (type IQD). See also “HCD support” on page 140 for I/O configuration support under z/VM. ICKDSF Release 17 is required on all systems that share DASD with a z990 processor (see 6.2.
6947ch06.fm Draft Document for Review April 7, 2004 6:15 pm 30 logical partitions and two LCSSs. Support to further exploit z990 functions will be delivered as an Open Source Contribution via: http://www.software.ibm.com/developerworks/opensource/linux390 Commercial distributions of Linux on zSeries are available from Linux distributors, such as Red Hat, SUSE, and TurboLinux.
6947ch06.fm Draft Document for Review April 7, 2004 6:15 pm Software Requirements z/OS V1.6 a z/OS V1.5 z/OS V1.4 Exploit z/OS V1.3 z/OS V1.
6947ch06.fm Draft Document for Review April 7, 2004 6:15 pm Software Requirements z/VM V5.1 z/VM V4.4 z/VM V3.1 and V4.3 Functions 24 processors within a single logical partition X Internal spanned channels X X X External spanned channels X X X VSE/ ESA V2.7 and z/VSE V3.1 VSE/ ESA V2.6 TPF V4.1 Linux on zSeries a X Adapter Interruption (CHPID types FCP and OSD) X X V=V support for CHPID types FCP, OSD, and IQD X X HiperSockets X X X X X c X X Xd X VLAN (IEEE 802.
6947ch06.fm Draft Document for Review April 7, 2004 6:15 pm d. z/VM V4.3 only. e. z/VM 4.3 only with PTF for APAR VM63397. f. PUT 16. g. For z/VM install, IPL, and operation from SCSI disks. h. z/VM V4.3 only. For Linux as a guest. i. Planned for z/VSE V3.1 only (for FCP attached SCSI disks on the IBM ESS). j. See //http:www10.software.inm.com/developerworks/opensource/linux390. k. z/VM IPL from SCSI disks. l. For Linux as a guest. m. PUT 13 with PTF for APAR PJ2733. n. With PTF for APAR VM63405. o.
6947ch06.fm Draft Document for Review April 7, 2004 6:15 pm Even using the soft capping option, the partition’s utilization can reach up to its maximum, based on the number of logical processors and weights, as usual. Only the rolling 4-hour average utilization is tracked, allowing utilization peaks above the defined capacity value.
6947ch06.fm Draft Document for Review April 7, 2004 6:15 pm – If the set CPUID command has been issued, bits 0-7 are set to ‘FF’ by z/VM and bits 8-31 are set to the value entered in the set CPUID command. Bits 32-63 are the same as they would have been without running as a z/VM guest. Table 6-5 shows the possible output returned to the issuing program for an operating system running as a guest under z/VM.
Draft Document for Review April 7, 2004 6:15 pm 6947ch07.fm 7 Chapter 7. Sysplex functions This chapter describes the capabilities of the z990 to support coupling functions including Parallel Sysplex, Geographically Dispersed Parallel Sysplex™ (GDPS®), and Intelligent Resource Director.
6947ch07.fm Draft Document for Review April 7, 2004 6:15 pm 7.1 Parallel Sysplex Figure 7-1 illustrates the components of a Parallel Sysplex as implemented within the zSeries architecture. Shown is a z900 model 2xx ICF (CF01) connected to two z990 servers running in Sysplex. There is a second Integrated Coupling Facility (CF02) defined within one of the z990s, containing SysPlex logical partitions running z/OS.
Draft Document for Review April 7, 2004 6:15 pm 6947ch07.fm Business applications are “data sharing enabled” and cloned across images to allow workload balancing and to prevent loss of application availability in the event of an outage. Many operational and recovery processes can be automated, reducing the need for human intervention.
6947ch07.fm Draft Document for Review April 7, 2004 6:15 pm The Workload Manager (WLM) component of z/OS or OS/390 provides sysplex-wide workload management capabilities based on installation-specified performance goals and the business importance of the workloads. The Workload Manager tries to attain the performance goals through dynamic resource distribution. WLM provides the Parallel Sysplex cluster with the intelligence to determine where work needs to be processed and in what priority.
6947ch07.fm Draft Document for Review April 7, 2004 6:15 pm 7.1.2 Parallel Sysplex summary Through this state-of-the-art cluster technology, the power of multiple z/OS and/or OS/390 images can be harnessed to work in concert on common workloads. The zSeries Parallel Sysplex cluster takes the commercial strengths of the z/OS or OS/390 platform to improved levels of system management, competitive price/performance, scalable growth, and continuous availability. 7.
6947ch07.fm Draft Document for Review April 7, 2004 6:15 pm A function is introduced with the z990 server, implemented in the server's Support Element code, which now requires the ETR Network ID of the attached Sysplex Timer Network to be manually set in the Support Element at installation time. This function checks that the ETR Network ID being received in the timing signals via each of the server's two ETR ports matches the ETR Network ID manually set in the server's Support Element (SE).
6947ch07.fm Draft Document for Review April 7, 2004 6:15 pm . Figure 7-2 z990 SE workplace: External Timer Reference Configuration panel The network ID configured on the z990 must match the actual Sysplex Timer network ID to which the server is connected. If the network ID entered on the SE panel does not match the network ID that was assigned to the Sysplex Timer, the timer port enters a semi-operation state.
6947ch07.fm Draft Document for Review April 7, 2004 6:15 pm 7.2.2 Coupling Facility and CFCC considerations The z990 can participate in a Parallel Sysplex when the Coupling Facility resides in a G5 or G6 or any zSeries Server. When system images in the sysplex reside across z990 and non-z990 Servers, consideration must be given for compatibility support; see “Compatibility support for z/OS” on page 134.
6947ch07.fm Draft Document for Review April 7, 2004 6:15 pm updated CFCC code to a CF logical partition, simply deactivate and activated the partition. When the CF comes up, it displays its version on the OPRMSG panel for that partition. Continue to run other LPARs on the z990 where a ‘disruptive’ CFCC patch is applied without being impacted by the application of the patch. CFCC levels supported on a z990 CFLEVEL Minimum software levelsa CFLEVEL 12 z/OS 1.
6947ch07.fm Draft Document for Review April 7, 2004 6:15 pm 7.2.4 Coupling Facility link connectivity The type of CF links you can use to connect a CF to an operating system logical partition is important because of the impact of the link performance on response times and coupling overheads. For configurations covering large distances, the time spent on the link can be the largest part of the response time (mainly if the CF is defined on a z990 server).
6947ch07.fm Draft Document for Review April 7, 2004 6:15 pm Link Type z990 Max 64b Maximum number of links per z990 a. A maximum of 32 ISC-3s can be defined in compatibility mode, which operates at to 1 Gb/s. b. The maximum number of external and internal Coupling Links combined (ICB-2, ICB-3, ICB-4, ISC-3, and active IC links) cannot exceed 64 per system. Refer to Table 7-3 for an overview of the CF link connectivity options for the various supported servers.
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6947ch07.fm Draft Document for Review April 7, 2004 6:15 pm CPs are processor units used to process z/OS, OS/390, CFCC, z/VM, Linux, TPF, VSE/ESA, or z/VSE instructions. The logical partition can use dedicated or shared CPs. However, it is not possible to have a logical partition with dedicated and shared CPs at the same time. ICFs are PUs dedicated to process the CF Control Code (CFCC) on a Coupling Facility image, which is always running on a logical partition.
6947ch07.fm Draft Document for Review April 7, 2004 6:15 pm 7.2.7 Dynamic CF dispatching and dynamic ICF expansion The CF Control Code (CFCC), the “CF Operating System,” is implemented using the Active Wait technique. This means it is always running (processing or searching for service) and never enters into a wait state. This also means that it gets all the processor capacity (cycles) available for the Coupling Facility logical partition.
6947ch07.fm Draft Document for Review April 7, 2004 6:15 pm Dynamic ICF expansion can also be configured using dedicated ICF PUs and shared CPs from the z/OS image. The z/OS image must have all CPs defined as shared and the Dynamic CF Dispatch function must be activated. Dynamic ICF Expansion is available on z990 models that have at least one ICF. Dynamic ICF Expansion requires that Dynamic CF Dispatching be activated (DYNDISP ON).
6947ch07.fm Draft Document for Review April 7, 2004 6:15 pm Cost benefits are realized by enabling the use of non-standalone Coupling Facilities (for example, ICFs) for all resource sharing and data sharing environments. 7.3.2 CF Structure Duplexing System-managed Coupling Facility structure duplexing creates a duplexed copy of the structure in advance of any failure, providing a robust failure recovery capability through failover to the unaffected structure instance.
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6947ch07.fm Draft Document for Review April 7, 2004 6:15 pm It includes a sample migration plan, describes how to monitor this new Parallel Sysplex technology and how to determine its cost/benefit in your environment, and gives setup recommendations. 7.4 Geographically Dispersed Parallel Sysplex IBM Installation Services for GDPS is a total end-to-end solution that manages availability within a site and across multiple sites.
6947ch07.fm Draft Document for Review April 7, 2004 6:15 pm Sysplex cluster must be configured with redundant hardware (for example, a Coupling Facility and a Sysplex Timer in each site), and the cross-site connections must be redundant.
6947ch07.fm Draft Document for Review April 7, 2004 6:15 pm application UCB UCB PPRC P S Figure 7-9 HyperSwap Planned HyperSwap GDPS/PPRC planned HyperSwap provides: The ability to switch all primary PPRC disk subsystems with the secondary PPRC disk subsystems for a planned reconfiguration and enables disk configuration maintenance and planned site maintenance without requiring any applications to be quiesced.
6947ch07.fm Draft Document for Review April 7, 2004 6:15 pm GDPS/PPRC Management for Open Systems LUNs GDPS/PPRC technology has been extended to manage a heterogeneous environment of z/OS and Open Systems data. If installations share their disk subsystems between the z/OS and Open Systems platforms, GDPS/PPRC, running in a z/OS system, can manage the PPRC status of devices that belong to the other platforms and are not even defined to the z/OS platform.
6947ch07.fm Draft Document for Review April 7, 2004 6:15 pm Restriction: The maximum distance between a pair of Sysplex Timers in an Expanded Availability configuration remains at 40 kilometers (25 miles). To achieve 100 kilometers distance between sites one option is to consider an intermediate site at less than 40 kilometers from one or the other site or to place two Sysplex Timers in one site.
6947ch07.fm Draft Document for Review April 7, 2004 6:15 pm to perform a normal Data Base Management System (DBMS) restart - not DBMS recovery at the opposite site. GDPS/XRC is application-independent and therefore covers the customer's complete application environment.
6947ch07.fm Draft Document for Review April 7, 2004 6:15 pm lost elsewhere in the enterprise. CBU adds Central Processors (CPs) to the available pool of processors and is activated only in an emergency. GDPS-CBU management automates the process of dynamically adding reserved Central Processors, thereby minimizing manual customer intervention and the potential for errors. The outage time for critical workloads can be reduced from hours to minutes.
6947ch07.fm Draft Document for Review April 7, 2004 6:15 pm IRD addresses three separate but mutually supportive functions: LPAR CPU management WLM dynamically adjusts the number of logical processors within a logical partition and the processor weight based on the WLM policy. The ability to move the CPU weights across an LPAR cluster provides processing power to where it is most needed based on WLM goal mode policy.
6947ch07.fm Draft Document for Review April 7, 2004 6:15 pm Value of CPU management The benefits of CPU management include the following: Logical CPs perform at the fastest uniprocessor speed available. This results in the number of logical CPs tuned to the number of physical CPs of service being delivered by the logical partition current weight.
6947ch07.fm Draft Document for Review April 7, 2004 6:15 pm Where several channels are attached from a z990 LCSS to a switch, they can be considered a resource pool for accessing any of the control units attached to the same switch. To achieve this without DCM would require deactivating paths, performing a dynamic I/O reconfiguration, and activating new paths. DCM achieves the equivalent process automatically, using those same mechanisms. Channels managed by DCM are referred to here as “managed” channels.
6947ch07.fm Draft Document for Review April 7, 2004 6:15 pm Simplified I/O definition The connection between managed channels and managed control units does not have to be explicitly defined. Reduced skills required to manage z/OS Managed channels and control units are automatically monitored, balanced, tuned, and reconfigured. Enhanced availability A failing or hung channel path will result in reduced throughput on the affected control unit.
6947ch07.fm Draft Document for Review April 7, 2004 6:15 pm CSS Priority Queueing uses different priorities calculated in a different way from the I/O priorities used for UCB and control unit queueing.
6947ch07.fm Draft Document for Review April 7, 2004 6:15 pm Within an LPAR cluster, the prioritization is managed by WLM goal mode and coordinated across the cluster. Hence the range should be set identically for all logical partitions in the same LPAR cluster. WLM sets priorities within a range of eight values that will be mapped to the specified range. If a larger range is specified, WLM uses the top eight values.
Draft Document for Review April 7, 2004 6:15 pm 6947ch07.fm System automation - I/O operations When using system automation, take care when using PROHIBIT or BLOCK on a port that is participating in Dynamic Channel Path Management. When blocking a managed channel port, configuring the CHPID OFFLINE to all members of the LPAR Cluster is all that is required.
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Draft Document for Review April 7, 2004 6:15 pm 6947ch08.fm 8 Chapter 8. Capacity upgrades This chapter describes the zSeries 990 server’s capacity upgrade functions and features. It also includes capacity measurements and performance considerations. The z990 servers have the capability of concurrent upgrades, without a server outage, in both planned and unplanned situations. In most cases, a z990 capacity upgrade can also be nondisruptive, without a system outage.
6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm 8.1 Concurrent upgrades The z990 servers have the capability of concurrent upgrades, providing additional capacity with no server outage. In most cases, with prior planning and operating system support, a concurrent upgrade can also be nondisruptive, meaning with no system outage (Power-on Resets (PORs), logical partition deactivations, and IPLs do not have to take place).
6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm These LIC-CC based PU conversions, as listed on Table 2-7, “PU conversions” on page 65, require that at least one PU (CP, ICF or IFL) has to remain untouched, otherwise the conversion is disruptive. The PU conversion generates a new LIC-CC which can be installed concurrently in two steps. First, the assigned PU is removed from the z990 configuration. Second, the newly available PU is activated as the new PU type.
6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm On/Off CoD can concurrently add processors (CPs, IFLs, ICFs, and zAAPs) up to the limit of the installed book(s) of an existing server, and is restricted to the double of the current installed capacity. On/Off CoD uses the CIU ordering process, initiated by the customer via the Web using IBM Resource Link, and makes use of CUoD techniques. On/Off CoD requires a special contract.
Draft Document for Review April 7, 2004 6:15 pm 6947ch08.fm CUoD provides the ability to concurrently add processors (CPs, IFLs, ICFs, and zAAPs), memory capacity, and I/O ports.
6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm CUoD for processors CUoD for processors can add, concurrently, more CPs, IFLs, ICFs, and zAAPs to a z990 server by assigning available spare PUs via LIC-CC. Depending on the quantity of the additional CPs, IFLs, ICFs, and zAAPs in the upgrade, additional book(s) may be required and can be concurrently installed before the LIC-CC enablement. Note: The sum of CPs, unassigned CPs, IFLs, unassigned IFLs, ICFs, and zAAPs cannot exceed 8 PUs per book.
Draft Document for Review April 7, 2004 6:15 pm 6947ch08.fm Then the 2084-B16, software model 309, is concurrently upgraded to a software model 310 (10 CPs) with two IFLs by assigning and activating three more spare PUs (one as CP and two as IFLs). Additional logical processors can be concurrently configured online to logical partitions by the operating system when reserved processors are previously defined, resulting in image upgrades.
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6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm The new amount of installed memory cannot cause the storage granularity or increment to change. However, a new Reset Profile (to allow the customer to potentially select a higher storage increment to Plan Ahead for concurrent memory upgrade) will be available. The Minimum Storage Granularity will be the required storage granularity based on what memory is currently LIC-CC installed.
6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm A z990 server has 16 ESCON channels available, on two 16-port ESCON channel cards installed in an I/O cage. Each channel card has eight ports enabled. In this example, eight additional ESCON channels are concurrently added to the configuration by enabling, via LIC-CC, using four unused ports on each ESCON channel card.
Draft Document for Review April 7, 2004 6:15 pm 6947ch08.fm CIU may change the server’s software model (3xx) if additional CPs are requested, but it cannot change the z990 server model (2084-xxx). Additional logical processors can be concurrently configured online to logical partitions by the operating system when reserved processors are previously defined, resulting in image upgrades. The operating system must have the capability to concurrently configure more processors online.
6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm ibm.com/servers/resourcelink Customer Internet CIU order Optional customer secondary order approval Remote Support Facility Figure 8-4 CIU ordering example The following is a sample list of the screen sequences a customer must follow on Resource Link to initiate an order: 1. Sign on to Resource Link. 2. Select the CIU option from the main Resource Link page. 3. Customer and machine details associated with the Userid are listed. 4.
6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm ibm.com/servers/resourcelink Customer Internet HMC Access Support Element (SE) CIU order CIU order z990 Server Remote Support Facility Figure 8-5 CIU activation example Figure 8-5 shows the CIU activation process. IBM Resource Link communicates with the Remote Support Facility to stage the CIU order and prepare it for download. The customer is automatically notified when the order is ready for download.
6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm Figure 8-6 CIU order example The number of CPs, ICFs, zAAPs, IFLs, SAPs, memory size, CBU features, unassigned CPs, and unassigned IFLs (Linux) on the current configuration are displayed on the left side. On the right side are the corresponding updated values of the ordered configuration.
Draft Document for Review April 7, 2004 6:15 pm 6947ch08.fm Activation The customer's system stores all the LIC-CC records associated with the z990 that has the CIU option. These LIC-CC records will only be available for download when they are externally activated by Resource Link. Upon submission of the order, Resource Link will dynamically enable the appropriate LIC-CC records and make them available to the customer, via the Remote Support Facility, to be downloaded by the Hardware Management Console.
6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm Figure 8-8 CIU upgrade selection screen An On/Off CoD upgrade for processors cannot be applied while a previous On/Off CoD or a CBU is activated. In those cases, the requested upgrade can be retrieved, but can be applied only after the current temporary upgrade is deactivated. On/Off CoD upgrades for memory can be retrieved and applied, even while a CBU or a previous On/Off CoD activation is in place. 8.
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6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm Initiation Before a customer can order temporary capacity, they must have a signed agreement for Customer Initiated Upgrade (CIU) facility. In addition to this agreement, they will need to acknowledge and agree to additional specific terms which govern the use of temporary capacity. At the completion of signing a contract, an order is placed through CIU to install an On/Off CoD right to use feature.
6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm $....... Figure 8-9 On/Off CoD order example This On/Off CoD example is ordering an upgrade from 4 CPs to 5 CPs plus 2 zAAPs to the current server. The maximum number of CPs, ICFs, zAAPs and IFLs is limited by the current number of available spare PUs of the installed books on the z990 server.
6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm On/Off CoD right to use feature without transferring ownership. This might be desirable if the customer wants to put CBU on the z990 server, or simply wants to put business controls in place that prevent On/Off CoD from being used in the future. Application of feature code 9898 will terminate the right to use On/Off CoD. This feature cannot be ordered if a temporary session is already active.
Draft Document for Review April 7, 2004 6:15 pm 6947ch08.fm Important: The CBU capability can coexist with On/Off CoD enablement. Both CBU and On/Off CoD LIC-CC can be installed on a z990 server, but the CBU activation and On/Off CoD activation are mutually exclusive. CBU can only add CPs to an existing z990 server, but note that CPs can assume any kind of workload that could be running on IFLs, zAAPs, and ICF processors at the failed system or systems.
6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm When the emergency is over (or the CBU test is complete), the server must be taken back to its original, permanent configuration. The CBU features can be deactivated by the customer at any time before the expiration date. Otherwise, the performance of the system will be degraded after expiration, unless CBU is deactivated.
6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm CBU deactivation The process of deactivating CBU is simple and straightforward. The process starts by quiescing the added CPs (normally the highest numbered) from all the logical partitions, and varying them offline from the operating systems. Then from the HMC CBU activation panel, perform a concurrent CBU undo. CBU testing Testing of disaster/recovery plans is easy with CBU.
6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm servers in the take-over site to restore processing power for mission-critical production workloads. GDPS automation will: Perform the analysis required to determine the scope of the failure; this minimizes operator intervention and the potential for errors. Automate authentication and activation of the reserved CPs. Automatically restart the critical applications after reserved CP activation.
6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm Concurrent upgrades are not supported with CPs defined as additional SAPs. If reserved processors are defined to a logical partition, then z/OS, OS/390, and z/VM operating system images can dynamically configure more processors online, allowing nondisruptive processor upgrades. The Coupling Facility Control Code (CFCC) can also configure more processors online to Coupling Facility logical partitions using the CFCC image operations panel.
6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm All scenarios show the hardware (physical) and the logical partition configurations before and after the upgrade. Only the 8 PUs available for CPs, IFLs, ICFs, and zAAPs are shown on each server’s book. Shared logical partitions upgrade Figure 8-11 on page 210 shows a 2084-A08, software model 307 server. This one-book server configuration has seven CPs and one spare PU.
6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm Partition LP1 has two reserved CPs defined and, if the operating system running on it has the capability of configuring processors online, this partition can be nondisruptively upgraded to nine CPs, as shown in this example. Partition LP2 has no reserved CPs, so it cannot be nondisruptively upgraded. If any upgrade for this partition is required, it will require deactivation to configure more CPs.
6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm At this point, even with no partition configuration changes, LP2 and LP3 (shared) partitions may experience performance improvements. As there is now more available capacity (physical processors) to be used by all logical shared CPs, the “logical-to-physical processors ratio” is reduced. In this example, before the upgrade, there were twelve shared logical CPs (six for LP2 and six for LP3) to be dispatched into six physical CPs.
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6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm Changing the number of logical partitions defined to a z990 server. The only way to add or delete a logical partition is by a POR using a new IOCDS including or excluding the new partition. Changing the number of LCSS on a server. Changing the number of subchannels supported on a LCSS. Logical partition processor upgrades when reserved processors were not previously defined are disruptive to image upgrades.
6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm Define the appropriate number of LCSSs (maximum is 4), based on the required number of logical partitions (maximum is 30) and the number of CHPIDs (maximum is 256 per image and per LCSS) that a future configuration may have. Spare and reserved logical partitions, which can have partition name ‘ * ‘ for future renaming as described in the previous item, can help to define additional LCSSs for future use.
6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm z990 introduces a new microprocessor architecture exploiting the CMOS9S-SOI technology while improving uniprocessor performance.
Draft Document for Review April 7, 2004 6:15 pm 6947ch08.fm zSeries Application Assist Processors (zAAPs), which are designed to operate asynchronously with the CPs to execute Java programming under control of IBM Java Virtual Machine (JVM) for logical partitions running z/OS. The IBM JVM processing cycles can be executed on the configured zAAPs with no anticipated modifications to the Java applications.
6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm Book 0 PU ... L1 Book 1 PU PU L1 L1 PU ... L1 Ring Structure L2 Cache L2 Cache Memory Memory MBA MBA Figure 8-16 Two-book system logical view In this example, a local access is done by the first PU on Book 0 to its local L2 cache, and a remote access is done by the last PU on Book 1 to the L2 cache on Book 1.
6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm To exploit this parallel execution capability, the z990 server has implemented an improved instruction scheduling. The instruction execution order is optimized to provide instruction sequences that can operate in a multi-pipeline environment. The major enhancements are in the e-business applications, such as WebSphere and other Java and C/C++ code. Further exploitation can also be done on the software side.
6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm cryptographic processes that use SSL/TLS can be offloaded from the host to the PCICA feature to reduce CP and IFL usage, thus increasing system throughput. Performance assists for Linux and z/VM z990 adapter interruptions for Linux and z/VM - the z990, Linux on zSeries, and z/VM work together to provide performance improvements by exploiting extensions to the Queued Direct Input/Output (QDIO) architecture.
6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm IBM utilizes the Large Systems Performance Reference (LSPR) method to provide relative capacity information, which takes into account processor design sensitivities to workload type. LSPR benchmarks are laboratory controlled tests of representative workload environments, objectively measured and analyzed. 8.8.
6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm Each individual LSPR workload is designed to focus on a single major type of activity, such as interactive, on-line database, or batch. The LSPR does not focus on individual pieces of work such as specific job or application. Instead, each LSPR workload includes a broad mix of activity related to that workload type.
6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm workload types are now required to better evaluate processor capacity as the production environments are changing, including new, e-business applications.
6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm The WASDB workload reflects a new-e-business production environment that uses WebSphere applications and a DB2 data base all running in z/OS. WASDB is a collection of Java classes, Java Servlets, Java Server Pages and Enterprise Java Beans integrated into a single application. It is designed to emulate an online brokerage firm. WASDB was developed using the VisualAge® for Java and WebSphere Studio tools.
6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm by taking the WASDB workload, and converting it to run both application and data base server in a single Linux image. The WASDB/L workload is basically the same as the WASDB workload for z/OS, with exception of being enabled for Linux. UDB 7.0 is used instead of DB2 v7.0, and WebSphere AE 4.0.4 is used instead of WebSphere 4.0.1.400.
6947ch08.fm Draft Document for Review April 7, 2004 6:15 pm z990 LSPR tables The current LSPR tables including all the z990 ITR Ratios, based on a z990 uniprocessor for all workload environments, can be found at: http://www.ibm.
Draft Document for Review April 7, 2004 6:15 pm 6947ch09.fm 9 Chapter 9. Environmentals This chapter introduces the IBM eServer zSeries 990 environmental requirements. We list its dimensions, weights, power, and cooling requirements as an overview of what’s needed to plan for the installation of a z990 server. For more comprehensive physical planning information, refer to zSeries 990 Installation Manual for Physical Planning (IMPP), GC28-6824.
6947ch09.fm Draft Document for Review April 7, 2004 6:15 pm 9.1 Introduction The z990 is always a two-frame system. The frames are shipped separately and are fastened together when installed. Installation of a z990 is always on a raised floor. The number of cables to be expected for most configurations may be so large that installation is only possible with space underneath. The dimensions of a z990 are slightly smaller than that of a two-frame z900 and its maximum weight is slightly higher. 9.1.
6947ch09.fm Draft Document for Review April 7, 2004 6:15 pm Table 9-2 Internal Battery Feature emergency power times I/O configuration Model One I/O cage Two I/O cages Three I/O cages IBM 2084 model A08 8 minutes 13 minutes 12 minutes IBM 2084 model B16 13 minutes 8.5 minutes 10.5 minutes IBM 2084 model C24 8.5 minutes 11 minutes 9 minutes IBM 2084 model D32 13 minutes 8.5 minutes 7.5 minutes 9.1.
6947ch09.fm Draft Document for Review April 7, 2004 6:15 pm Table 9-4 System weights Configuration Weight in kg (lb) without IBF Weight in kg (lb) with IBF IBM 2084-A08 1174 (2582) to 1534 (3376) 1263 (2779) to 1714 (3770) IBM 2084-B16 1281 (2818) to 1642 (3612) 1460 (3212) to 1910 (4203) IBM 2084-C24 1329 (2924) to 1690 (3718) 1508 (3318) to 1959 (4309) IBM 2084-D32 1401 (3082) to 1738 (3824) 1669 (3673) to 2007 (4415) 9.3 Dimensions The z990 always has two frames: frame A and frame Z.
Draft Document for Review April 7, 2004 6:15 pm 6947axA.fm A Appendix A. Hardware Management Console (HMC) Introduction In this appendix we discuss the z990 Hardware Management Console, and provide you with some configuration guidelines. The HMC is a PC/ISA bus PC running OS/2®, Communications Server for OS/2, a remote control systems management product, and the Hardware Management Console Application (HMCA).
6947axA.fm Draft Document for Review April 7, 2004 6:15 pm Consolidation of: Operator controls Hardware status reporting Hardware message presentation Operating system messages Problem analysis and reporting Licensed Internal Code (LIC) control and distribution Remote I/O configuration and IOCDS management Scheduled operations The HMC communicates with the CPC through the Support Element (SE).
6947axA.fm Draft Document for Review April 7, 2004 6:15 pm HMC LAN zSeries z990 HMC G5/G6 Series zSeries z900 Figure A-2 Multi CPC Environment Important: Beginning with the next zSeries server, after the IBM eServer zSeries 890 and 990 all new HMCs on all currently marketed zSeries servers are intended to become closed platforms. They will only support the HMC application and not the installation of other applications such as the IBM ESCON Director and the IBM Sysplex Timer console applications.
6947axA.fm Draft Document for Review April 7, 2004 6:15 pm Important: The z890 and z990 will be the last zSeries servers to offer Token Ring adapter features on the Hardware Management Consoles (HMCs), Support Element (SEs), and Trusted Key Entry (TKE) workstations. The IBM 2074 Model 3 Console Support Controller will be the last controller to offer Token Ring adapter features.
6947axA.fm Draft Document for Review April 7, 2004 6:15 pm Additional token ring only wiring scenario Additional connections to the token ring LAN may be made to expand the connectivity beyond the local Hardware Management Console and Support Elements, as shown in Figure A-4 on page 237. If connections to previous generations of Enterprise Server systems are desired, they may be connected using the MAU in the system, or they may be connected using token ring-to-token ring bridges.
6947axA.fm Draft Document for Review April 7, 2004 6:15 pm The Ethernet features assume the use of 10/100 Mbit Ethernet facilities, requiring the use of CAT-5 Ethernet cabling. Since the Support Element Ethernet only feature includes two Ethernet adapters, there will be two Ethernet connections available. For this scenario, only the Ethernet cable connected to the Ethernet in the first (top) PCMCIA slot of the Support Elements will be used.
6947axA.fm Draft Document for Review April 7, 2004 6:15 pm Ethernet LAN Bridge Token-Ring LAN SE SE SE SE SE SE G5-G6 Series zSeries 990 zSeries 900 Figure A-6 Ethernet only - one-path wiring scenario with additional connections Ethernet only - two-path wiring scenario Ethernet only - two-path wiring scenario (not applicable to systems with FC 0075. This scenario is included for those who may be reusing a previous Hardware Management Console.
6947axA.fm Draft Document for Review April 7, 2004 6:15 pm attached to either LAN is able to automatically discover the Support Elements, assuming that the LAN network allows NetBios to flow between the devices (allowing NetBios to flow is a requirement for local HMC-to-SE communication, but it is not a requirement for remote HMC-to-SE communication).
6947axA.fm Draft Document for Review April 7, 2004 6:15 pm Primary Ethernet LAN Secondary Ethernet LAN SE SE SE Bridge SE zSeries 990 zSeries 990 Token-Ring LAN Enterprise LAN Figure A-8 Ethernet only - two-path wiring scenario with additional connections Token ring and Ethernet wiring scenario The token ring and Ethernet wiring scenario, shown in Figure A-9, is intended for enterprises that have both token ring wiring and Ethernet wiring requirements.
6947axA.fm Draft Document for Review April 7, 2004 6:15 pm Ethernet LAN Token-Ring LAN SE SE zSeries 990 Figure A-9 Token ring and Ethernet wiring scenario Additional connections to the Token Ring LAN These connections, shown in Figure A-10 on page 243, may be made to expand the connectivity beyond the local Hardware Management Console and Support Elements. This would be done as in the “Token ring only wiring scenario” on page 236.
6947axA.fm Draft Document for Review April 7, 2004 6:15 pm IBM uses remote control program product facilities to assist in problem determination, and to provide operational assistance as required. IBM also uses the SDLC or TCP/IP asynchronous connection facilities to transmit service data to and from the IBM Service Support System, to gather error data, and to receive fixes.A remote operation configuration is shown in Figure A-10 on page 243.
6947axA.fm Draft Document for Review April 7, 2004 6:15 pm seen as overkill. Thus a requirement for those users has been to lower the cost of acquisition by offering an alternative solution. The integrated 3270 Console support meets that requirement. On the HMC workspace there is now an icon to open this 3270 window. It is designed for production system use. One HMC at a time can use the function; however, there is support to switch the function from one HMC to another.
6947axA.fm Draft Document for Review April 7, 2004 6:15 pm The Send and Receive push buttons have been removed. There is now a check box for indicating that the command typed is a reply to a “Priority Message”. SNA Operations Management for Operations Automation With the industry move to TCP/IP networks, Systems Network Architecture (SNA) Operations Management commands will no longer be supported on z990 servers.
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Draft Document for Review April 7, 2004 6:15 pm 6947axB.fm B Appendix B. Fiber optic cabling services In order to address the complexities and changes over time to different type of cables/connectors and Standards, IBM Networking Services provides a comprehensive set of services for your products and enterprises. This service helps you gain an Information Technology (IT) advantage by providing you with the tools you need to gain market share in this fast-paced e-business economy.
6947axB.fm Draft Document for Review April 7, 2004 6:15 pm Fiber optic cabling services from IBM As mentioned, fiber optic cables, cable planning, labeling, and installation are all customer responsibilities for new installations and upgrades. Fiber optic conversion kits and Mode Conditioning Patch (MCP) cables are not orderable as features on z990.
Draft Document for Review April 7, 2004 6:15 pm 6947axB.fm Option 1 - Fiber optic jumper cabling package (available today for z800 and z900). IBM does the detailed planning. This option includes planning, new cables, installation, and documentation. An analysis of the zSeries channel configuration, I/O devices, and any existing fiber optic cabling is required to determine the appropriate fiber optic cables. Option 2 - Fiber optic jumper cable migration and reuse for a zSeries upgrade (new option).
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Draft Document for Review April 7, 2004 6:15 pm 6947bibl.fm Related publications The publications listed in this section are considered particularly suitable for a more detailed discussion of the topics covered in this redbook. IBM Redbooks For information on ordering these publications, see “How to get IBM Redbooks” on page 252. Note that some of the documents referenced here may be available in softcopy only.
6947bibl.fm Draft Document for Review April 7, 2004 6:15 pm Online resources These Web sites and URLs are also relevant as further information sources: IBM zSeries server product line http://www.ibm.com/servers/eserver/zseries/ IBM zSeries connectivity options http://www.ibm.com/servers/eserver/zseries/connectivity IBM Large Systems Performance Reference for zSeries http://www.ibm.com/servers/eserver/zseries/lspr IBM Resource Link http://www.ibm.
6947glos.fm Draft Document for Review April 7, 2004 6:15 pm Glossary active configuration. In an ESCON environment, the ESCON Director configuration determined by the status of the current set of connectivity attributes. Contrast with saved configuration. allowed. In an ESCON Director, the attribute that, when set, establishes dynamic connectivity capability. Contrast with prohibited. American National Standards Institute (ANSI).
6947glos.fm core. (1) In an optical cable, the central region of an optical fiber through which light is transmitted. (2) In an optical cable, the central region of an optical fiber that has an index of refraction greater than the surrounding cladding material. See also cladding and optical fiber. coupler. In an ESCON environment, link hardware used to join optical fiber connectors of the same type. Contrast with adapter. CPC. Central Processor Complex CTC. (1) Channel-to-channel.
6947glos.fm Draft Document for Review April 7, 2004 6:15 pm ESA/390. See Enterprise Systems Architecture/390. ESCD console. The ESCON Director display and keyboard device used to perform operator and service tasks at the ESCD. ESCD. Enterprise Systems Connection (ESCON) Director. ESCON channel. A channel having an Enterprise Systems Connection channel-to-control-unit I/O interface that uses optical cables as a transmission medium. May operate in CBY, CNC, CTC or CVC mode. Contrast with parallel channel.
6947glos.fm initial program load (IPL). (1) The initialization procedure that causes an operating system to commence operation. (2) The process by which a configuration image is loaded into storage at the beginning of a work day or after a system malfunction. (3) The process of loading system programs and preparing a system to run jobs. input/output (I/O). (1) Pertaining to a device whose parts can perform an input process and an output process at the same time.
6947glos.fm Draft Document for Review April 7, 2004 6:15 pm local area network (LAN). A computer network located in a user’s premises within a limited geographic area. Logical Channel Subsystem (LCSS). A defined subset of the CPC hardware (subchannels, channels, and I/O interfaces) that is used to support the operation of a Logical Channel Subsystem. The LCSS relieves the processor of direct I/O communication tasks, and performs path management functions.
6947glos.fm original equipment manufacturers information (OEMI). A reference to an IBM guideline for a computer peripheral interface. More specifically, refer to IBM S/360 and S/370 Channel to Control Unit Original Equipment Manufacture’s Information. The interfaces uses ESA/390 logical protocols over an I/O interface that configures attached units in a multi-drop bus environment. parallel channel.
Draft Document for Review April 7, 2004 6:15 pm 6947glos.fm Small Computer System Interface (SCSI). (1) An ANSI standard for a logical interface to a computer peripherals and for a computer peripheral interface. The interface uses a SCSI logical protocol over an I/O interface that configures attached targets and initiators in a multi-drop bus topology. (2) A standard hardware interface that enables a variety of peripheral devices to communicate with one another. spanning channels.
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(0.5” spine) 0.475”<->0.873” 250 <-> 459 pages (1.0” spine) 0.875”<->1.498” 460 <-> 788 pages (1.5” spine) 1.5”<-> 1.998” 789 <->1051 pages 6947spine.fm 261 To determine the spine width of a book, you divide the paper PPI into the number of pages in the book. An example is a 250 page book using Plainfield opaque 50# smooth which has a PPI of 526. Divided 250 by 526 which equals a spine width of .4752". In this case, you would use the .5” spine.
Conditional Text Settings (ONLY!) to the book files. 262 (2.5” spine) 2.5”<->nnn.n” 1315<-> nnnn pages 6947spine.fm To determine the spine width of a book, you divide the paper PPI into the number of pages in the book. An example is a 250 page book using Plainfield opaque 50# smooth which has a PPI of 526. Divided 250 by 526 which equals a spine width of .4752". In this case, you would use the .5” spine.
6947IX.fm Draft Document for Review April 7, 2004 6:15 pm Index Numerics 1000BASE-T Ethernet 11 16-port ESCON feature 93 50.0 micron 99–100 62.
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Draft Document for Review April 7, 2004 6:16 pm Back cover ® IBM eServer zSeries 990 Technical Guide Structure and design A scalable Processor Unit, Memory, Multiple Capacity upgrade options The IBM Eserver zSeries® 990 scalable server provides major extensions to existing zSeries architecture and capabilities. The concept of Logical Channel Subsystems is added, and the maximum number of processor units and logical partitions is increased.
