Title Page PPC440x5 CPU Core User’s Manual Preliminary SA14-2613-02 September 12, 2002
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User’s Manual Preliminary PPC440x5 CPU Core Contents Figures ............................................................................................................................ 15 Tables .............................................................................................................................. 19 About This Book ............................................................................................................ 23 1. Overview ............................................
User’s Manual PPC440x5 CPU Core Preliminary 2.3.2 Allocated Instruction Class ..................................................................................................... 2.3.3 Preserved Instruction Class ................................................................................................... 2.3.4 Reserved Instruction Class .................................................................................................... 2.4 Implemented Instruction Set Summary ......................
User’s Manual Preliminary PPC440x5 CPU Core 2.10 Synchronization ............................................................................................................................. 2.10.1 Context Synchronization ...................................................................................................... 2.10.2 Execution Synchronization .................................................................................................. 2.10.3 Storage Ordering and Synchronization .........
User’s Manual PPC440x5 CPU Core Preliminary 5.1 MMU Overview .............................................................................................................................. 5.1.1 Support for PowerPC Book-E MMU Architecture ................................................................ 5.2 Translation Lookaside Buffer ......................................................................................................... 5.3 Page Identification ............................................
User’s Manual Preliminary PPC440x5 CPU Core 6.4.4 Critical Save/Restore Register 0 (CSRR0) .......................................................................... 6.4.5 Critical Save/Restore Register 1 (CSRR1) .......................................................................... 6.4.6 Machine Check Save/Restore Register 0 (MCSRR0) ......................................................... 6.4.7 Machine Check Save/Restore Register 1 (MCSRR1) .........................................................
User’s Manual PPC440x5 CPU Core Preliminary 7.4 Watchdog Timer ............................................................................................................................ 7.5 Timer Control Register (TCR) ....................................................................................................... 7.6 Timer Status Register (TSR) ......................................................................................................... 7.7 Freezing the Timer Facilities .............
User’s Manual Preliminary PPC440x5 CPU Core 9.3 Pseudocode .................................................................................................................................. 9.3.1 Operator Precedence .......................................................................................................... 9.4 Register Usage ............................................................................................................................. 9.5 Alphabetical Instruction Listing .....
User’s Manual PPC440x5 CPU Core Preliminary icbt ............................................................................................................................................. iccci............................................................................................................................................ icread......................................................................................................................................... isel ........................
User’s Manual Preliminary PPC440x5 CPU Core mtspr ......................................................................................................................................... mulchw ...................................................................................................................................... mulchwu .................................................................................................................................... mulhhw ................................
User’s Manual PPC440x5 CPU Core Preliminary stwu ........................................................................................................................................... stwux ......................................................................................................................................... stwx ........................................................................................................................................... subf............................
User’s Manual Preliminary PPC440x5 CPU Core ICDBDR..................................................................................................................................... ICDBTRH .................................................................................................................................. ICDBTRL ................................................................................................................................... INV0–INV3 .....................................
User’s Manual PPC440x5 CPU Core Preliminary Index ............................................................................................................................. 571 Revision Log ................................................................................................................ 589 Page 14 of 583 ppc440x5TOC.fm.
User’s Manual Preliminary PPC440x5 CPU Core Figures Figure 1-1. PPC440 Core Block Diagram ................................................................................................. 30 Figure 2-1. User Programming Model Registers ...................................................................................... 48 Figure 2-2. Supervisor Programming Model Registers ............................................................................ 49 Figure 2-3. Link Register (LR) ...............
User’s Manual PPC440x5 CPU Core Preliminary Figure 6-3. Save/Restore Register 1 (SRR1) .........................................................................................168 Figure 6-4. Critical Save/Restore Register 0 (CSRR0) ...........................................................................168 Figure 6-5. Critical Save/Restore Register 1 (CSRR1) ...........................................................................169 Figure 6-6.
User’s Manual Preliminary PPC440x5 CPU Core Figure 10-14. Data Cache Debug Tag Register Low (DCDBTRL) ............................................................. 479 Figure 10-15. Data Exception Address Register (DEAR) ........................................................................... 480 Figure 10-16. Decrementer (DEC) ............................................................................................................. 481 Figure 10-17. Decrementer Auto-Reload (DECAR) .................
User’s Manual PPC440x5 CPU Core Preliminary Figure A-2. B Instruction Format .............................................................................................................522 Figure A-3. SC Instruction Format ...........................................................................................................522 Figure A-4. D Instruction Format .............................................................................................................522 Figure A-5.
User’s Manual Preliminary PPC440x5 CPU Core Tables Table 2-1. Data Operand Definitions ....................................................................................................... 40 Table 2-2. Alignment Effects for Storage Access Instructions ................................................................ 40 Table 2-3. Register Categories ............................................................................................................... 50 Table 2-4.
User’s Manual PPC440x5 CPU Core Preliminary Table 5-4. Access Control Applied to Cache Management Instructions ...............................................144 Table 6-1. Interrupt Types Associated with each IVOR .........................................................................171 Table 6-2. Interrupt and Exception Types ..............................................................................................175 Table 7-1. Fixed Interval Timer Period Selection .......................
User’s Manual Preliminary PPC440x5 CPU Core Table 9-31. Extended Mnemonics for tw ................................................................................................. 441 Table 9-32. Extended Mnemonics for twi ................................................................................................ 444 Table 10-1. Register Categories ............................................................................................................. 452 Table 10-2.
User’s Manual PPC440x5 CPU Core Page 22 of 583 Preliminary ppc440x5LOT.fm.
User’s Manual Preliminary PPC440x5 CPU Core About This Book This user’s manual provides the architectural overview, programming model, and detailed information about the instruction set, registers, and other facilities of the IBM™ Book-E Enhanced PowerPC™ 440x5 (PPC440x5™) 32-bit embedded controller core.
User’s Manual PPC440x5 CPU Core Preliminary Contents, on page v. Figures, on page xi. Tables, on page xiii. Index, on page 571. Notation The manual uses the following notational conventions: • Active low signals are shown with an overbar (Active_Low) • All numbers are decimal unless specified in some special way. • 0bnnnn means a number expressed in binary format. • 0xnnnn means a number expressed in hexadecimal format. Underscores may be used between digits.
User’s Manual Preliminary • PPC440x5 CPU Core n x means the replication of x, n times (that is, x concatenated to itself n – 1 times). n0 and n1 are special cases: • n0 means a field of n bits with each bit equal to 0. Thus 50 is equivalent to 0b00000. • n1 means a field of n bits with each bit equal to 1. Thus 51 is equivalent to 0b11111. • /, //, ///, ... denotes a reserved field in an instruction or in a register. • ? denotes an allocated bit in a register.
User’s Manual PPC440x5 CPU Core Page 26 of 589 Preliminary preface.fm.
User’s Manual Preliminary PPC440x5 CPU Core 1. Overview The IBM™ PowerPC™ 440x5 32-bit embedded processor core, referred to as the PPC440x5 core, implements the Book-E Enhanced PowerPC Architecture. This chapter describes: • PPC440x5 core features • The PPC440x5 core as an implementation of the Book-E Enhanced PowerPC Architecture • The organization of the PPC440x5 core, including a block diagram and descriptions of the functional units • PPC440x5 core interfaces 1.
User’s Manual PPC440x5 CPU Core Preliminary • 9-port (6-read, 3-write) 32x32-bit General Purpose Register (GPR) file • Hardware support for all CPU misaligned accesses • Full support for both big and little endian byte ordering • Extensive power management designed into core for maximum performance/power efficiency • Primary caches • Independently configurable instruction and data cache arrays • Array size offerings: 32KB, 16KB, and 8KB • Single-cycle access • 32-byte (eight word) line size • Highly-assoc
User’s Manual Preliminary PPC440x5 CPU Core – Decrementer with auto-reload capability – Fixed Interval Timer (FIT) – Watchdog Timer with critical interrupt and/or auto-reset • Multiple core Interfaces defined by the IBM CoreConnect on-chip system architecture • PLB interfaces • Three independent 128-bit interfaces for instruction reads, data reads, and data writes • Glueless attachment to 32-, 64-, or 128-bit CoreConnect system environments • Multiple CPU:PLB frequency ratios supported (N:1, N:2, N:3) • 6
User’s Manual PPC440x5 CPU Core Preliminary 1.3 PPC440x5 Organization The PPC440x5 core includes a seven-stage pipelined PowerPC core, which consists of a three stage, dualissue instruction fetch and decode unit with attached branch unit, together with three independent, 4-stage pipelines for complex integer, simple integer, and load/store operations, respectively.
User’s Manual Preliminary PPC440x5 CPU Core 1.3.2 Execution Pipelines The PPC440x5 core contains three execution pipelines: complex integer, simple integer, and load/store. Each pipeline consists of four stages and can access the nine-ported (six read, three write) GPR file. In order to improve performance and avoid contention for the GPR file, there are two identical copies of it.
User’s Manual PPC440x5 CPU Core Preliminary The ICC supports cache line locking, at either an 8-line or 16-line granularity, depending on cache size (16line for 32KB, 8-line for 8KB and 16KB). In addition, the notion of a “transient” portion of the cache is supported, in which the cache can be configured such that only a limited portion is used for instruction cache lines from memory pages that are designated by a storage attribute from the MMU as being transient in nature.
User’s Manual Preliminary PPC440x5 CPU Core The translation lookaside buffer (TLB) is the primary hardware resource involved in the control of translation, protection, and storage attributes. It consists of 64 entries, each specifying the various attributes of a given page of the address space. The TLB is fully-associative; the entry for a given page can be placed anywhere in the TLB.
User’s Manual PPC440x5 CPU Core Preliminary 1.3.5 Timers The PPC440x5 contains a Time Base and three timers: a Decrementer (DEC), a Fixed Interval Timer (FIT), and a Watchdog Timer. The Time Base is a 64-bit counter which gets incremented at a frequency either equal to the processor core clock rate or as controlled by a separate asynchronous timer clock input to the core. No interrupt is generated as a result of the Time Base wrapping back to zero.
User’s Manual Preliminary PPC440x5 CPU Core tion in real time. Debug wait mode enables the processor to continue to service real-time critical interrupts while instruction execution is otherwise stopped for hardware debug. The debug modes are controlled by Debug Control Register 0 (DBCR0) and the setting of bits in the Machine State Register (MSR). Internal debug mode supports accessing architected processor resources, setting hardware and software breakpoints, and monitoring processor status.
User’s Manual PPC440x5 CPU Core Preliminary 1.4.1 Processor Local Bus (PLB) There are three independent 128-bit PLB interfaces to the PPC440x5 core. Each of these interfaces includes a 36-bit address bus and a 128-bit data bus. One PLB interface supports instruction cache reads, while the other two support data cache reads and writes, respectively.
User’s Manual Preliminary PPC440x5 CPU Core PowerPC floating point unit (single or double precision), multimedia engine, DSP, or other custom function implementing algorithms appropriate for specific system applications. The APU interface supports dual-issue pipeline designs, and can be used with macros that contain their own register files, or with simpler macros which use the CPU GPR file for source and/or target operands.
User’s Manual PPC440x5 CPU Core Page 38 of 589 Preliminary overview.fm.
User’s Manual Preliminary PPC440x5 CPU Core 2.
User’s Manual PPC440x5 CPU Core Preliminary Data storage operands for storage access instructions have the following characteristics. Table 2-1.
User’s Manual Preliminary PPC440x5 CPU Core Similarly, the TLB management instructions access page operands, and—as determined by the page size— the associated low-order effective address bits are ignored during the execution of these instructions. Instruction storage operands, on the other hand, are always four bytes long, and the effective addresses calculated by Branch instructions are therefore always word-aligned. 2.1.
User’s Manual PPC440x5 CPU Core Preliminary The 14-bit BD field is concatenated on the right with 0b00, sign-extended, and then added to either the address of the branch instruction if AA=0, or to 0 if AA=1; the low-order 32 bits of the sum form the effective address of the next instruction.
User’s Manual Preliminary PPC440x5 CPU Core • The ordering that assigns the lowest address to the highest-order (“left-most”) eight bits of the scalar, the next sequential address to the next-highest-order eight bits, and so on. This ordering is called big endian because the “big end” (most-significant end) of the scalar, considered as a binary number, comes first in storage. IBM RISC System/6000, IBM System/390, and Motorola 680x0 are examples of computer architectures using this byte ordering.
User’s Manual PPC440x5 CPU Core Preliminary Big Endian Mapping The big endian mapping of structure s follows (the data is highlighted in the structure mappings). Addresses, in hexadecimal, are below the data stored at the address. The contents of each byte, as defined in structure s, is shown as a (hexadecimal) number or character (for the string elements). The shaded cells correspond to padded bytes.
User’s Manual Preliminary PPC440x5 CPU Core On the other hand, in a little endian mapping the same instruction is arranged with the least-significant byte (LSB) of the instruction word at the lowest-numbered address: LSB 0x00 MSB 0x01 0x02 0x03 By the definition of PowerPC Book-E bit numbering, the most-significant byte of an instruction is the byte containing bits 0:7 of the instruction.
User’s Manual PPC440x5 CPU Core Preliminary • For word loads and stores (including load/store multiple), bytes are reversed within the word, for one byte order with respect to the other. • For doubleword loads and stores (AP loads/stores only), bytes are reversed within the doubleword, for one byte order with respect to the other. • For quadword loads and stores (AP loads/stores only), bytes are reversed within the quadword, for one byte order with respect to the other.
User’s Manual Preliminary PPC440x5 CPU Core 2.2 Registers This section provides an overview of the register categories and types provided by the PPC440x5. Detailed descriptions of each of the registers are provided within the chapters covering the functions with which they are associated (for example, the cache control and cache debug registers are described in Instruction and Data Caches on page 95).
User’s Manual PPC440x5 CPU Core Preliminary Integer Processing Branch Control General Purpose Condition Register GPR0 CR GPR1 Count Register GPR2 CTR • • • Link Register LR GPR31 Processor Control Integer Exception Register XER Timer Time Base SPR General 4–7 SPRG4 SPRG5 SPRG5 TBL TBU SPRG7 User SPR General 0 USPRG0 Figure 2-1. User Programming Model Registers Page 48 of 589 prgmodel.fm.
User’s Manual Preliminary PPC440x5 CPU Core Processor Control Machine State Register Timer Time Base Storage Control Process ID MSR TBU PID Processor Version Register TBL PVR Timer Control Register Processor ID Register TCR PIR Timer Status Register Debug Debug Status Register Core Configuration Registers TSR DBSR Decrementer Debug Data Register DEC DBDR CCR0 CCR1 Reset Configuration RSTCFG SPR General SPRG0 • • • SPRG7 Decrementer Auto-Reload MMU Control Register MMUCR Debug Cont
User’s Manual PPC440x5 CPU Core Preliminary Table 2-3.
User’s Manual Preliminary PPC440x5 CPU Core Table 2-3. Register Categories Register Category Register(s) DEC DECAR Type SPR Page 211 Supervisor, write-only SPR 211 User read, Supervisor write SPR 209 TCR Supervisor SPR 215 TSR Supervisor SPR 216 Timer TBL, TBU prgmodel.fm.
User’s Manual PPC440x5 CPU Core Preliminary 2.2.1 Register Types There are five register types contained within and/or supported by the PPC440x5 core. Each register type is characterized by the instructions which are used to read and write the registers of that type. The following subsections provide an overview of each of the register types and the instructions associated with them. 2.2.1.
User’s Manual Preliminary PPC440x5 CPU Core 2.2.1.4 Machine State Register The Machine State Register (MSR) is a register of its own unique type that controls important chip functions, such as the enabling or disabling of various interrupt types. The MSR can be written from a GPR using the mtmsr instruction. The contents of the MSR can be read into a GPR using the mfmsr instruction. The MSR[EE] bit can be set or cleared atomically using the wrtee or wrteei instructions.
User’s Manual PPC440x5 CPU Core Preliminary • cause a Floating-Point Unavailable interrupt if the instruction is recognized as a floating-point instruction, but floating-point processing is disabled; or • cause an Unimplemented Instruction exception type Program interrupt, if the instruction is recognized as a floating-point instruction and floating-point processing is enabled, but the instruction is not supported by the implementation; or • perform the actions described in the rest of this document, if t
User’s Manual Preliminary PPC440x5 CPU Core In addition to supporting the defined instructions of PowerPC Book-E, the PPC440x5 also implements a number of instructions which use the allocated instruction opcodes, and thus are not part of the PowerPC Book-E architecture. Table 2-21 on page 63 identifies the allocated instructions that are implemented within the PPC440x5 core.
User’s Manual PPC440x5 CPU Core Preliminary 2.3.4 Reserved Instruction Class This class of instructions consists of all instruction primary opcodes (and associated extended opcodes, if applicable) which do not belong to either the defined, allocated, or preserved instruction classes. Reserved instructions are available for future versions of PowerPC Book-E architecture.
User’s Manual Preliminary PPC440x5 CPU Core Table 2-4 summarizes the PPC440x5 instruction set by category. Instructions within each category are described in subsequent sections. Table 2-4.
User’s Manual PPC440x5 CPU Core Preliminary an “indexed” form (in which the address is formed by adding the contents of the RA and RB GPRs) and a “base + displacement” form (in which the address is formed by adding a 16-bit signed immediate value (specified as part of the instruction) to the contents of GPR RA. See the detailed instruction descriptions in Instruction Set on page 249. Table 2-5.
User’s Manual Preliminary PPC440x5 CPU Core 2.4.1.3 Integer Logical Instructions Table 2-7 lists the integer logical instructions in the PPC440x5. See Integer Arithmetic Instructions on page 58 for an explanation of the “[.]” syntax. Table 2-7. Integer Logical Instructions And and[.] andi. andis. And with complement andc[.] Or with complement Nand Or nand[.] or[.] ori oris Nor orc[.] nor[.] Xor Equivalence xor[.] xori eqv[.] xoris Extend sign extsb[.] extsh[.
User’s Manual PPC440x5 CPU Core Preliminary 2.4.1.7 Integer Shift Instructions Table 2-11 lists the integer shift instructions in the PPC440x5. Note that the shift right algebraic insructions implicitly update the XER[CA] field. See Integer Arithmetic Instructions on page 58 for an explanation of the “[.]” syntax. Table 2-11. Integer Shift Instructions Shift Left slw[.] Shift Right srw[.] Shift Right Algebraic sraw[.] srawi[.] 2.4.1.
User’s Manual Preliminary PPC440x5 CPU Core 2.4.3.1 Condition Register Logical Instructions These instructions perform logical operations on a specified pair of bits in the CR, placing the result in another specified bit. The benefit of these instructions is that they can logically combine the results of several comparison operations without incurring the overhead of conditional branching between each one.
User’s Manual PPC440x5 CPU Core Preliminary Table 2-17 shows the processor synchronization instruction in the PPC440x5. Table 2-17. Processor Synchronization Instruction isync 2.4.4 Storage Control Instructions These instructions manage the instruction and data caches and the TLB of the PPC440x5 core. Instructions are also provided to synchronize and order storage accesses. The instructions in these three sub-categories of storage control instructions are described below. 2.4.4.
User’s Manual Preliminary PPC440x5 CPU Core 2.4.4.3 Storage Synchronization Instructions The storage synchronization instructions allow software to enforce ordering amongst the storage accesses caused by load and store instructions, which by default are “weakly-ordered” by the processor. “Weaklyordered” means that the processor is architecturally permitted to perform loads and stores generally out-oforder with respect to their sequence within the instruction stream, with some exceptions.
User’s Manual PPC440x5 CPU Core Preliminary 2.5 Branch Processing The four branch instructions provided by PPC440x5 are summarized in Table 2.4.2 on Page 60. In addition, each of these instructions is described in detail in Instruction Set on page 249. The following sections provide additional information on branch addressing, instruction fields, prediction, and registers. 2.5.
User’s Manual Preliminary PPC440x5 CPU Core Table 2-22 summarizes the usage of the bits of the BO field. BO[4] is further discussed in Branch Prediction on page 65 Table 2-22. BO Field Definition BO Bit Description CR Test Control BO[0] 0 Test CR bit specified by BI field for value specified by BO[1] 1 Do not test CR CR Test Value BO[1] 0 If BO[0] = 0, test for CR[BI] = 0. 1 If BO[0] = 0, test for CR[BI] = 1.
User’s Manual PPC440x5 CPU Core Preliminary The PPC440x5 core combines the static prediction mechanism defined by PowerPC Book-E, together with a dynamic branch prediction mechanism, in order to provide correct branch prediction as often as possible. The dynamic branch prediction mechanism is an implementation optimization, and is not part of the architecture, nor is it visible to the programming model.
User’s Manual Preliminary PPC440x5 CPU Core When being used as a return address by a bclr instruction, bits 30:31 of the LR are ignored, since all instruction addresses are on word boundaries. Access to the LR is non-privileged. 0 31 Figure 2-3. Link Register (LR) 0:31 Link Register contents Target address of bclr instruction 2.5.5.2 Count Register (CTR) The CTR is written from a GPR using mtspr, and can be read into a GPR using mfspr.
User’s Manual PPC440x5 CPU Core Preliminary CR2 CR0 0 3 4 7 8 CR6 CR4 11 12 CR1 15 16 CR3 19 20 23 24 CR5 27 28 31 CR7 Figure 2-5.
User’s Manual Preliminary PPC440x5 CPU Core Table 2-24. CR Updating Instructions Integer Storage Access Arithmetic add.[o] addc.[o] adde.[o] addic. addme.[o] addze.[o] stwcx. Logical divw.[o] divwu.[o] neg.[o] Rotate Shift Storage Control Auxiliary Processor CR-Logical and Register Management TLB Mgmt. Arithmetic and Logical macchw.[o] macchws.[o] macchwsu.[o] macchwu.[o] machhw.[o] machhws.[o] machhwsu.[o] machhwu.[o] maclhw.[o] maclhws.[o] maclhwsu.[o] maclhwu.[o] and. andi. andis. andc.
User’s Manual PPC440x5 CPU Core Preliminary • Certain forms of various integer instructions (the “.” forms) implicitly update CR[CR0], as do certain forms of the auxiliary processor instructions implemented within the PPC440x5 core. • Auxiliary processor instructions may in general update a specified CR field in an implementation-specified manner.
User’s Manual Preliminary PPC440x5 CPU Core CR Update By Integer Compare Instructions Integer compare instructions update a specified CR field with the result of a comparison of two 32-bit numbers, the first of which is from a GPR and the second of which is either an immediate value or from another GPR. There are two types of integer compare instructions, arithmetic and logical, and they are distinguished by the interpretation given to the 32-bit numbers being compared.
User’s Manual PPC440x5 CPU Core Preliminary 2.6.2 Integer Exception Register (XER) The XER records overflow and carry indications from integer arithmetic and shift instructions. It also provides a byte count for string indexed integer storage access instructions (lswx and stswx). Note that the term exception in the name of this register does not refer to exceptions as they relate to interrupts, but rather to the arithmetic exceptions of carry and overflow.
User’s Manual Preliminary PPC440x5 CPU Core Table 2-25. XER[SO,OV] Updating Instructions Integer Arithmetic Add addo[.] addco[.] addeo[.] addmeo[.] addzeo[.] Subtract Auxiliary Processor Multiply subfo[.] subfco[.] subfeo[.] mullwo[.] subfmeo[.] subfzeo[.] Divide Negate divwo[.] nego[.] divwuo[.] Multiply-Accumulate Negative Multiply- Accumulate macchwo[.] macchwso[.] macchwsuo[.] macchwuo[.] machhwo[.] machhwso[.] machhwsuo[.] machhwuo[.] maclhwo[.] maclhwso[.] maclhwsuo[.] maclhwuo[.
User’s Manual PPC440x5 CPU Core Preliminary 2.6.2.2 Overflow (OV) Field This field is updated by certain integer arithmetic instructions to indicate whether the infinitely precise result of the operation can be represented in 32 bits. For those integer arithmetic instructions that update XER[OV] and produce signed results, XER[OV] = 1 if the result is greater than 231 – 1 or less than –231; otherwise, XER[OV] = 0.
User’s Manual Preliminary PPC440x5 CPU Core • Processor Version Register (PVR) Indicates the specific implementation of a processor • Processor Identification Register (PIR) Indicates the specific instance of a processor in a multi-processor system • Core Configuration Register 0 (CCR0) Controls specific processor functions, such as instruction prefetch • Reset Configuration (RSTCFG) Reports the values of certain fields of the TLB as supplied at reset Except for the MSR, each of these registers is describ
User’s Manual PPC440x5 CPU Core Preliminary OWN 0 11 12 31 PVN Figure 2-9. Processor Version Register (PVR) 0:11 OWN Owner Identifier Identifies the owner of a core. 12:31 PVN Processor Version Number Implementation-specific value identifying the specific version and use of a processor core within a chip. 2.7.
User’s Manual Preliminary PPC440x5 CPU Core PRE 0 1 DSTG 2 3 4 5 9 10 11 12 CRPE DTB GDCBT ICSLC 15 16 17 18 19 22 23 24 GICBT FLSTA DAPUIB 27 28 29 30 31 ICSLT Figure 2-11.
User’s Manual PPC440x5 CPU Core Preliminary Force Load/Store Alignment 23 FLSTA 30:31 See Load and Store Alignment on page 117. Reserved 24:27 28:29 0 No Alignment exception on integer storage access instructions, regardless of alignment 1 An alignment exception occurs on integer storage access instructions if data address is not on an operand boundary. ICSLC ICSLT Instruction Cache Speculative Line Count Number of additional lines (0–3) to fill on instruction fetch miss.
User’s Manual Preliminary PPC440x5 CPU Core Controls inversion of parity bit recorded for the U fields in the data cache. 13 DCUPEI Data Cache U-bit Parity Error Insert 0 record even parity (normal) 1 record odd parity (simulate parity error) 14 DCMPEI Data Cache Modified-bit Parity Error Insert 0 record even parity (normal) 1 record odd parity (simulate parity error) Controls inversion of parity bits recorded for the modified (dirty) field in the data cache.
User’s Manual PPC440x5 CPU Core Preliminary U1 Storage Attribute 17 U1 18 U2 19 U3 0 U1 storage attribute is disabled 1 U1 storage attribute is enabled See Table 5-1 on page 135. U2 Storage Attribute 0 U2 storage attribute is disabled 1 U2 storage attribute is enabled See Table 5-1 on page 135. U3 Storage Attribute 20:23 0 U3 storage attribute is disabled 1 U3 storage attribute is enabled See Table 5-1 on page 135.
User’s Manual Preliminary PPC440x5 CPU Core Table 2-27. Privileged Instructions (continued) mfmsr mfspr For any SPR Number with SPRN5 = 1. See Privileged SPRs on page 81. mtdcr mtmsr mtspr For any SPR Number with SPRN5 = 1. See Privileged SPRs on page 81. rfci rfi rfmci tlbre tlbsx tlbsync tlbwe wrtee wrteei 2.8.2 Privileged SPRs Most SPRs are privileged. The only defined non-privileged SPRs are the LR, CTR, XER, USPRG0, SPRG4– 7 (read access only), TBU (read access only), and TBL (read access only).
User’s Manual PPC440x5 CPU Core Preliminary The architecture provides two mechanisms for protecting against errant accesses to such “non-well-behaved” memory addresses. The first is the guarded (G) storage attribute, and protects against speculative data accesses. The second is the execute permission mechanism, and protects against speculative instruction fetches. Both of these mechanisms are described in Memory Management on page 133 2.
User’s Manual Preliminary XYZ PPC440x5 CPU Core fetch and execute the instruction at address XYZ In this sequence, the isync instruction does not guarantee that the XYZ instruction is fetched after the store has occurred to memory. There is no guarantee which XYZ instruction will execute; either the old version or the new (stored) version might. 2.
User’s Manual PPC440x5 CPU Core Preliminary thought of as being context synchronizing with respect to the MSR[EE] bit, in that it guarantees that subsequent instructions execute (or are prevented from executing and an interrupt taken) according to the new context of MSR[EE]. 2.10.3 Storage Ordering and Synchronization Storage synchronization enforces ordering between storage access instructions executed by the PPC440x5 core. There are two storage synchronizing instructions: msync and mbar.
User’s Manual Preliminary PPC440x5 CPU Core 3. Initialization This chapter describes the initial state of the PPC440x5 core after a hardware reset, and contains a description of the initialization software required to complete initialization so that the PPC440x5 core can begin executing application code. Initialization of other on-chip and/or off-chip system components may also be needed, in addition to the processor core initialization described in this chapter. 3.
User’s Manual PPC440x5 CPU Core Preliminary nizing operation (including causing any exceptions which would lead to an interrupt), since a context synchronizing operation will invalidate the shadow TLB entries. Initialization software should consider all other resources within the PPC440x5 core to be undefined after reset, in order for the initialization sequence to be compatible with other PowerPC implementations.
User’s Manual Preliminary PPC440x5 CPU Core Table 3-1.
User’s Manual PPC440x5 CPU Core Preliminary Table 3-1. Reset Values of Registers and Other PPC440x5 Facilities Resource Field Reset Value U0 System-dependent U1 System-dependent U2 System-dependent U3 System-dependent E System-dependent EPRN System-dependent WRC 0b00 RSTCFG Comment All RSTCFG fields are specified by core input signals TCR EPN0:19 1 Translation table entry for the initial program memory page is valid.
User’s Manual Preliminary PPC440x5 CPU Core 3.2 Reset Types The PPC440x5 core supports three types of reset: core, chip, and system. The type of reset is indicated by a set of core input signals. For each type of reset, the core resources are initialized as indicated in Table 3-1 on page 86. Core reset is intended to reset the PPC440x5 core without necessarily resetting the rest of the onchip logic.
User’s Manual PPC440x5 CPU Core Preliminary 2. Invalidate the instruction cache (iccci) 3. Invalidate the data cache (dccci) 4. Synchronize memory accesses (msync) This step forces any data PLB operations that may have been in progress prior to the reset operation to complete, thereby allowing subsequent data accesses to be initiated and completed properly. 5.
User’s Manual Preliminary PPC440x5 CPU Core care must be taken during the initialization sequence to prevent any such context synchronizing operations (such as interrupts and the isync instruction) until after this step is completed, and an architected TLB entry has been established in the TLB.
User’s Manual PPC440x5 CPU Core Preliminary 11. Initialize interrupt resources 1. Initialize IVPR to specify high-order address of the interrupt handling routines Make sure that the corresponding address region is covered by a TLB entry (or entries) 2.
User’s Manual Preliminary PPC440x5 CPU Core 1. Set MSR[CE] to enable/disable Critical Input and Watchdog Timer interrupts 2. Set MSR[EE] to enable/disable External Input, Decrementer, and Fixed Interval Timer interrupts 3. Set MSR[DE] to enable/disable Debug interrupts 4.
User’s Manual PPC440x5 CPU Core Page 94 of 589 Preliminary init.fm.
User’s Manual Preliminary PPC440x5 CPU Core 4. Instruction and Data Caches The PPC440x5 core provides separate instruction and data cache controllers and arrays, which allow concurrent access and minimize pipeline stalls. The storage capacity of the cache arrays, which can range from 8KB–32KB each, depends upon the implementation.
User’s Manual PPC440x5 CPU Core Preliminary ated with the line that currently resides in that way. The middle-order address bits form an index to select a specific set of the cache, while the five lowest-order address bits form a byte-offset to choose a specific byte (or bytes, depending on the size of the operation) from the 32-byte cache line. Table 4-1.
User’s Manual Preliminary PPC440x5 CPU Core VNDXA 0 VNDXC 7 8 15 16 VNDXB 23 24 31 VNDXD Figure 4-1.
User’s Manual PPC440x5 CPU Core Preliminary The size of the victim index fields varies according to the size of the respective cache. Also, which field is used varies according to the type of access, the size of the cache, and the address of the cache line. Table 4-3 describes the correlation between the victim index fields and different access types, cache sizes, and addresses. Table 4-3.
User’s Manual Preliminary PPC440x5 CPU Core 4.1.2 Cache Locking and Transient Mechanism Both caches support locking, at a “way” granularity. Any number of ways can be locked, from 0 ways to one less than the total number of ways (64 ways for 32KB and 16KB cache sizes, 32 ways for the 8KB cache size). At least one way must always be left unlocked, for use by cacheable line fills.
User’s Manual PPC440x5 CPU Core Preliminary Replacement Policy on page 96, the values of the fields are constrained to lie within the range specified by the NFLOOR field of the corresponding victim limit register, and the last way of the cache (way 31 for the 8KB cache size, way 63 for the 16KB or 32KB cache size). That is, when one of the normal victim index fields is incremented past the last way of the cache, it wraps back to the value of the NFLOOR field of the associated victim limit register.
User’s Manual Preliminary PPC440x5 CPU Core block -- 32 bytes), it takes sixteen such dcbt operations (one for each set) before the next way of the initial set will be targeted again. 7. Execute msync and then isync again, to guarantee that all of the dcbt operations have completed and updated the corresponding victim index fields. 8. Set the NFLOOR, TFLOOR, and TCEILING values to the desired indices for the operating normal and transient regions of the cache.
User’s Manual PPC440x5 CPU Core Preliminary Figure 4-3 and Figure 4-4 illustrate two of these examples of the use of the locking and transient mechanisms. Other configurations are possible, given the ability to program each of the victim limit fields to different relative values, although some configurations are not necessarily useful or practical. Figure 4-3.
User’s Manual Preliminary PPC440x5 CPU Core Figure 4-4. Cache Locking and Transient Mechanism (Example 2) Cache Set n 1 Way w2 NORMAL LINES Way TCEILING+1 Way TCEILING NORMAL/TRANSIENT LINES Way NFLOOR Way NFLOOR-1 TRANSIENT LINES Way TFLOOR Way TFLOOR-1 LOCKED LINES Way 0 Note 1: This example illustrates partitioning of the cache into locked, transient, and normal regions where the transient and normal regions partially overlap.
User’s Manual PPC440x5 CPU Core Preliminary The ICC also handles the execution of the PowerPC instruction cache management instructions, for touching (prefetching) or invalidating cache lines, or for flash invalidation of the entire cache. Resources for controlling and debugging the instruction cache operation are also provided. The rest of this section describes each of these functions in more detail. 4.2.
User’s Manual Preliminary PPC440x5 CPU Core the ICC will immediately present the request for the new cache line, such that it may be serviced immediately after the previous cache line read is completed. The ICC never aborts any PLB request once it has been made, except when a processor reset occurs while the PLB request is being made.
User’s Manual PPC440x5 CPU Core Preliminary lines beyond the one in progress at the time that the ICC determines that it needs to request a new line will be abandoned.
User’s Manual Preliminary PPC440x5 CPU Core At this point, software may begin executing the instruction at addr1 and be guaranteed that the new instruction will be recognized. 4.2.3.2 Instruction Cache Synonyms A synonym is a cache line that is associated with the same real address as another cache line that is in the cache array at the same time.
User’s Manual PPC440x5 CPU Core Preliminary Alternatively, software can execute an iccci instruction, which flash invalidates the entire instruction cache without regard to the addresses with which the cache lines are associated. 4.2.4 Instruction Cache Control and Debug The PPC440x5 core provides various registers and instructions to control instruction cache operation and to help debug instruction cache problems. 4.2.4.
User’s Manual Preliminary PPC440x5 CPU Core PRE 0 1 DSTG 2 3 4 5 9 10 11 12 CRPE DTB GDCBT ICSLC 15 16 17 18 19 22 23 24 GICBT FLSTA DAPUIB 27 28 29 30 31 ICSLT Figure 4-5.
User’s Manual PPC440x5 CPU Core Preliminary Force Load/Store Alignment 23 FLSTA 30:31 See Load and Store Alignment on page 117. Reserved 24:27 28:29 0 No Alignment exception on integer storage access instructions, regardless of alignment 1 An alignment exception occurs on integer storage access instructions if data address is not on an operand boundary. ICSLC ICSLT Instruction Cache Speculative Line Count Number of additional lines (0–3) to fill on instruction fetch miss.
User’s Manual Preliminary PPC440x5 CPU Core Data Cache U-bit Parity Error Insert 13 DCUPEI 14 DCMPEI 0 record even parity (normal) 1 record odd parity (simulate parity error) Data Cache Modified-bit Parity Error Insert 0 record even parity (normal) 1 record odd parity (simulate parity error) Force Cache Operation Miss 15 FCOM 16:19 MMUPEI 0 normal operation 1 cache ops appear to miss the cache Memory Management Unit Parity Error Insert 0 record even parity (normal) 1 record odd parity (simulat
User’s Manual PPC440x5 CPU Core Preliminary When being used for these latter purposes, it is important that the icbt instruction deliver a deterministic result, namely the guaranteed establishment in the cache of the specified line. Accordingly, the PPC440x5 core provides a field in the CCR0 register that can be used to cause the icbt instruction to operate in this manner.
User’s Manual Preliminary PPC440x5 CPU Core mficdbdr regC mficdbtrh regD mficdbtrl regE # move instruction information into GPR C # move high portion of tag into GPR D # move low portion of tag into GPR E The following figures illustrate the ICDBDR, ICDBTRH, and ICDBTRL. 0 31 Figure 4-7. Instruction Cache Debug Data Register (ICDBDR) 0:31 Instruction machine code from instruction cache TPAR TEA 0 23 24 25 26 27 28 V 31 DAPAR Figure 4-8.
User’s Manual PPC440x5 CPU Core Preliminary Translation ID (TID) Disable 23 TD 0 TID enable 1 TID disable 24:31 TID Translation ID TID Disable field for the memory page associated with the cache line read by icread. TID field portion of the virtual address associated with the cache line read by icread. 4.2.4.6 Instruction Cache Parity Operations The instruction cache contains parity bits and multi-hit detection hardware to protect against soft data errors.
User’s Manual Preliminary PPC440x5 CPU Core There are 10 parity bits stored in the RAM cells of each instruction cache line. Two of those bits hold the parity for the tag information, and the remaining 8 bits hold the parity for each of the 8 32-bit instruction words in the line. (There are two parity bits for the tag data because the parity is calculated for alternating bits of the tag field, to guard against a single particle strike event that upsets two adjacent bits.
User’s Manual PPC440x5 CPU Core Preliminary support direct attachment to 32-bit and 64-bit PLB subsystems, as well as 128-bit PLB subsystems. The DCC handles frequency synchronization between the PPC440x5 core and the PLB, and can operate at any ratio of n:1, n:2, and n:3, where n is an integer greater than the corresponding denominator.
User’s Manual Preliminary PPC440x5 CPU Core Once a data cache line read request has been made, the entire line read will be performed and the line will be written into the data cache, regardless of whether or not the instruction stream branches (or is interrupted) away from the instruction which prompted the initial line read request.
User’s Manual PPC440x5 CPU Core Preliminary The load and store string and multiple instructions are performed using one memory access for each four bytes, unless and until an access would cross an aligned quadword boundary.
User’s Manual Preliminary PPC440x5 CPU Core 4.3.1.3 Store Operations The processing of store instructions in the DCC is affected by several factors, including the caching inhibited (I), write-through (W), and guarded (G) storage attributes, as well as whether or not the allocation of data cache lines is enabled for cacheable store misses.
User’s Manual PPC440x5 CPU Core Preliminary A given sequence of two store operations may only be gathered together if the targeted bytes are contained within the same aligned quadword of memory, and if they are contiguous with respect to each other. Subsequent store operations may continue to be gathered with the previously gathered sequence, subject to the same two rules (same aligned quadword and contiguous with the collection of previously gathered bytes).
User’s Manual Preliminary PPC440x5 CPU Core Table 4-5 summarizes how the various storage attributes and other circumstances affect the DCC behavior on store accesses. Table 4-5.
User’s Manual PPC440x5 CPU Core Preliminary set instead of just the one corresponding dirty bit). When a data cache line is flushed, the type of request made to the data write PLB interface depends upon which dirty bits associated with the line are set, and the state of the CCR1[FFF] bit. If the CCR1[FFF] bit is set, the request will always be for an entire 32-byte line.
User’s Manual Preliminary PPC440x5 CPU Core 4.3.1.6 Data Write PLB Interface Requests When a PLB write request results from a data cache line flush, the specific type and size of the request is as described in Line Flush Operations on page 121.
User’s Manual PPC440x5 CPU Core Preliminary 4.3.1.7 Storage Access Ordering In general, the DCC can perform load and store operations out-of-order with respect to the instruction stream. That is, the memory accesses associated with a sequence of load and store instructions may be performed in memory in an order different from that implied by the order of the instructions. For example, loads can be processed ahead of earlier stores, or stores can be processed ahead of earlier loads.
User’s Manual Preliminary PPC440x5 CPU Core 4.3.3 Data Cache Control and Debug The PPC440x5 core provides various registers and instructions to control data cache operation and to help debug data cache problems. 4.3.3.1 Data Cache Management and Debug Instruction Summary For detailed descriptions of the instructions summarized in this section, see Instruction Set on page 249 In the instruction descriptions, the term “block” describes the unit of storage operated on by the cache block instructions.
User’s Manual PPC440x5 CPU Core Preliminary 4.3.3.2 Core Configuration Register 0 (CCR0) The CCR0 register controls the behavior of the dcbt instruction, the handling of misaligned memory accesses, and the store gathering mechanism. The CCR0 register also controls various other functions within the PPC440x5 core that are unrelated to the data cache. Each of these functions is discussed in more detail in the related sections of this manual.
User’s Manual Preliminary PPC440x5 CPU Core the specified cache line in the data cache (assuming that a TLB entry for the referenced memory page exists and has read permission, and that the caching inhibited storage attribute is not set). The cache line fill associated with such a guaranteed dcbt will occur regardless of any potential instruction execution-stalling circumstances within the DCC.
User’s Manual PPC440x5 CPU Core Preliminary The following figures illustrate the DCDBTRH and DCDBTRL. TERA TRA 0 23 24 25 27 28 31 V Figure 4-10. Data Cache Debug Tag Register High (DCDBTRH) Bits 0:23 of the lower 32 bits of the 36-bit real address associated with the cache line read by dcread. 0:23 TRA Tag Real Address 24 V 0 Cache line is not valid. 1 Cache line is valid. Cache Line Valid 25:27 28:31 The valid indicator for the cache line read by dcread.
User’s Manual Preliminary PPC440x5 CPU Core 4.3.3.6 Data Cache Parity Operations The data cache contains parity bits and multi-hit detection hardware to protect against soft data errors. Both the data cache tags and data are protected. Data cache lines consist of a tag field, 256 bits of data, 4 modified (dirty) bits, 4 user attribute (U) bits, and 39 parity bits. The tag field is stored in CAM (Content Addressible Memory) cells, while the data and parity bits are stored in normal RAM cells.
User’s Manual PPC440x5 CPU Core Preliminary MCSR[DCSP] and MCSR[DCFP] indicate what type of data cache operation caused a parity exception. One of the two bits will be set if a parity error is detected in the data cache, along with MCSR[MCS]. See Machine Check Interrupts on page 161. MCSR[DCSP] is set if a parity error is detected during these search operations: 1. Multi-hit parity errors on any instruction that does a CAM lookup 2. Tag or data parity errors on load instructions 3.
User’s Manual Preliminary PPC440x5 CPU Core If the CCR1[DCMPEI] bit is set, the parity for any modified (dirty) bits that are written, either during the process of a line fill or by execution of a store instruction or dcbz, is set to odd parity. If the CCR1[FFF] bit is also set in addition to CCR1[DCMPEI], then the parity for all four modified (dirty) bits is set to odd parity.
User’s Manual PPC440x5 CPU Core Page 132 of 589 Preliminary cache.fm.
User’s Manual Preliminary PPC440x5 CPU Core 5. Memory Management The PPC440x5 supports a uniform, 4 gigabyte (GB) effective address (EA) space, and a 64GB (36-bit) real address (RA) space. The PPC440x5 memory management unit (MMU) performs address translation between effective and real addresses, as well as protection functions.
User’s Manual PPC440x5 CPU Core Preliminary • Memory coherence required (M) storage attribute Because the PPC440x5 does not provide hardware support for multiprocessor coherence, the memory coherence required storage attribute has no effect.
User’s Manual Preliminary PPC440x5 CPU Core Maintenance of TLB entries is under software control. System software determines the TLB entry replacement strategy and the format and use of any page table information. A TLB entry contains all of the information required to identify the page, to specify the address translation, to control the access permissions, and to designate the storage attributes.
User’s Manual PPC440x5 CPU Core Preliminary Table 5-1. TLB Entry Fields (continued) TLB Word Bit Field Description Address Translation Fields 1 0:21 1 22:23 1 28:31 RPN Real Page Number (variable size, from 4 - 22 bits) Bits 0:n–1 of the RPN field are used to replace bits 0:n–1 of the effective address to produce a portion of the real address for the storage access (where n = 32–log2(page size in bytes) and page size is specified by the SIZE field of the TLB entry).
User’s Manual Preliminary PPC440x5 CPU Core Table 5-1. TLB Entry Fields (continued) TLB Word Bit Field Description Memory Coherence Required (1 bit) See Memory Coherence Required (M) on page 146. 2 22 M 0 The page is not memory coherence required. 1 The page is memory coherence required. Note that the PPC440x5 does not support multiprocessing, and thus all storage accesses will behave as if M=0.
User’s Manual PPC440x5 CPU Core Preliminary Table 5-1. TLB Entry Fields (continued) TLB Word Bit Field Description Supervisor State Read Enable (1 bit) See Read Access on page 143. 2 31 SR 0 Load operations and the dcbt, dcbtst, dcbst, dcbf, icbt, and icbi instructions are not permitted from this page when MSR[PR]=0 and will cause a Read Access Control exception. Except for the dcbt, dcbtst, and icbt instructions, a Data Storage interrupt will occur (see Table 5-4 on page 144).
User’s Manual Preliminary PPC440x5 CPU Core space, allowing user mode programs running with MSR[IS,DS] set to 1 to access them (system library routines, for example, which may be shared by multiple user mode and/or supervisor mode programs). System-level code wishing to use these areas would have to first set the corresponding MSR[IS,DS] field in order to use the application-level TLB entries, or there would have to be alternative system-level TLB entries set up.
User’s Manual PPC440x5 CPU Core Preliminary Figure 5-1 illustrates the criteria for a virtual address to match a specific TLB entry, while Table 5-2 defines the page sizes associated with each SIZE field value, and the associated comparison of the effective address to the EPN field.
User’s Manual Preliminary PPC440x5 CPU Core The Real Page Number (RPN) and Extended Real Page Number (ERPN) fields of the matching TLB entry provide the page number portion of the real address. Let n=32–log2(page size in bytes) where page size is specified by the SIZE field of the matching TLB entry.
User’s Manual PPC440x5 CPU Core Preliminary Table 5-3.
User’s Manual Preliminary PPC440x5 CPU Core store operation is attempted in user mode to a page for which the UW access control bit is 0, then a Write Access Control exception occurs. If the instruction is an stswx with string length 0, then no interrupt is taken and no operation is performed (see Access Control Applied to Cache Management Instructions on page 143). For all other store operations, execution of the instruction is suppressed and a Data Storage interrupt is taken.
User’s Manual PPC440x5 CPU Core Preliminary • dcbz instructions are treated as stores with respect to access control since they actually change the data in a cache block. As such, they can cause Write Access Control exception type Data Storage interrupts.
User’s Manual Preliminary PPC440x5 CPU Core Table 5-4. Access Control Applied to Cache Management Instructions Read Protection Violation Exception? Write Protection Violation Exception? icbt Yes1 No iccci No No Instruction 1. dcbt, dcbtst, or icbt may cause a Read Access Control exception but will not result in a Data Storage interrupt 5.6 Storage Attributes Each TLB entry specifies a number of storage attributes for the memory page with which it is associated.
User’s Manual PPC440x5 CPU Core Preliminary See Instruction and Data Caches on page 95 for more information on the handling of accesses to caching inhibited storage. 5.6.3 Memory Coherence Required (M) The memory coherence required (M) storage attribute is defined by the architecture to support cache and memory coherency within multiprocessor shared memory systems.
User’s Manual Preliminary PPC440x5 CPU Core which means that the bytes are arranged with the most-significant byte at the lowest-numbered memory address. The operands in a memory page with E=1 are arranged with little-endian byte ordering, which means that the bytes are arranged with the least-significant byte at the lowest-numbered address. See Byte Ordering on page 42 for a more detailed explanation of big-endian and little-endian byte ordering. 5.6.
User’s Manual PPC440x5 CPU Core Preliminary 5.7.1 Memory Management Unit Control Register (MMUCR) The MMUCR is written from a GPR using mtspr, and can be read into a GPR using mfspr. In addition, the MMUCR[STID] is updated with the TID field of the selected TLB entry when a tlbre instruction is executed. Conversely, the TID field of the selected TLB entry is updated with the value of the MMUCR[STID] field when a tlbwe instruction is executed.
User’s Manual Preliminary PPC440x5 CPU Core Store Without Allocate (SWOA) Field Performance for certain applications can be affected by the allocation of cache lines on store misses. If the store accesses for a particular application are distributed sparsely in memory, and if the data is typically not re-used after having been stored, then performance may be improved by avoiding the latency and bus bandwidth associated with filling the entire cache line containing the bytes being stored.
User’s Manual PPC440x5 CPU Core Preliminary program to remove a locked line from the cache. The locking and unlocking of cache lines is generally a supervisor mode function, as the supervisor has access to the various mechanisms which control the cache locking mechanism (e.g., the Data Cache Victim Limit (DVLIM) and Instruction Cache Victim Limit (IVLIM) registers, and the MMUCR).
User’s Manual Preliminary PPC440x5 CPU Core Search Translation ID (STID) Field The STID field is used by the tlbsx[.] instruction to designate the process identifier value to be compared with the TID field of the TLB entries. For instruction fetch and data storage accesses and cache management operations, the TID field of the TLB entries is compared with the value in the PID register (see Process ID (PID) on page 151). For tlbsx[.
User’s Manual PPC440x5 CPU Core Preliminary The instruction shadow TLB (ITLB) contains four entries, while the data shadow TLB (DTLB) contains eight. There is no latency associated with accessing the shadow TLB arrays, and instruction execution continues in a pipelined fashion as long as the requested address is found in the shadow TLB. If the requested address is not found in the shadow TLB, the instruction fetch or data storage access is automatically stalled while the address is looked up in the UTLB.
User’s Manual Preliminary PPC440x5 CPU Core is the Data Exception Address Register (DEAR), which provides the exception-causing address for Data TLB Error and Data Storage interrupts. Finally, the Exception Syndrome Register (ESR) provides bits to differentiate amongst the various exception types which may cause a particular interrupt type. See Chapter 6, “Interrupts and Exceptions.” for more information on these mechanisms.
User’s Manual PPC440x5 CPU Core Preliminary TLB Word 0 (WS=0) 0 21 22 EPN V 23 24 TS 27 28 SIZE 39 31 32 TID TPAR TLB Word 1 (WS=1) 21 22 23 24 0 27 28 PAR1 RPN 31 ERPN TLB Word 2 (WS=2) 0 1 PAR2 15 16 17 2 140 18 19 20 21 22 23 24 U0 U1 U2 U3 W I M G E 25 26 27 28 29 30 31 UX UW UR SX SW SR Figure 5-5. TLB Entry Word Definitions 5.9.
User’s Manual Preliminary PPC440x5 CPU Core Execute, Read and Write Access Control exceptions may be used to allow software to maintain reference and change information for a TLB entry and for its associated memory page. The following description explains one way in which system software can maintain such reference and change information. The TLB entry is originally written into the TLB with its access control bits (UX, SX, UR, SR, UW, and SW) off.
User’s Manual PPC440x5 CPU Core Preliminary 2. MSR[ME] = 1, so the CPU vectors to the machine check handler (i.e takes the machine check interrupt) and resets the MSR[ME] bit. Note that even though the parity error causes an asynchronous interrupt, that interrupt is guaranteed to be taken before the tlbre instruction completes if the CCR0[PRE] (Parity Recoverability Enable) is set, and so the target register (RT) of the tlbre will not be updated. 3.
User’s Manual Preliminary PPC440x5 CPU Core tlbwe Rs,Ra,2 isync mtspr CCR1, Rz isync tlbre RT,RA,WS mmu.fm.
User’s Manual PPC440x5 CPU Core Page 158 of 589 Preliminary mmu.fm.
User’s Manual Preliminary PPC440x5 CPU Core 6. Interrupts and Exceptions This chapter begins by defining the terminology and classification of interrupts and exceptions in “Overview” and “Interrupt Classes”. Interrupt Processing on page 162 explains in general how interrupts are processed, including the requirements for partial execution of instructions. Several registers support interrupt handling and control. Interrupt Processing Registers on page 165 describes these registers.
User’s Manual PPC440x5 CPU Core Preliminary Synchronous, precise interrupts are those that precisely indicate the address of the instruction causing the exception that generated the interrupt; or, for certain synchronous, precise interrupt types, the address of the immediately following instruction.
User’s Manual Preliminary PPC440x5 CPU Core • No instruction following the instruction addressed by SRR0 or CSRR0 has executed. The only synchronous, imprecise interrupts in the PPC440x5 core are the “special cases” of “delayed” interrupts, which can result when certain kinds of exceptions occur while the corresponding interrupt type is disabled. The first of these is the Floating-Point Enabled exception type Program interrupt.
User’s Manual PPC440x5 CPU Core Preliminary properly be classified as either synchronous or asynchronous, nor as precise or imprecise. They also do not belong to either the critical or the non-critical interrupt class, but instead have associated with them a unique pair of save/restore registers, Machine Check Save/Restore Registers 0/1 (MCSRR0/1). Architecturally, the following general rules apply for Machine Check interrupts: 1.
User’s Manual Preliminary PPC440x5 CPU Core Interrupt processing consists of saving a small part of the processor state in certain registers, identifying the cause of the interrupt in another register, and continuing execution at the corresponding interrupt vector location. When an exception exists and the corresponding interrupt type is enabled, the following actions are performed, in order: 1.
User’s Manual PPC440x5 CPU Core Preliminary 6.3.1 Partially Executed Instructions In general, the architecture permits load and store instructions to be partially executed, interrupted, and then to be restarted from the beginning upon return from the interrupt.
User’s Manual Preliminary PPC440x5 CPU Core Decrementer Fixed-Interval Timer Watchdog Timer Debug (Unconditional Debug Event) 2. Unaligned elementary load or store, or any load or store multiple or string: All of the above listed under item 1, plus the following: Alignment Data Storage (if the access crosses a memory page boundary) Debug (Data Address Compare, Data Value Compare) 6.
User’s Manual PPC440x5 CPU Core 14 CE Preliminary Critical Interrupt Enable 0 Critical Input and Watchdog Timer interrupts are disabled. 1 Critical Input and Watchdog Timer interrupts are enabled. 15 Reserved 16 EE External Interrupt Enable 0 External Input, Decrementer, and Fixed Interval Timer interrupts are disabled. 1 External Input, Decrementer, and Fixed Interval Timer interrupts are enabled.
User’s Manual Preliminary 28:31 PPC440x5 CPU Core Reserved 6.4.2 Save/Restore Register 0 (SRR0) SRR0 is an SPR that is used to save machine state on non-critical interrupts, and to restore machine state when an rfi is executed. When a non-critical interrupt occurs, SRR0 is set to an address associated with the process which was executing at the time. When rfi is executed, instruction execution returns to the address in SRR0.
User’s Manual PPC440x5 CPU Core Preliminary EE WE 0 FP FE0 IS DE 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 CE PR ME DWE FE1 31 DS Figure 6-3. Save/Restore Register 1 (SRR1) 0:31 Copy of the MSR at the time of a non-critical interrupt. 6.4.4 Critical Save/Restore Register 0 (CSRR0) CSRR0 is an SPR that is used to save machine state on critical interrupts, and to restore machine state when an rfci is executed.
User’s Manual Preliminary PPC440x5 CPU Core Programming Note: An MSR bit that is reserved may be altered by rfci, consistent with the value being restored from CSRR1. CSRR1 can be written from a GPR using mtspr, and can be read into a GPR using mfspr. EE WE 0 FP FE0 DE IS 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 CE PR ME DWE FE1 31 DS Figure 6-5. Critical Save/Restore Register 1 (CSRR1) 0:31 Copy of the MSR when a critical interrupt is taken 6.4.
User’s Manual PPC440x5 CPU Core Preliminary Programming Note: An MSR bit that is reserved may be altered by rfmci, consistent with the value being restored from MCSRR1. MCSRR1 can be written from a GPR using mtspr, and can be read into a GPR using mfspr. EE WE 0 FP FE0 IS DE 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 CE PR ME DWE FE1 31 DS Figure 0-1. Machine Check Save/Restore Register 1 (MCSRR1) 0:31 Copy of the MSR at the time of a machine check interrupt. 6.4.
User’s Manual Preliminary PPC440x5 CPU Core Figure 6-8 shows the IVOR field definitions, while Table 6-1 identifies the specfic IVOR register associated with each interrupt type. IVO 0 15 16 27 28 31 Figure 6-8. Interrupt Vector Offset Registers (IVOR0–IVOR15) 0:15 16:27 Reserved IVO 28:31 Interrupt Vector Offset Reserved Table 6-1.
User’s Manual PPC440x5 CPU Core Preliminary IVP 0 15 16 31 Figure 6-9. Interrupt Vector Prefix Register (IVPR) 0:15 IVP Interrupt Vector Prefix 16:31 Reserved 6.4.11 Exception Syndrome Register (ESR) The ESR provides a syndrome to differentiate between the different kinds of exceptions that can generate the same interrupt type.
User’s Manual Preliminary 7 8 PPC440x5 CPU Core FP Floating Point Operation 0 Exception was not caused by a floating point instruction. 1 Exception was caused by a floating point instruction. ST Store Operation 0 Exception was not caused by a store-type storage access or cache management instruction. 1 Exception was caused by a store-type storage access or cache management instruction. 9 Reserved 10:11 DLK Data Storage Interrupt—Locking Exception 00 Locking exception did not occur.
User’s Manual PPC440x5 CPU Core 29:31 Preliminary Program Interrupt—Condition Register Field If ESR[PCRE]=1, this field indicates which CR field was to be updated by the floating-point instruction which caused the exception. PCRF This is an implementation-dependent field of the ESR and is not part of the PowerPC Book-E Architecture. This field is only defined for a Floating-Point Enabled exception type Program interrupt, and then only when ESR[PIE] is 0. 6.4.
User’s Manual Preliminary PPC440x5 CPU Core 5 ICP Instruction Cache Parity Error 0 Exception not caused by I-cache parity error 1 Exception caused by I-cache parity error 6 DCSP Data Cache Search Parity Error 0 Exception not caused by DCU Search parity error 1 Exception caused by DCU Search parity error Set if and only If the DCU parity error was discovered during a DCU Search operation. See Data Cache Parity Operations on page 129.
User’s Manual PPC440x5 CPU Core Preliminary IVOR6 Notes DBCR0/TCR Mask Bit MSR Mask Bit(s) ESR (See Note 4) Critical Exception Type Synchronous, Imprecise Interrupt Type Synchronous, Precise IVOR Asynchronous Table 6-2.
User’s Manual Preliminary PPC440x5 CPU Core Table Notes 1. Although it is not specified as part of Book E, it is common for system implementations to provide, as part of the interrupt controller, independent mask and status bits for the various sources of Critical Input and External Input interrupts. 2. Machine Check interrupts are not classified as asynchronous nor synchronous.
User’s Manual PPC440x5 CPU Core Preliminary 6.5.1 Critical Input Interrupt A Critical Input interrupt occurs when no higher priority exception exists, a Critical Input exception is presented to the interrupt mechanism, and MSR[CE] = 1. A Critical Input exception is caused by the activation of an asynchronous input to the PPC440x5 core.
User’s Manual Preliminary PPC440x5 CPU Core tion, regardless of the state of the MSR[ME] bit. If MSR[ME] is 1 when the Instruction Machine Check exception is presented to the interrupt mechanism, then execution of the instruction associated with the exception will be suppressed, a Machine Check interrupt will occur, and the interrupt processing registers will be updated as described on Page 179.
User’s Manual PPC440x5 CPU Core Preliminary Machine Check Save/Restore Register 1 (MCSRR1) Set to the contents of the MSR at the time of the interrupt. Machine State Register (MSR) All MSR bits set to 0. Exception Syndrome Register (ESR) MCI Set to 1 for an Instruction Machine Check exception; otherwise left unchanged. All other defined ESR bits are set to 0 for an Instruction Machine Check exception; otherwise they are left unchanged.
User’s Manual Preliminary PPC440x5 CPU Core See Machine Check Interrupts on page 161 for more information on the handling of Machine Check interrupts within the PPC440x5 core. Programming Note: If a Instruction Synchronous Machine Check exception occurs (i.e. an error occurs on the PLB transfer that is intended to fill a line in the instruction cache, any data associated with the exception will not be placed into the instruction cache.
User’s Manual PPC440x5 CPU Core Preliminary instructions not with the execution of instructions. Data Storage exceptions and Data TLB Miss exceptions are associated with the execution of instruction cache management instructions, as well as with the execution of load, store, and data cache management instructions.
User’s Manual Preliminary PPC440x5 CPU Core • dcbtst For all other instructions, if a Data Storage exception occurs, then execution of the instruction causing the exception is suppressed, a Data Storage interrupt is generated, the interrupt processing registers are updated as indicated below (all registers not listed are unchanged), and instruction execution resumes at address IVPR[IVP] || IVOR2[IVO] || 0b0000.
User’s Manual PPC440x5 CPU Core Preliminary AP Set to 1 if the instruction causing the interrupt is an auxiliary processor load or store; otherwise set to 0. BO Set to 1 if the instruction caused a Byte Ordering exception; otherwise set to 0.
User’s Manual Preliminary PPC440x5 CPU Core Machine State Register (MSR) CE, ME, DE Unchanged. All other MSR bits set to 0. Exception Syndrome Register (ESR) BO Set to 0. MCI Unchanged. All other defined ESR bits are set to 0. 6.5.5 External Input Interrupt An External Input interrupt occurs when no higher priority exception exists, an External Input exception is presented to the interrupt mechanism, and MSR[EE] = 1.
User’s Manual PPC440x5 CPU Core Preliminary • An integer load or store instruction that references a data storage operand that is not aligned on an operand-sized boundary, when CCR0[FLSTA] is 1. Load and store multiple instructions are considered to reference word operands, and hence word-alignment is required for the target address of these instructions when CCR0[FLSTA] is 1.
User’s Manual Preliminary PPC440x5 CPU Core Exception Syndrome Register (ESR) FP Set to 1 if the instruction causing the interrupt is a floating-point load or store; otherwise set to 0. ST Set to 1 if the instruction causing the interrupt is a store, dcbz, or dcbi instruction; otherwise set to 0. AP Set to 1 if the instruction causing the interrupt is an auxiliary processor load or store; otherwise set to 0. All other defined ESR bits are set to 0. 6.5.
User’s Manual PPC440x5 CPU Core Preliminary exception will cause a Debug interrupt to occur, rather than a Program interrupt. See Chapter 8, “Debug Facilities” for more information on Trap debug events.
User’s Manual Preliminary PPC440x5 CPU Core was already being presented to the interrupt mechanism at the time MSR[FE0,FE1] was changed from 0 to a non-zero value, SRR0 is set to the address of the instruction that would have executed after the MSR-changing instruction.
User’s Manual PPC440x5 CPU Core Preliminary Programming Note: The ESR[PCRE,PCMP,PCRF] fields are provided to assist the Program interrupt handler with the emulation of part of the function of the various floating-point CR-updating instructions, when any of these instructions cause a precise (“non-delayed”) Floating-Point Enabled exception type Program interrupt.
User’s Manual Preliminary PPC440x5 CPU Core Save/Restore Register 1 (SRR1) Set to the contents of the MSR at the time of the interrupt. Machine State Register (MSR) CE, ME, DE Unchanged. All other MSR bits set to 0. 6.5.
User’s Manual PPC440x5 CPU Core Preliminary Save/Restore Register 1 (SRR1) Set to the contents of the MSR at the time of the interrupt. Machine State Register (MSR) CE, ME, DE Unchanged. All other MSR bits set to 0. Programming Note: Software is responsible for clearing the Decrementer exception status by writing to TSR[DIS], prior to reenabling MSR[EE], in order to avoid another, redundant Decrementer interrupt. 6.5.
User’s Manual Preliminary PPC440x5 CPU Core Critical Save/Restore Register 0 (CSRR0) Set to the effective address of the next instruction to be executed. Critical Save/Restore Register 1 (CSRR1) Set to the contents of the MSR at the time of the interrupt. Machine State Register (MSR) ME Unchanged. All other MSR bits set to 0.
User’s Manual PPC440x5 CPU Core Preliminary Save/Restore Register 0 (SRR0) Set to the effective address of the instruction causing the Data TLB Error interrupt. Save/Restore Register 1 (SRR1) Set to the contents of the MSR at the time of the interrupt. Machine State Register (MSR) CE, ME, DE Unchanged. All other MSR bits set to 0.
User’s Manual Preliminary PPC440x5 CPU Core When an Instruction TLB Error interrupt occurs, the processor suppresses the execution of the instruction causing the Instruction TLB Miss exception, the interrupt processing registers are updated as indicated below (all registers not listed are unchanged), and instruction execution resumes at address IVPR[IVP] || IVOR14[IVO] || 0b0000. Save/Restore Register 0 (SRR0) Set to the effective address of the instruction causing the Instruction TLB Error interrupt.
User’s Manual PPC440x5 CPU Core Preliminary specified by the various debug facility registers. This exception can occur regardless of debug mode, and regardless of the value of MSR[DE]. Branch Taken (BRT) exception A BRT Debug exception occurs when BRT debug events are enabled (DBCR0[BRT]=1) and execution is attempted of a branch instruction for which the branch conditions are met.
User’s Manual Preliminary PPC440x5 CPU Core Programming Note: It is a programming error for software to enable internal debug mode (by setting DBCR0[IDM] to 1) while Debug exceptions are already present in the DBSR. Software must first clear all DBSR Debug exception status (that is, all fields except IDE, MRR, IAC12ATS, and IAC34ATS) before setting DBCR0[IDM] to 1. If a stwcx.
User’s Manual PPC440x5 CPU Core Preliminary Since the ICMP Debug exception does not suppress the execution of the instruction causing the exception, but rather allows it to complete before causing the interrupt, the behavior of the interrupt is different in the special case where the instruction causing the ICMP Debug exception is itself setting MSR[DE] to 0. In this case, the interrupt will be delayed and will occur if and when MSR[DE] is again set to 1, assuming DBSR[ICMP] is still set.
User’s Manual Preliminary PPC440x5 CPU Core 6.6 Interrupt Ordering and Masking It is possible for multiple exceptions to exist simultaneously, each of which could cause the generation of an interrupt. Furthermore, the PowerPC Book-E architecture does not provide for the generation of more than one interrupt of the same class (critical or non-critical) at a time.
User’s Manual PPC440x5 CPU Core Preliminary This prevents any asynchronous interrupts, as well as (in the case of MSR[DE]) any Debug interrupts (which include both synchronous and asynchronous types). • Branching (or sequential execution) to addresses not mapped by the TLB, or mapped without execute access permission This prevents Instruction Storage and Instruction TLB Error interrupts.
User’s Manual Preliminary PPC440x5 CPU Core interrupt may have occurred from within a non-critical class interrupt handler, prior to the non-critical class interrupt handler having saved SRR0 and SRR1. Therefore, within the critical class interrupt handler, both pairs of save/restore registers may contain data that is necessary to the system software.
User’s Manual PPC440x5 CPU Core Preliminary 6.7 Exception Priorities PowerPC Book-E requires all synchronous (precise and imprecise) interrupts to be reported in program order, as implied by the sequential execution model. The one exception to this rule is the case of multiple synchronous imprecise interrupts.
User’s Manual Preliminary PPC440x5 CPU Core Only applies to the defined 64-bit load, store, and cache management instructions, which are not recognized by the PPC440x5 core. 5. Program (Privileged Instruction) Only applies to the dcbi instruction, and only occurs if MSR[PR]=1. 6. Data TLB Error (Data TLB Miss exception) 7. Data Storage (all exception types except Byte Ordering exception) 8. Alignment (Alignment exception) 9. Debug (DAC or DVC exception) 10. Debug (ICMP exception) 6.7.
User’s Manual PPC440x5 CPU Core Preliminary 4. Program (Illegal Instruction exception) This exception will occur if no auxiliary processor unit is attached to the PPC440x5 core, or if the particular allocated load or store instruction is not recognized by the attached auxiliary processor. 5. Program (Privileged Instruction exception) This exception will occur if an attached auxiliary processor unit recognizes the instruction and indicates that the instruction is privileged, but MSR[PR]=1. 6.
User’s Manual Preliminary PPC440x5 CPU Core This exception will occur if an attached floating-point unit recognizes and supports the instruction, floating-point instruction processing is enabled (MSR[FP]=1), and the instruction sets FPSCR[FEX] to 1. 8. Debug (ICMP exception) 6.7.
User’s Manual PPC440x5 CPU Core Preliminary instructions that are implemented within the PPC440x5 core. This list also covers the defined 64-bit privileged instructions, the tlbiva instruction, and the mfapidi instruction, all of which are not implemented by the PPC440x5 core. 1. Debug (IAC exception) 2. Instruction TLB Error (Instruction TLB Miss exception) 3. Instruction Storage (Execute Access Control exception) 4.
User’s Manual Preliminary PPC440x5 CPU Core 6.7.9 Exception Priorities for Branch Instructions The following list identifies the priority order of the exception types that may occur within the PPC440x5 core as the result of the attempted execution of a branch instruction. 1. Debug (IAC exception) 2. Instruction TLB Error (Instruction TLB Miss exception) 3. Instruction Storage (Execute Access Control exception) 4. Debug (BRT exception) 5. Debug (ICMP exception) 6.7.
User’s Manual PPC440x5 CPU Core Preliminary 4. Program (Illegal Instruction exception) Applies to all reserved instruction opcodes except the reserved-nop instruction opcodes. 5. Debug (ICMP exception) Only applies to the reserved-nop instruction opcodes. 6.7.
User’s Manual Preliminary PPC440x5 CPU Core 7. Timer Facilities The PPC440x5 provides four timer facilities: a time base, a Decrementer (DEC), a Fixed Interval Timer (FIT), and a Watchdog Timer.
User’s Manual PPC440x5 CPU Core Preliminary Software access to TBU and TBL is non-privileged for read but privileged for write, and hence different SPR numbers are used for reading than for writing. TBU and TBL are written using mtspr and read using mfspr. The period of the 64-bit time base is approximately 1462 years for a 400 MHz clock source. The time base value itself does not generate any exceptions, even when it wraps.
User’s Manual Preliminary lwz li mtspr mtspr mtspr PPC440x5 CPU Core Ry, lower Rz, 0 TBL,Rz TBU,Rx TBL,Ry # set GPR Rz to 0 # force TBL to 0 (thereby preventing wrap into TBU) # set TBU to initial value # set TBL to initial value 7.2 Decrementer (DEC) The DEC is a 32-bit privileged SPR that decrements at the same rate that the time base increments. The DEC is read and written using mfspr and mtspr, respectively.
User’s Manual PPC440x5 CPU Core Preliminary 0 31 Figure 7-5. Decrementer Auto-Reload (DECAR) 0:31 Copied to DEC at next time base clock when DEC = 1 and auto-reload is enabled (TCR[ARE] = 1). Decrementer auto-reload value Using mtspr to force the DEC to 0 does not cause a Decrementer exception and thus does not cause TSR[DIS] to be set.
User’s Manual Preliminary PPC440x5 CPU Core Table 7-1. Fixed Interval Timer Period Selection (continued) TCR[FP] Time Base Bit Period (Time Base Clocks) 0b11 TBL7 225 clocks Period (400 Mhz Clock) 83.9 ms When a Fixed Interval Timer exception occurs, the exception status is recorded by setting the Fixed interval Timer Interrupt Status (FIS) field of the TSR to 1.
User’s Manual PPC440x5 CPU Core Preliminary avoid another Watchdog Timer interrupt due to the same exception (unless TCR[WIE] is cleared instead). Watchdog Timer Interrupt on page 192 provides more information on the handling of Watchdog Timer interrupts. If TSR[WIS] is already 1 at the time of the next Watchdog Timer exception, then the action to take depends on the value of the Watchdog Reset Control (TRC) field of the TCR.
User’s Manual Preliminary PPC440x5 CPU Core Figure 7-6 illustrates the sequence of Watchdog Timer events which occurs according to this typical system usage. Watchdog Timer exception disabled; next exception sets TSR[ENW] so subsequent exception will set TSR[WIS]. Exception SW Loop TSR[ENW,WIS] = 0b00 Watchdog Timer exception enabled; next exception sets TSR[WIS] and causes TSR[ENW,WIS] = 0b10 interrupt if enabled by TCR[WIE] and MSR[CE].
User’s Manual PPC440x5 CPU Core WP 0 1 WIE 2 3 4 WRC Preliminary FP FIE 5 DIE 6 7 8 9 10 31 ARE Figure 7-7. Timer Control Register (TCR) WP Watchdog Timer Period 00 221 time base clocks 01 225 time base clocks 10 229 time base clocks 11 233 time base clocks 2:3 WRC Watchdog Timer Reset Control 00 No Watchdog Timer reset will occur. 01 Core reset 10 Chip reset 11 System reset 4 WIE Watchdog Timer Interrupt Enable 0 Disable Watchdog Timer interrupt. 1 Enable Watchdog Timer interrupt.
User’s Manual Preliminary ENW 0 PPC440x5 CPU Core WRS 1 WIS 2 FIS 3 4 5 6 31 DIS Figure 7-8. Timer Status Register (TSR) 0 ENW Enable Next Watchdog Timer Exception 0 Action on next Watchdog Timer exception is to set TSR[ENW] = 1. 1 Action on next Watchdog Timer exception is governed by TSR[WIS]. 1 WIS Watchdog Timer Interrupt Status 0 Watchdog Timer exception has not occurred. 1 Watchdog Timer exception has occurred.
User’s Manual PPC440x5 CPU Core Page 218 of 589 Preliminary timers.fm.
User’s Manual Preliminary PPC440x5 CPU Core 8. Debug Facilities The debug facilities of the PPC440x5 include support for several debug modes for debugging during hardware and software development, as well as debug events that allow developers to control the debug process. Debug registers control these debug modes and debug events. The debug registers may be accessed either through software running on the processor or through the JTAG debug port of the PPC440x5 core.
User’s Manual PPC440x5 CPU Core Preliminary page 159 for a description of the MSR and Debug interrupts). When a Debug interrupt occurs, special debugger software at the interrupt handler can check processor status and other conditions related to the debug event, as well as alter processor resources using all of the instructions defined for the PPC440x5. Internal debug mode relies on this interrupt handling software at the Debug interrupt vector to debug software problems.
User’s Manual Preliminary PPC440x5 CPU Core Debug wait mode is enabled by setting both MSR[DWE] and the debug wait mode enable within the JTAG controller to 1. Since MSR[DWE] is automatically cleared upon any interrupt, debug wait mode is temporarily disabled upon an interrupt, and then can be automatically re-enabled when returning from the interrupt due to the restoration of the MSR value upon the execution of an rfi, rfci, or rfmci instruction.
User’s Manual PPC440x5 CPU Core Preliminary Table 8-1. Debug Events Event Description Instruction Complete (ICMP) Caused by the successful completion of the execution of any instruction. Interrupt (IRPT) Caused by the generation of an interrupt. Unconditional (UDE) Caused by the assertion of an unconditional debug event request from the JTAG interface to the PPC440x5 core. 8.3.
User’s Manual Preliminary PPC440x5 CPU Core Note that the IAC range auto-toggle mechanism can “switch” the IAC range mode from inclusive to exclusive, and vice-versa. See IAC Range Mode Auto-Toggle Field on page 224. • Range exclusive comparison mode (DBCR1[IAC12M/IAC34M] = 0b11) In this mode, the IAC1 or IAC2 event occurs only if the instruction address is outside the range defined by the IAC1 and IAC2 register values, as follows: address < IAC1 or address ≥ IAC2.
User’s Manual PPC440x5 CPU Core Preliminary matches the IAC conditions and is in virtual address space 1 (MSR[IS] = 1). Note that in these latter two modes, in which the virtual address space of the instruction is considered, it is not the entire virtual address which is considered. The Process ID, which forms the final part of the virtual address, is not considered.
User’s Manual Preliminary PPC440x5 CPU Core status fields is summarized in Table 8-2 Table 8-2.
User’s Manual PPC440x5 CPU Core Preliminary interrupt has occurred imprecisely. On the other hand, if the IAC mode is set to either range inclusive or range exclusive mode, then IAC debug events cannot occur when operating in internal debug mode with MSR[DE] = 0, unless external debug mode and/or debug wait mode is also enabled.
User’s Manual Preliminary PPC440x5 CPU Core DAC Mode Field DBCR2[DAC12M] controls the comparison mode for the DAC1 and DAC2 events. There are four comparison modes supported by the PPC440x5: • Exact comparison mode (DBCR2[DAC12M] = 0b00) In this mode, the data address is compared to the value in the corresponding DAC register, and the DAC event occurs only if the comparison is an exact match.
User’s Manual PPC440x5 CPU Core Preliminary When the data address falls outside the specified range, either one or both of the DAC debug event bits corresponding to the operation type (read or write) will be set in the DBSR, as determined by which of the corresponding two DAC event enable bits are set in DBCR0.
User’s Manual Preliminary PPC440x5 CPU Core 8.3.2.2 DAC Debug Event Processing The behavior of the PPC440x5 upon a DAC debug event depends on the setting of DBCR2[DAC12A]. This field of DBCR2 controls whether DAC debug events are processed in a synchronous (DBCR2[DAC12A] = 0) or an asynchronous (DBCR2[DAC12A] = 1) fashion.
User’s Manual PPC440x5 CPU Core Preliminary counter will contain the address of that instruction, and that instruction’s execution will have been suppressed. Conversely, if the DAC debug event is processed after the completion of the instruction causing the event, then the program counter will contain the address of some instruction after the one which caused the event.
User’s Manual Preliminary PPC440x5 CPU Core dcbst, dcbf The dcbst and dcbf instructions are considered “loads” with respect to storage access control, since they do not change the contents of a given storage location. They may merely cause the data at that storage location to be moved from the data cache out to memory. However, in a debug environment, the fact that these instructions may lead to write operations on the external interface is typically the event of interest.
User’s Manual PPC440x5 CPU Core Preliminary Event on page 226 describes the DAC conditions. In addition to the DAC conditions, there are two DVC registers on the PPC440x5, DVC1 and DVC2. The DVC registers can be used to specify two independent, 4-byte data values, which are selectively compared against the data being accessed by a given load, store, or cache management instruction. When a DVC event occurs, the corresponding DBSR[DAC1R, DAC1W, DAC2R, DAC2W] bit is set.
User’s Manual Preliminary PPC440x5 CPU Core In this mode, at least one data byte lane that is enabled by a DVC byte enable field must be being accessed and must match the corresponding byte data value in the corresponding DVC1 or DVC2 register. • AND-OR comparison mode (DBCR2[DVC1M, DVC2M] = 0b11) In this mode, the four byte lanes of an aligned word are divided into two pairs, with byte lanes 0 and 1 being in one pair, and byte lanes 2 and 3 in the other pair.
User’s Manual PPC440x5 CPU Core Preliminary lswx, stswx DVC debug events do not occur for lswx or stswx instructions with a length of 0 (XER[TBC] = 0), since these instructions do not actually access storage. 8.3.4 Branch Taken (BRT) Debug Event BRT debug events occur when BRT debug events are enabled (DBCR0[BRT] = 1) and execution is attempted of a branch instruction for which the branch condition(s) are satisfied, such that the instruction stream will be redirected to the target address of the branch.
User’s Manual Preliminary PPC440x5 CPU Core 8.3.6 Return (RET) Debug Event RET debug events occur when RET debug events are enabled (DBCR0[RET] = 1) and execution is attempted of a return (rfi, rfci, or rfmci) instruction. When operating in external debug mode or debug wait mode, the occurrence of a RET debug event is recorded in DBSR[RET] and causes the instruction execution to be suppressed. The processor then enters the stop state and ceases the processing of instructions.
User’s Manual PPC440x5 CPU Core Preliminary that there is a special case of MSR[DE] = 1 at the time of the execution of the instruction causing the ICMP debug event, but that instruction itself sets MSR[DE] to 0. This special case is described in more detail in Debug Interrupt on page 195, in the subsection on the setting of CSRR0.
User’s Manual Preliminary PPC440x5 CPU Core 8.3.9 Unconditional Debug Event (UDE) UDE debug events occur when a debug tool asserts the unconditional debug event request via the JTAG interface. The UDE debug event is the only event which does not have a corresponding enable field in DBCR0. When operating in external debug mode or debug wait mode, the occurrence of a UDE debug event is recorded in DBSR[UDE] and causes the processor to enter the stop state and cease processing instructions.
User’s Manual PPC440x5 CPU Core Preliminary Table 8-3. Debug Event Summary (continued) External Debug Mode Debug Wait Mode Internal Debug Mode MSR DE Debug Events IAC DAC DVC BRT TRAP RET ICMP IRPT UDE Disabled Disabled Enabled 0 Note 2 Yes Yes No Yes Note 3 No Note 1 Yes Disabled Disabled Disabled — Yes Yes Yes Yes Yes Yes Note 4 yes Yes Table Notes 1.
User’s Manual Preliminary PPC440x5 CPU Core changing any of the debug facility register fields related to the DAC and/or DVC debug events, software must execute an msync instruction before making the changes, to ensure that all storage accesses complete using the old context of these register fields. 8.6.1 Debug Control Register 0 (DBCR0) DBCR0 is an SPR that is used to enable debug modes and events, reset the processor, and control timer operation when debugging.
User’s Manual PPC440x5 CPU Core Preliminary 9 IAC2 IAC 2 Debug Event 0 Disable IAC 2 debug event. 1 Enable IAC 2 debug event. 10 IAC3 IAC 3 Debug Event 0 Disable IAC 3 debug event. 1 Enable IAC 3 debug event. 11 IAC4 IAC 4 Debug Event 0 Disable IAC 4 debug event. 1 Enable IAC 4 debug event. 12 DAC1R Data Address Compare (DAC) 1 Read Debug Event 0 Disable DAC 1 read debug event. 1 Enable DAC 1 read debug event. 13 DAC1W DAC 1 Write Debug Event 0 Disable DAC 1 write debug event.
User’s Manual Preliminary PPC440x5 CPU Core IAC 1 Effective/Real 00 Effective (MSR[IS] = don’t care) 2:3 IAC1ER 01 Reserved 10 Virtual (MSR[IS] = 0) 11 Virtual (MSR[IS] = 1) IAC 2 User/Supervisor 00 Both 4:5 IAC2US 01 Reserved 10 Supervisor only (MSR[PR] = 0) 11 User only (MSR[PR] = 1) IAC 2 Effective/Real 00 Effective (MSR[IS] = don’t care) 6:7 IAC2ER 01 Reserved 10 Virtual (MSR[IS] = 0) 11 Virtual (MSR[IS] = 1) IAC 1/2 Mode 00 Exact match 8:9 IAC12M 01 Reserved 10 Range inclusive 11 Range exc
User’s Manual PPC440x5 CPU Core 31 IAC34AT Page 242 of 589 Preliminary IAC3/4 Auto-Toggle Enable 0 Disable IAC 3/4 auto-toggle 1 Enable IAC 3/4 auto-toggle debug.fm.
User’s Manual Preliminary PPC440x5 CPU Core 8.6.3 Debug Control Register 2 (DBCR2) DBCR2 is an SPR that is used to configure DAC and DVC debug events. DBCR2 can be written from a GPR using mtspr, and can be read into a GPR using mfspr. 0 1 DAC12M DAC2US DAC1US 2 3 4 DAC1ER 5 6 7 8 DAC2ER DVC1BE DVC1M 9 10 11 12 13 14 15 16 DAC12A 19 20 23 24 DVC2M 27 28 31 DVC2BE Figure 8-3.
User’s Manual PPC440x5 CPU Core Preliminary DVC 2 Mode 00 Reserved 14:15 01 AND all bytes enabled by DVC2BE DVC2M 10 OR all bytes enabled by DVC2BE 11 AND-OR pairs of bytes enabled by DVC2BE (0 AND 1) OR (2 AND 3) Reserved 16:19 20:23 DVC1BE DVC 1 Byte Enables 0:3 24:27 Reserved 28:31 DVC2BE DVC 2 Byte Enables 0:3 8.6.4 Debug Status Register (DBSR) The DBSR contains status on debug events as well as information on the type of the most recent reset.
User’s Manual Preliminary PPC440x5 CPU Core 6 IRPT Interrupt Debug Event 0 Event didn’t occur 1 Event occurred 7 TRAP Trap Debug Event 0 Event didn’t occur 1 Event occurred 8 IAC1 IAC 1 Debug Event 0 Event didn’t occur 1 Event occurred 9 IAC2 IAC 2 Debug Event 0 Event didn’t occur 1 Event occurred 10 IAC3 IAC 3 Debug Event 0 Event didn’t occur 1 Event occurred 11 IAC4 IAC 4 Debug Event 0 Event didn’t occur 1 Event occurred 12 DAC1R DAC 1 Read Debug Event 0 Event didn’t occur 1 Event oc
User’s Manual PPC440x5 CPU Core Preliminary 0 29 30 31 Figure 8-5. Instruction Address Compare Registers (IAC1–IAC4) 0:29 Instruction Address Compare (IAC) word address 30:31 Reserved 8.6.6 Data Address Compare Registers (DAC1–DAC2) The two DAC registers specify the addresses upon which DAC (and/or DVC) debug events should occur. Each of the DAC registers can be written from a GPR using mtspr, and can be read into a GPR using mfspr. 0 31 Figure 8-6.
User’s Manual Preliminary PPC440x5 CPU Core 8.6.8 Debug Data Register (DBDR) The DBDR can be used for communication between software running on the processor and debug tool hardware and software. The DBDR can be written from a GPR using mtspr, and can be read into a GPR using mfspr. 0 31 Figure 8-8. Debug Data Register (DBDR) 0:31 debug.fm.
User’s Manual PPC440x5 CPU Core Page 248 of 589 Preliminary debug.fm.
Preliminary PPC440x5 CPU Core User’s Manual 9. Instruction Set Descriptions of the PPC440x5 instructions follow. Each description contains the following elements: • Instruction names (mnemonic and full) • Instruction syntax • Instruction format diagram • Pseudocode description • Prose description • Registers altered Where appropriate, instruction descriptions list invalid instruction forms and exceptions, and provide programming notes. Table 9-1 summarizes the PPC440x5 instruction set by category.
PPC440x5 CPU Core User’s Manual Preliminary 9.1 Instruction Set Portability To support embedded real-time applications, the PPC440x5 core implements the defined instruction set of the Book-E Enhanced PowerPC Architecture, with the exception of those operations which are defined for 64-bit implementations only, and those which are defined as floating-point operations.
Preliminary PPC440x5 CPU Core User’s Manual These instruction fields contain values, such as opcodes, that cannot be altered. The instruction format diagrams specify the values of defined fields. • Variable These fields contain operands, such as general purpose register specifiers and immediate values, each of which may contain any one of a number of values. The instruction format diagrams specify the field names of variable fields. • Reserved Bits in a reserved field should be set to 0.
PPC440x5 CPU Core User’s Manual Preliminary EA Effective address; the 32-bit address, derived by applying indexing or indirect addressing rules to the specified operand, that specifies an location in main storage. EXTS(x) The result of extending x on the left with sign bits. FLD An instruction or register field FLDb A bit in a named instruction or register field FLDb,b, . . .
Preliminary PPC440x5 CPU Core User’s Manual instruction(EA) An instruction operating on a data or instruction cache block associated with an EA. leave Leave innermost do loop or do loop specified in a leave statement. n A decimal number n The bit or bit value b is replicated n times. xx Bit positions which are don’t-cares.
PPC440x5 CPU Core User’s Manual Preliminary Common examples of these kinds of register changes include the Condition Register (CR) and the Integer Exception Register (XER). For discussion of the CR, see Condition Register (CR) on page 67. For discussion of the XER, see Integer Exception Register (XER) on page 72. 9.5 Alphabetical Instruction Listing The following pages list the instructions, both defined and allocated, which are implemented within the PPC440x5 core. Page 254 of 589 instrset.fm.
add Add PPC440x5 CPU Core User’s Manual Preliminary add Add add add. addo addo. OE= 0, Rc= 0 OE= 0, Rc= 1 OE= 1, Rc= 0 OE= 1, Rc= 1 RT, RA, RB RT, RA, RB RT, RA, RB RT, RA, RB 31 0 RT 6 RA 11 RB 16 OE 266 Rc 21 22 31 (RT) ← (RA) + (RB) The sum of the contents of register RA and the contents of register RB is placed into register RT. Registers Altered • RT • CR[CR0] if Rc contains 1 • XER[SO, OV] if OE contains 1 instrset.fm.
addc Add Carrying PPC440x5 CPU Core User’s Manual Preliminary addc Add Carrying addc addc. addco addco. RT, RA, RB RT, RA, RB RT, RA, RB RT, RA, RB 31 0 OE= 0, Rc= 0 OE= 0, Rc= 1 OE= 1, Rc= 0 OE= 1, Rc= 1 RT 6 RA 11 RB 16 OE 10 Rc 21 22 31 (RT) ← (RA) + (RB) if (RA) + (RB) >u 232 – 1 then XER[CA] ← 1 else XER[CA] ← 0 The sum of the contents of register RA and register RB is placed into register RT.
adde Add Extended PPC440x5 CPU Core User’s Manual Preliminary adde Add Extended adde adde. addeo addeo. RT, RA, RB RT, RA, RB RT, RA, RB RT, RA, RB 31 0 OE= 0, Rc= 0 OE= 0, Rc= 1 OE= 1, Rc= 0 OE =1, Rc=1 RT 6 RA 11 RB 16 OE 138 Rc 21 22 31 (RT) ← (RA) + (RB) + XER[CA] if (RA) + (RB) + XER[CA] >u 232 – 1 then XER[CA] ← 1 else XER[CA] ← 0 The sum of the contents of register RA, register RB, and XER[CA] is placed into register RT.
addi Add Immediate PPC440x5 CPU Core User’s Manual Preliminary addi Add Immediate addi RT, RA, IM 14 RT 0 6 RA 11 IM 16 31 (RT) ← (RA|0) + EXTS(IM) If the RA field is 0, the IM field, sign-extended to 32 bits, is placed into register RT. If the RA field is nonzero, the sum of the contents of register RA and the contents of the IM field, signextended to 32 bits, is placed into register RT.
addic Add Immediate Carrying PPC440x5 CPU Core User’s Manual Preliminary addic Add Immediate Carrying addic RT, RA, IM 12 RT 0 RA 6 11 IM 16 31 (RT) ← (RA) + EXTS(IM) if (RA) + EXTS(IM) >u 232 – 1 then XER[CA] ← 1 else XER[CA] ← 0 The sum of the contents of register RA and the contents of the IM field, sign-extended to 32 bits, is placed into register RT. XER[CA] is set to a value determined by the unsigned magnitude of the result of the add operation.
addic. Add Immediate Carrying and Record PPC440x5 CPU Core User’s Manual Preliminary addic. Add Immediate Carrying and Record addic. RT, RA, IM 13 RT 0 RA 6 11 IM 16 31 (RT) ← (RA) + EXTS(IM) if (RA) + EXTS(IM) >u 232 – 1 then XER[CA] ← 1 else XER[CA] ← 0 The sum of the contents of register RA and the contents of the IM field, sign-extended to 32 bits, is placed into register RT. XER[CA] is set to a value determined by the unsigned magnitude of the result of the add operation.
addis Add Immediate Shifted PPC440x5 CPU Core User’s Manual Preliminary addis Add Immediate Shifted addis RT, RA, IM 15 RT 0 6 RA 11 IM 16 31 (RT) ← (RA|0) + (IM || 160) If the RA field is 0, the IM field is concatenated on its right with sixteen 0-bits and placed into register RT. If the RA field is nonzero, the contents of register RA are added to the contents of the extended IM field. The sum is stored into register RT.
addme Add to Minus One Extended PPC440x5 CPU Core User’s Manual Preliminary addme Add to Minus One Extended addme addme. addmeo addmeo. RT, RA RT, RA RT, RA RT, RA 31 0 OE= 0, Rc= 0 OE= 0, Rc= 1 OE=1, Rc= 0 OE =1, Rc=1 RT 6 RA 11 OE 16 234 Rc 21 22 31 (RT) ← (RA) + XER[CA] + (–1) if (RA) + XER[CA] + 0xFFFF FFFF >u 232 – 1 then XER[CA] ← 1 else XER[CA] ← 0 The sum of the contents of register RA, XER[CA], and –1 is placed into register RT.
addze Add to Zero Extended PPC440x5 CPU Core User’s Manual Preliminary addze Add to Zero Extended addze addze. addzeo addzeo. RT, RA RT, RA RT, RA RT, RA 31 0 OE=0, Rc=0 OE=0, Rc=1 OE=1, Rc=0 OE=1, Rc=1 RT 6 RA 11 OE 16 202 Rc 21 22 31 (RT) ← (RA) + XER[CA] if (RA) + XER[CA] >u 232 – 1 then XER[CA] ← 1 else XER[CA] ← 0 The sum of the contents of register RA and XER[CA] is placed into register RT. XER[CA] is set to a value determined by the unsigned magnitude of the result of the add operation.
and AND PPC440x5 CPU Core User’s Manual Preliminary and AND and and. RA, RS, RB RA, RS, RB 31 0 Rc=0 Rc=1 RS 6 RA 11 RB 16 28 21 Rc 31 (RA) ← (RS) ∧ (RB) The contents of register RS are ANDed with the contents of register RB; the result is placed into register RA. Registers Altered • RA • CR[CR0] if Rc contains 1 Page 264 of 589 instrset.fm.
andc AND with Complement PPC440x5 CPU Core User’s Manual Preliminary andc AND with Complement andc andc. RA,RS,RB RA,RS,RB 31 0 Rc=0 Rc=1 RS 6 RA 11 RB 16 60 21 2 Rc 31 (RA) ← (RS) ∧ ¬(RB) The contents of register RS are ANDed with the ones complement of the contents of register RB; the result is placed into register RA. Registers Altered • RA • CR[CR0] if Rc contains 1 instrset.fm.
andi. AND Immediate PPC440x5 CPU Core User’s Manual Preliminary andi. AND Immediate andi. RA, RS, IM 28 0 RS 6 RA 11 IM 16 31 (RA) ← (RS) ∧ (160 || IM) The IM field is extended to 32 bits by concatenating 16 0-bits on its left. The contents of register RS is ANDed with the extended IM field; the result is placed into register RA. Registers Altered • RA • CR[CR0] Programming Note The andi. instruction can test whether any of the 16 least-significant bits in a GPR are 1-bits. andi.
andis. AND Immediate Shifted PPC440x5 CPU Core User’s Manual Preliminary andis. AND Immediate Shifted andis. RA, RS, IM 29 0 RS 6 RA 11 IM 16 31 (RA) ← (RS) ∧ (IM || 160) The IM field is extended to 32 bits by concatenating 16 0-bits on its right. The contents of register RS are ANDed with the extended IM field; the result is placed into register RA. Registers Altered • RA • CR[CR0] Programming Note The andis. instruction can test whether any of the 16 most-significant bits in a GPR are 1-bits.
b Branch PPC440x5 CPU Core User’s Manual Preliminary b Branch b ba bl bla target target target target 18 0 AA=0, LK=0 AA=1, LK=0 AA=0, LK=1 AA=1, LK=1 LI 6 AA LK 30 31 If AA = 1 then LI ← target6:29 NIA ← EXTS(LI || 20) else LI ← (target – CIA)6:29 NIA ← CIA + EXTS(LI || 20) if LK = 1 then (LR) ← CIA + 4 PC ← NIA The next instruction address (NIA) is the effective address of the branch target. The NIA is formed by adding a displacement to a base address.
bc Branch Conditional PPC440x5 CPU Core User’s Manual Preliminary bc Branch Conditional bc bca bcl bcla BO, BI, target BO, BI, target BO, BI, target BO, BI, target 16 0 AA=0, LK= 0 AA =1, LK= 0 AA= 0, LK=1 AA =1, LK=1 BO 6 BI 11 BD 16 AA LK 30 31 if BO2 = 0 then CTR ← CTR – 1 if (BO2 = 1 ∨ ((CTR = 0) = BO3)) ∧ (BO0 = 1 ∨ (CRBI = BO1)) then if AA = 1 then BD ← target16:29 NIA ← EXTS(BD || 20) else BD ← (target – CIA)16:29 NIA ← CIA + EXTS(BD || 20) else NIA ← CIA + 4 if LK = 1 then (LR) ← CIA + 4 P
bc Branch Conditional PPC440x5 CPU Core User’s Manual Preliminary Table 9-8. Extended Mnemonics for bc, bca, bcl, bcla Mnemonic Operands Function Other Registers Altered Decrement CTR; branch if CTR ≠ 0. bdnz Extended mnemonic for bc 16,0,target bdnza Extended mnemonic for bca 16,0,target target bdnzl Extended mnemonic for bcl 16,0,target (LR) ← CIA + 4. bdnzla Extended mnemonic for bcla 16,0,target (LR) ← CIA + 4. Decrement CTR. Branch if CTR ≠ 0 AND CRcr_bit = 0.
bc Branch Conditional PPC440x5 CPU Core User’s Manual Preliminary Table 9-8. Extended Mnemonics for bc, bca, bcl, bcla (continued) Mnemonic Operands Other Registers Altered Decrement CTR Branch if CTR = 0 AND CRcr_bit = 0. bdzf bdzfa Function Extended mnemonic for bc 2,cr_bit,target cr_bit, target Extended mnemonic for bca 2,cr_bit,target bdzfl Extended mnemonic for bcl 2,cr_bit,target (LR) ← CIA + 4. bdzfla Extended mnemonic for bcla 2,cr_bit,target (LR) ← CIA + 4. Decrement CTR.
bc Branch Conditional PPC440x5 CPU Core User’s Manual Preliminary Table 9-8. Extended Mnemonics for bc, bca, bcl, bcla (continued) Mnemonic Operands Other Registers Altered Branch if greater than or equal. Use CR0 if cr_field is omitted.
bc Branch Conditional PPC440x5 CPU Core User’s Manual Preliminary Table 9-8. Extended Mnemonics for bc, bca, bcl, bcla (continued) Mnemonic Operands Other Registers Altered Branch if not equal. Use CR0 if cr_field is omitted. bne bnea Function Extended mnemonic for bc 4,4∗cr_field+2,target [cr_field,] target Extended mnemonic for bca 4,4∗cr_field+2,target bnel Extended mnemonic for bcl 4,4∗cr_field+2,target (LR) ← CIA + 4.
bc Branch Conditional PPC440x5 CPU Core User’s Manual Preliminary Table 9-8. Extended Mnemonics for bc, bca, bcl, bcla (continued) Mnemonic Operands Other Registers Altered Branch if not unordered. Use CR0 if cr_field is omitted. bnu bnua Function Extended mnemonic for bc 4,4∗cr_field+3,target [cr_field,] target Extended mnemonic for bca 4,4∗cr_field+3,target bnul Extended mnemonic for bcl 4,4∗cr_field+3,target (LR) ← CIA + 4.
bcctr Branch Conditional to Count Register PPC440x5 CPU Core User’s Manual Preliminary bcctr Branch Conditional to Count Register bcctr bcctrl BO, BI BO, BI 19 0 LK = 0 LK =1 BO BI 6 11 528 16 LK 21 31 if (BO0 = 1 ∨ (CRBI = BO1)) then NIA ← CTR0:29 || 20 else NIA ← CIA + 4 if LK = 1 then (LR) ← CIA + 4 PC ← NIA If BO0 contains 0, then the CR bit specified by the BI field is compared to BO1 as part of the branch condition.
bcctr Branch Conditional to Count Register PPC440x5 CPU Core User’s Manual Preliminary Table 9-9. Extended Mnemonics for bcctr, bcctrl (continued) Mnemonic Operands Function Other Registers Altered Branch, if equal, to address in CTR Use CR0 if cr_field is omitted. beqctr [cr_field] Extended mnemonic for bcctr 12,4∗cr_field+2 Extended mnemonic for bcctrl 12,4∗cr_field+2 beqctrl (LR) ← CIA + 4. (LR) ← CIA + 4. (LR) ← CIA + 4. (LR) ← CIA + 4. (LR) ← CIA + 4. (LR) ← CIA + 4.
bcctr Branch Conditional to Count Register PPC440x5 CPU Core User’s Manual Preliminary Table 9-9. Extended Mnemonics for bcctr, bcctrl (continued) Mnemonic Operands Function Other Registers Altered Branch, if not greater than, to address in CTR. Use CR0 if cr_field is omitted. bngctr [cr_field] Extended mnemonic for bcctr 4,4∗cr_field+1 Extended mnemonic for bcctrl 4,4∗cr_field+1 bngctrl (LR) ← CIA + 4. (LR) ← CIA + 4. (LR) ← CIA + 4. (LR) ← CIA + 4. (LR) ← CIA + 4. (LR) ← CIA + 4.
bclr Branch Conditional to Link Register PPC440x5 CPU Core User’s Manual Preliminary bclr Branch Conditional to Link Register bclr bclrl BO, BI BO, BI 19 0 LK = 0 LK =1 BO 6 BI 11 16 16 21 LK 31 if BO2 = 0 then CTR ← CTR – 1 if (BO2 = 1 ∨ ((CTR = 0) = BO3)) ∧ (BO0 = 1 ∨ (CRBI = BO1)) then NIA ← LR0:29 || 20 else NIA ← CIA + 4 if LK = 1 then (LR) ← CIA + 4 PC ← NIA If BO2 contains 0, the CTR decrements, and the decremented value is tested for 0 as part of the branch condition.
bclr Branch Conditional to Link Register PPC440x5 CPU Core User’s Manual Preliminary Table 9-10. Extended Mnemonics for bclr, bclrl Mnemonic Operands Function Other Registers Altered Branch unconditionally to address in LR. blr Extended mnemonic for bclr 20,0 blrl Extended mnemonic for bclrl 20,0 (LR) ← CIA + 4. (LR) ← CIA + 4. (LR) ← CIA + 4. (LR) ← CIA + 4. (LR) ← CIA + 4. (LR) ← CIA + 4. Extended mnemonic for bclr 16,0 Extended mnemonic for bclrl 16,0 bdnzlrl Decrement CTR.
bclr Branch Conditional to Link Register PPC440x5 CPU Core User’s Manual Preliminary Table 9-10. Extended Mnemonics for bclr, bclrl (continued) Mnemonic Operands Function Other Registers Altered Branch if equal to address in LR. Use CR0 if cr_field is omitted. beqlr [cr_field] Extended mnemonic for bclr 12,4∗cr_field+2 Extended mnemonic for bclrl 12,4∗cr_field+2 beqlrl (LR) ← CIA + 4. (LR) ← CIA + 4. (LR) ← CIA + 4. (LR) ← CIA + 4. (LR) ← CIA + 4. (LR) ← CIA + 4. (LR) ← CIA + 4.
bclr Branch Conditional to Link Register PPC440x5 CPU Core User’s Manual Preliminary Table 9-10. Extended Mnemonics for bclr, bclrl (continued) Mnemonic Operands Function Other Registers Altered Branch, if not greater than, to address in LR. Use CR0 if cr_field is omitted. bnglr [cr_field] Extended mnemonic for bclr 4,4∗cr_field+1 Extended mnemonic for bclrl 4,4∗cr_field+1 bnglrl (LR) ← CIA + 4. (LR) ← CIA + 4. (LR) ← CIA + 4. (LR) ← CIA + 4. (LR) ← CIA + 4. (LR) ← CIA + 4.
cmp Compare PPC440x5 CPU Core User’s Manual Preliminary cmp Compare cmp BF, 0, RA, RB 31 BF 0 6 RA 9 11 RB 16 0 21 31 c0:3 ← 40 if (RA) < (RB) then c0 ← 1 if (RA) > (RB) then c1 ← 1 if (RA) = (RB) then c2 ← 1 c3 ← XER[SO] n ← BF CR[CRn] ← c0:3 The contents of register RA are compared with the contents of register RB using a 32-bit signed compare. The CR field specified by the BF field is updated to reflect the results of the compare and the value of XER[SO] is placed into the same CR field.
cmpi Compare Immediate PPC440x5 CPU Core User’s Manual Preliminary cmpi Compare Immediate cmpi BF, 0, RA, IM 11 BF 0 6 RA 9 11 IM 16 31 c0:3 ← 40 if (RA) < EXTS(IM) then c0 ← 1 if (RA) > EXTS(IM) then c1 ← 1 if (RA) = EXTS(IM) then c2 ← 1 c3 ← XER[SO] n ← BF CR[CRn] ← c0:3 The IM field is sign-extended to 32 bits. The contents of register RA are compared with the extended IM field, using a 32-bit signed compare.
cmpl Compare Logical PPC440x5 CPU Core User’s Manual Preliminary cmpl Compare Logical cmpl BF, 0, RA, RB 31 BF 0 6 RA 9 11 RB 16 32 21 31 c0:3 ← 40 u if (RA) < (RB) then c0 ← 1 u if (RA) > (RB) then c1 ← 1 if (RA) = (RB) then c2 ← 1 c3 ← XER[SO] n ← BF CR[CRn] ← c0:3 The contents of register RA are compared with the contents of register RB, using a 32-bit unsigned compare.
cmpli Compare Logical Immediate PPC440x5 CPU Core User’s Manual Preliminary cmpli Compare Logical Immediate cmpli BF, 0, RA, IM 10 BF 0 6 RA 9 11 IM 16 31 c0:3 ← 40 u if (RA) < (160 || IM) then c0 ← 1 u if (RA) > (160 || IM) then c1 ← 1 if (RA) = (160 || IM) then c2 ← 1 c3 ← XER[SO] n ← BF CR[CRn] ← c0:3 The IM field is extended to 32 bits by concatenating 16 0-bits to its left. The contents of register RA are compared with IM using a 32-bit unsigned compare.
cntlzw Count Leading Zeros Word PPC440x5 CPU Core User’s Manual Preliminary cntlzw Count Leading Zeros Word cntlzw cntlzw. RA, RS RA, RS 31 0 Rc=0 Rc=1 RS 6 RA 11 26 16 Rc 21 31 n ← 0 do while n < 32 if (RS)n = 1 then leave n ← n + 1 (RA) ← n The consecutive leading 0 bits in register RS are counted; the count is placed into register RA. The count ranges from 0 through 32, inclusive.
crand Condition Register AND PPC440x5 CPU Core User’s Manual Preliminary crand Condition Register AND crand BT, BA, BB 19 0 BT 6 BA 11 BB 16 257 21 31 CRBT ← CRBA ∧ CRBB The CR bit specified by the BA field is ANDed with the CR bit specified by the BB field; the result is placed into the CR bit specified by the BT field. If instruction bit 31 contains 1, the contents of CR[CR0] are undefined. Registers Altered • CRBT Invalid Instruction Forms • Reserved fields instrset.fm.
crandc Condition Register AND with Complement PPC440x5 CPU Core User’s Manual Preliminary crandc Condition Register AND with Complement crandc BT, BA, BB 19 0 BT 6 BA 11 BB 16 129 21 31 CRBT ← CRBA ∧ ¬CRBB The CR bit specified by the BA field is ANDed with the ones complement of the CR bit specified by the BB field; the result is placed into the CR bit specified by the BT field. If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
creqv Condition Register Equivalent PPC440x5 CPU Core User’s Manual Preliminary creqv Condition Register Equivalent creqv BT, BA, BB 19 BT 0 6 BA 11 BB 16 289 21 31 CRBT ← ¬(CRBA ⊕ CRBB) The CR bit specified by the BA field is XORed with the CR bit specified by the BB field; the ones complement of the result is placed into the CR bit specified by the BT field. If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
crnand Condition Register NAND PPC440x5 CPU Core User’s Manual Preliminary crnand Condition Register NAND crnand BT, BA, BB 19 0 BT 6 BA 11 BB 16 225 21 31 CRBT ← ¬(CRBA ∧ CRBB) The CR bit specified by the BA field is ANDed with the CR bit specified by the BB field; the ones complement of the result is placed into the CR bit specified by the BT field. If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
crnor Condition Register NOR PPC440x5 CPU Core User’s Manual Preliminary crnor Condition Register NOR crnor BT, BA, BB 19 BT 0 6 BA 11 BB 16 33 21 31 CRBT ← ¬(CRBA ∨ CRBB) The CR bit specified by the BA field is ORed with the CR bit specified by the BB field; the ones complement of the result is placed into the CR bit specified by the BT field. If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
cror Condition Register OR PPC440x5 CPU Core User’s Manual Preliminary cror Condition Register OR cror BT, BA, BB 19 BT 0 6 BA 11 BB 16 449 21 31 CRBT ← CRBA ∨ CRBB The CR bit specified by the BA field is ORed with the CR bit specified by the BB field; the result is placed into the CR bit specified by the BT field. If instruction bit 31 contains 1, the contents of CR[CR0] are undefined. Registers Altered • CRBT Invalid Instruction Forms • Reserved fields Table 9-17.
crorc Condition Register OR with Complement PPC440x5 CPU Core User’s Manual Preliminary crorc Condition Register OR with Complement crorc BT, BA, BB 19 0 BT 6 BA 11 BB 16 417 21 31 CRBT ← CRBA ∨ ¬CRBB The condition register (CR) bit specified by the BA field is ORed with the ones complement of the CR bit specified by the BB field; the result is placed into the CR bit specified by the BT field. If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
crxor Condition Register XOR PPC440x5 CPU Core User’s Manual Preliminary crxor Condition Register XOR crxor BT, BA, BB 19 BT 0 6 BA 11 BB 16 193 21 31 CRBT ← CRBA ⊕ CRBB The CR bit specified by the BA field is XORed with the CR bit specified by the BB field; the result is placed into the CR bit specified by the BT field. If instruction bit 31 contains 1, the contents of CR[CR0] are undefined. Registers Altered • CRBT Invalid Instruction Forms • Reserved fields Table 9-18.
dcba Data Cache Block Allocate PPC440x5 CPU Core User’s Manual Preliminary dcba Data Cache Block Allocate dcba RA, RB 31 0 RA 6 11 RB 16 758 21 31 dcba is treated as a no-op by the PPC440x5 core. instrset.fm.
dcbf Data Cache Block Flush PPC440x5 CPU Core User’s Manual Preliminary dcbf Data Cache Block Flush dcbf RA, RB 31 0 RA 6 11 RB 16 86 21 31 EA ← (RA|0) + (RB) DCBF(EA) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
dcbi Data Cache Block Invalidate PPC440x5 CPU Core User’s Manual Preliminary dcbi Data Cache Block Invalidate dcbi RA, RB 31 0 RA 6 11 RB 16 470 21 31 EA ← (RA|0) + (RB) DCBI(EA) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
dcbst Data Cache Block Store PPC440x5 CPU Core User’s Manual Preliminary dcbst Data Cache Block Store dcbst RA, RB 31 0 RA 6 11 RB 16 54 21 31 EA ← (RA|0) + (RB) DCBST(EA) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB. The base address is 0 if the RA field is 0, and is the contents of register RA otherwise.
dcbt Data Cache Block Touch PPC440x5 CPU Core User’s Manual Preliminary dcbt Data Cache Block Touch dcbt RA, RB 31 0 RA 6 11 RB 16 278 21 31 EA ← (RA|0) + (RB) DCBT(EA) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB. The base address is 0 when the RA field is 0, and is the contents of register RA otherwise.
dcbtst Data Cache Block Touch for Store PPC440x5 CPU Core User’s Manual Preliminary dcbtst Data Cache Block Touch for Store dcbtst RA, RB 31 0 RA 6 11 RB 16 246 21 31 EA ← (RA|0) + (RB) DCBTST(EA) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
dcbtst Preliminary Data Cache Block Touch for Store PPC440x5 CPU Core User’s Manual This instruction is considered a “load” with respect to data address compare (DAC) Debug exceptions. See Debug Interrupt on page 195 for more information. instrset.fm.
dcbz Data Cache Block Set to Zero PPC440x5 CPU Core User’s Manual Preliminary dcbz Data Cache Block Set to Zero dcbz RA, RB 31 0 RA 6 11 RB 16 1014 21 31 EA ← (RA|0) + (RB) DCBZ(EA) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
dcbz Preliminary Data Cache Block Set to Zero PPC440x5 CPU Core User’s Manual This instruction is considered a “store” with respect to data address compare (DAC) Debug exceptions. See Debug Interrupt on page 195 for more information. instrset.fm.
dccci Data Cache Congruence Class Invalidate PPC440x5 CPU Core User’s Manual Preliminary dccci Data Cache Congruence Class Invalidate dccci RA, RB 31 0 RA 6 11 RB 16 454 21 31 DCCCI This instruction flash invalidates the entire data cache array. The RA and RB operands are not used; previous implementations used these operands to calculate an effective address (EA) which specified the particular block or blocks to be invalidated.
dcread Data Cache Read PPC440x5 CPU Core User’s Manual Preliminary dcread Data Cache Read dcread RT, RA, RB 31 0 RT RA 6 11 RB 486 16 21 31 EA ← (RA|0) + (RB) INDEX ← EA17:26 WORD ← EA27:29 (RT) ← (data cache data)[INDEX,WORD] DCDBTRH ← (data cache tag high)[INDEX] DCDBTRL ← (data cache tag low)[INDEX] An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
dcread Data Cache Read PPC440x5 CPU Core User’s Manual Preliminary Registers Altered • RT • DCDBTRH • DCDBTRL Invalid Instruction Forms • Reserved fields Programming Note Execution of this instruction is privileged. The PPC440x5 core does not support the use of the dcread instruction when the data cache controller is still in the process of performing cache operations associated with previously executed instructions (such as line fills and line flushes).
divw Divide Word PPC440x5 CPU Core User’s Manual Preliminary divw Divide Word divw divw. divwo divwo. RT, RA, RB RT, RA, RB RT, RA, RB RT, RA, RB 31 OE=0, Rc=0 OE=0, Rc=1 OE=1, Rc=0 OE=1, Rc=1 RT 0 6 RA RB 11 16 OE 491 Rc 21 22 31 (RT) ← (RA) ÷ (RB) The contents of register RA are divided by the contents of register RB. The quotient is placed into register RT. Both the dividend and the divisor are interpreted as signed integers.
divwu Divide Word Unsigned PPC440x5 CPU Core User’s Manual Preliminary divwu Divide Word Unsigned divwu divwu. divwuo divwuo. RT, RA, RB RT, RA, RB RT, RA, RB RT, RA, RB 31 OE=0, Rc=0 OE=0, Rc=1 OE=1, Rc=0 OE=1, Rc=1 RT 0 6 RA RB 11 16 OE 459 Rc 21 22 31 (RT) ← (RA) ÷ (RB) The contents of register RA are divided by the contents of register RB. The quotient is placed into register RT. The dividend and the divisor are interpreted as unsigned integers.
dlmzb Determine Leftmost Zero Byte PPC440x5 CPU Core User’s Manual Preliminary dlmzb determine left most zero byte dlmzb dlmzb.
eqv Equivalent PPC440x5 CPU Core User’s Manual Preliminary eqv Equivalent eqv eqv. RA, RS, RB RA, RS, RB 31 0 Rc=0 Rc=1 RS 6 RA 11 RB 16 284 21 Rc 31 (RA) ← ¬((RS) ⊕ (RB)) The contents of register RS are XORed with the contents of register RB; the ones complement of the result is placed into register RA. Registers Altered • RA • CR[CR0] if Rc contains 1 Page 310 of 589 instrset.fm.
extsb Extend Sign Byte PPC440x5 CPU Core User’s Manual Preliminary extsb Extend Sign Byte extsb extsb. RA, RS RA, RS 31 0 Rc=0 Rc=1 RS 6 RA 11 954 16 21 Rc 31 (RA) ← EXTS(RS)24:31 The least significant byte of register RS is sign-extended to 32 bits by replicating bit 24 of the register into bits 0 through 23 of the result. The result is placed into register RA. Registers Altered • RA • CR[CR0] if Rc contains 1 Invalid Instruction Forms • Reserved fields instrset.fm.
extsh Extend Sign Halfword PPC440x5 CPU Core User’s Manual Preliminary extsh Extend Sign Halfword extsh extsh. RA, RS RA, RS 31 0 Rc=0 Rc=1 RS 6 RA 11 922 16 21 Rc 31 (RA) ← EXTS(RS)16:31 The least significant halfword of register RS is sign-extended to 32 bits by replicating bit 16 of the register into bits 0 through 15 of the result. The result is placed into register RA.
icbi Instruction Cache Block Invalidate PPC440x5 CPU Core User’s Manual Preliminary icbi Instruction Cache Block Invalidate icbi RA, RB 31 0 RA 6 11 RB 16 982 21 31 EA ← (RA|0) + (RB) ICBI(EA) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise. If the instruction block at the EA is in the instruction cache, the cache block is marked invalid.
icbt Instruction Cache Block Touch PPC440x5 CPU Core User’s Manual Preliminary icbt Instruction Cache Block Touch icbt RA, RB 31 0 RA 6 11 RB 16 22 21 31 EA← (RA|0) + (RB) ICBT(EA) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
icbt Preliminary Instruction Cache Block Touch PPC440x5 CPU Core User’s Manual This instruction is considered a “load” with respect to Data Storage exceptions. See Data Storage Interrupt on page 181 for more information. This instruction is considered a “load” with respect to data address compare (DAC) Debug exceptions. See Debug Interrupt on page 195 for more information. instrset.fm.
iccci Instruction Cache Congruence Class Invalidate PPC440x5 CPU Core User’s Manual Preliminary iccci Instruction Cache Congruence Class Invalidate iccci RA, RB 31 0 RA 6 11 RB 16 966 21 31 ICCCI This instruction flash invalidates the entire instruction cache array. The RA and RB operands are not used; previous implementations used these operands to calculate an effective address (EA) which specified the particular block or blocks to be invalidated.
icread Instruction Cache Read PPC440x5 CPU Core User’s Manual Preliminary icread Instruction Cache Read icread RA, RB 31 0 RA 6 11 RB 998 16 21 31 EA ← (RA|0) + (RB) INDEX ← EA17:26 WORD ← EA27:29 ICDBDR ← (instruction cache data)[INDEX,WORD] ICDBTRH ← (instruction cache tag high)[INDEX] ICDBTRL ← (instruction cache tag low)[INDEX] An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
icread Instruction Cache Read PPC440x5 CPU Core User’s Manual Preliminary Registers Altered • ICDBDR • ICDBTRH • ICDBTRL Invalid Instruction Forms • Reserved fields Programming Note Execution of this instruction is privileged. The PPC440x5 does not automatically synchronize context between an icread instruction and the subsequent mfspr instructions which read the results of the icread instruction into GPRs.
isel Integer Select PPC440x5 CPU Core User’s Manual Preliminary isel Add Immediate isel RT, RA, RB, CRb 31 0 RT 6 RA 11 RB 16 CRb 21 15 26 31 if CR[CRb] = 1 then (RT) ← (RA|0) else (RT) ← (RB) If CR[CRb] = 0, register RT is written with the contents of register RB. If CR[CRb] = 1 and RA ≠ 0, register RT is written with the contents of register RA. If CR[CRb] = 1 and RA = 0, register RT is written with 0. Registers Altered • RT instrset.fm.
isync Instruction Synchronize PPC440x5 CPU Core User’s Manual Preliminary isync Instruction Synchronize isync 19 0 150 6 21 31 The isync instruction is a context synchronizing instruction. isync provides an ordering function for the effects of all instructions executed by the processor. Executing isync insures that all instructions preceding the isync instruction execute before isync completes, except that storage accesses caused by those instructions need not have completed.
lbz Load Byte and Zero PPC440x5 CPU Core User’s Manual Preliminary lbz Load Byte and Zero lbz RT, D(RA) 34 0 RT 6 RA 11 D 16 31 EA ← (RA|0) + EXTS(D) (RT) ← 240 || MS(EA,1) An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise. The byte at the EA is extended to 32 bits by concatenating 24 0-bits to its left.
lbzu Load Byte and Zero with Update PPC440x5 CPU Core User’s Manual Preliminary lbzu Load Byte and Zero with Update lbzu RT, D(RA) 35 0 RT 6 RA 11 D 16 31 EA ← (RA|0) + EXTS(D) (RA) ← EA (RT) ← 240 || MS(EA,1) An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise. The EA is placed into register RA.
lbzux Load Byte and Zero with Update Indexed PPC440x5 CPU Core User’s Manual Preliminary lbzux Load Byte and Zero with Update Indexed lbzux RT, RA, RB 31 0 RT 6 RA 11 RB 16 119 21 31 EA ← (RA|0) + (RB) (RA) ← EA (RT) ← 240 || MS(EA,1) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise. The EA is placed into register RA.
lbzx Load Byte and Zero Indexed PPC440x5 CPU Core User’s Manual Preliminary lbzx Load Byte and Zero Indexed lbzx RT,RA, RB 31 0 RT 6 RA 11 RB 16 87 21 31 EA ← (RA|0) + (RB) (RT) ← 240 || MS(EA,1) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise. The byte at the EA is extended to 32 bits by concatenating 24 0-bits to its left.
lha Load Halfword Algebraic PPC440x5 CPU Core User’s Manual Preliminary lha Load Halfword Algebraic lha RT, D(RA) 42 0 RT 6 RA 11 D 16 31 EA ← (RA|0) + EXTS(D) (RT) ← EXTS(MS(EA,2)) An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
lhau Load Halfword Algebraic with Update PPC440x5 CPU Core User’s Manual Preliminary lhau Load Halfword Algebraic with Update lhau RT, D(RA) 43 0 RT 6 RA 11 D 16 31 EA ← (RA|0) + EXTS(D) (RA) ← EA (RT) ← EXTS(MS(EA,2)) An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits. The base address is 0 when the RA field is 0 and is the contents of register RA otherwise.
lhaux Load Halfword Algebraic with Update Indexed PPC440x5 CPU Core User’s Manual Preliminary lhaux Load Halfword Algebraic with Update Indexed lhaux RT, RA, RB 31 0 RT 6 RA 11 RB 16 375 21 31 EA ← (RA|0) + (RB) (RA) ← EA (RT) ← EXTS(MS(EA,2)) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise. The EA is placed into register RA.
lhax Load Halfword Algebraic Indexed PPC440x5 CPU Core User’s Manual Preliminary lhax Load Halfword Algebraic Indexed lhax RT, RA, RB 31 0 RT 6 RA 11 RB 16 343 21 31 EA ← (RA|0) + (RB) (RT) ← EXTS(MS(EA,2)) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise. The halfword at the EA is sign-extended to 32 bits and placed into register RT.
lhbrx Load Halfword Byte-Reverse Indexed PPC440x5 CPU Core User’s Manual Preliminary lhbrx Load Halfword Byte-Reverse Indexed lhbrx RT, RA, RB 31 0 RT 6 RA 11 RB 16 790 21 31 EA ← (RA|0) + (RB) (RT) ← 160 || BYTE_REVERSE(MS(EA,2)) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
lhz Load Halfword and Zero PPC440x5 CPU Core User’s Manual Preliminary lhz Load Halfword and Zero lhz RT, D(RA) 40 0 RT 6 RA 11 D 16 31 EA ← (RA|0) + EXTS(D) (RT) ← 160 || MS(EA,2) An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
lhzu Load Halfword and Zero with Update PPC440x5 CPU Core User’s Manual Preliminary lhzu Load Halfword and Zero with Update lhzu RT, D(RA) 41 0 RT 6 RA 11 D 16 31 EA ← (RA|0) + EXTS(D) (RA) ← EA (RT) ← 160 || MS(EA,2) An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise. The EA is placed into register RA.
lhzux Load Halfword and Zero with Update Indexed PPC440x5 CPU Core User’s Manual Preliminary lhzux Load Halfword and Zero with Update Indexed lhzux RT, RA, RB 31 0 RT 6 RA 11 RB 16 311 21 31 EA ← (RA|0) + (RB) (RA) ← EA (RT) ← 160 || MS(EA,2) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise. The EA is placed into register RA.
lhzx Load Halfword and Zero Indexed PPC440x5 CPU Core User’s Manual Preliminary lhzx Load Halfword and Zero Indexed lhzx RT, RA, RB 31 0 RT 6 RA 11 RB 16 279 21 31 EA ← (RA|0) + (RB) (RT) ← 160 || MS(EA,2) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise. The halfword at the EA is extended to 32 bits by concatenating 16 0-bits to its left.
lmw Load Multiple Word PPC440x5 CPU Core User’s Manual Preliminary lmw Load Multiple Word lmw RT, D(RA) 46 0 RT 6 RA 11 D 16 31 EA ← (RA|0) + EXTS(D) r ← RT do while r ≤ 31 GPR(r)) ← MS(EA,4) r ← r + 1 EA ← EA + 4 An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field in the instruction to 32 bits. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
lswi Load String Word Immediate PPC440x5 CPU Core User’s Manual Preliminary lswi Load String Word Immediate lswi RT, RA, NB 31 0 RT 6 RA 11 NB 16 597 21 31 EA ← (RA|0) if NB = 0 then CNT ← 32 else CNT ← NB n ← CNT RFINAL ← ((RT + CEIL(CNT/4) – 1) % 32) r ← RT – 1 i ← 0 do while n > 0 if i = 0 then r ← r + 1 if r = 32 then r ← 0 GPR(r)) ← 0 GPR(r)i:i+7) ← MS(EA,1) i ← i + 8 if i = 32 then i ← 0 EA ← EA + 1 n ← n – 1 An effective address (EA) is determined by the RA field.
lswi Load String Word Immediate PPC440x5 CPU Core User’s Manual Preliminary • RA is in the range of registers to be loaded • RA = RT = 0 Programming Note This instruction can be restarted, meaning that it could be interrupted after having already updated some of the target registers, and then re-executed from the beginning (after returning from the interrupt), in which case the registers which had already been loaded prior to the interrupt will be loaded a second time.
lswx Load String Word Indexed PPC440x5 CPU Core User’s Manual Preliminary lswx Load String Word Indexed lswx RT, RA, RB 31 0 RT 6 RA 11 RB 16 533 21 31 EA ← (RA|0) + (RB) CNT ← XER[TBC] n ← CNT RFINAL ← ((RT + CEIL(CNT/4) – 1) % 32) r ← RT – 1 i ← 0 do while n > 0 if i = 0 then r ← r + 1 if r = 32 then r ← 0 GPR(r)) ← 0 GPR(r)i:i+7) ← MS(EA,1) i ← i + 8 if i = 32 then i ← 0 EA ← EA + 1 n ← n – 1 An effective address (EA) is formed by adding an index to a base address.
lswx Load String Word Indexed PPC440x5 CPU Core User’s Manual Preliminary Programming Note This instruction can be restarted, meaning that it could be interrupted after having already updated some of the target registers, and then re-executed from the beginning (after returning from the interrupt), in which case the registers which had already been loaded prior to the interrupt will be loaded a second time.
lwarx Load Word and Reserve Indexed PPC440x5 CPU Core User’s Manual Preliminary lwarx Load Word and Reserve Indexed lwarx RT, RA, RB 31 RT 0 6 RA 11 RB 16 20 21 31 EA ← (RA|0) + (RB) RESERVE ← 1 (RT) ← MS(EA,4) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise. The word at the EA is placed into register RT.
lwbrx Load Word Byte-Reverse Indexed PPC440x5 CPU Core User’s Manual Preliminary lwbrx Load Word Byte-Reverse Indexed lwbrx RT, RA, RB 31 0 RT 6 RA 11 RB 16 534 21 31 EA ← (RA|0) + (RB) (RT) ← BYTE_REVERSE(MS(EA,4)) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
lwz Load Word and Zero PPC440x5 CPU Core User’s Manual Preliminary lwz Load Word and Zero lwz RT, D(RA) 32 0 RT 6 RA 11 D 16 31 EA ← (RA|0) + EXTS(D) (RT) ← MS(EA,4) An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise. The word at the EA is placed into register RT. Registers Altered • RT instrset.fm.
lwzu Load Word and Zero with Update PPC440x5 CPU Core User’s Manual Preliminary lwzu Load Word and Zero with Update lwzu RT, D(RA) 33 0 RT 6 RA 11 D 16 31 EA ← (RA|0) + EXTS(D) (RA) ← EA (RT) ← MS(EA,4) An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise. The EA is placed into register RA.
lwzux Load Word and Zero with Update Indexed PPC440x5 CPU Core User’s Manual Preliminary lwzux Load Word and Zero with Update Indexed lwzux RT, RA, RB 31 0 RT 6 RA 11 RB 16 55 21 31 EA ← (RA|0) + (RB) (RA) ← EA (RT) ← MS(EA,4) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise. The EA is placed into register RA.
lwzx Load Word and Zero Indexed PPC440x5 CPU Core User’s Manual Preliminary lwzx Load Word and Zero Indexed lwzx RT, RA, RB 31 0 RT 6 RA 11 RB 16 23 21 31 EA ← (RA|0) + (RB) (RT) ← MS(EA,4) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise. The word at the EA is placed into register RT.
macchw Multiply Accumulate Cross Halfword to Word Modulo Signed PPC440x5 CPU Core User’s Manual Preliminary macchw Multiply Accumulate Cross Halfword to Word Modulo Signed macchw macchw. macchwo macchwo. RT, RA, RB RT, RA, RB RT, RA, RB RT, RA, RB 4 0 OE=0, Rc=0 OE=0, Rc=1 OE=1, Rc=0 OE=1, Rc=1 RT 6 RA 11 RB 16 OE 21 22 172 Rc 31 prod0:31 ← (RA)16:31 × (RB)0:15 signed temp0:32 ← prod0:31 + (RT) (RT) ← temp1:32 The low-order halfword of RA is multiplied by the high-order halfword of RB.
macchws Multiply Accumulate Cross Halfword to Word Saturate Signed PPC440x5 CPU Core User’s Manual Preliminary macchws Multiply Accumulate Cross Halfword to Word Saturate Signed macchws macchws. macchwso macchwso.
macchwsu Multiply Accumulate Cross Halfword to Word Saturate Unsigned PPC440x5 CPU Core User’s Manual Preliminary macchwsu Multiply Accumulate Cross Halfword to Word Saturate Unsigned macchwsu macchwsu. macchwsuo macchwsuo.
macchwu Multiply Accumulate Cross Halfword to Word Modulo Unsigned PPC440x5 CPU Core User’s Manual Preliminary macchwu Multiply Accumulate Cross Halfword to Word Modulo Unsigned macchwu macchwu. macchwuo macchwuo.
machhw Multiply Accumulate High Halfword to Word Modulo Signed PPC440x5 CPU Core User’s Manual Preliminary machhw Multiply Accumulate High Halfword to Word Modulo Signed machhw machhw. machhwo machhwo. RT, RA, RB RT, RA, RB RT, RA, RB RT, RA, RB 4 0 OE=0, Rc=0 OE=0, Rc=1 OE=1, Rc=0 OE=1, Rc=1 RT 6 RA 11 RB 16 OE 21 22 44 Rc 31 prod0:31 ← (RA)0:15 × (RB)0:15 signed temp0:32 ← prod0:31 + (RT) (RT) ← temp1:32 The high-order halfword of RA is multiplied by the high-order halfword of RB.
machhws Multiply Accumulate High Halfword to Word Saturate Signed PPC440x5 CPU Core User’s Manual Preliminary machhws Multiply Accumulate High Halfword to Word Saturate Signed machhws machhws. machhwso machhwso.
machhwsu Multiply Accumulate High Halfword to Word Saturate Unsigned PPC440x5 CPU Core User’s Manual Preliminary machhwsu Multiply Accumulate High Halfword to Word Saturate Unsigned machhwsu machhwsu. machhwsuo machhwsuo.
machhwu Multiply Accumulate High Halfword to Word Modulo Unsigned PPC440x5 CPU Core User’s Manual Preliminary machhwu Multiply Accumulate High Halfword to Word Modulo Unsigned machhwu machhwu. machhwuo machhwuo.
maclhw Multiply Accumulate Low Halfword to Word Modulo Signed PPC440x5 CPU Core User’s Manual Preliminary maclhw Multiply Accumulate Low Halfword to Word Modulo Signed maclhw maclhw. maclhwo maclhwo. RT, RA, RB RT, RA, RB RT, RA, RB RT, RA, RB 4 0 OE=0, Rc=0 OE=0, Rc=1 OE=1, Rc=0 OE=1, Rc=1 RT 6 RA 11 RB 16 OE 21 22 428 Rc 31 prod0:31 ← (RA)16:31 × (RB)16:31 signed temp0:32 ← prod0:31 + (RT) (RT) ← temp1:32 The low-order halfword of RA is multiplied by the low-order halfword of RB.
maclhws Multiply Accumulate Low Halfword to Word Saturate Signed PPC440x5 CPU Core User’s Manual Preliminary maclhws Multiply Accumulate Low Halfword to Word Saturate Signed maclhws maclhws. maclhwso maclhwso.
maclhwsu Multiply Accumulate Low Halfword to Word Saturate Unsigned PPC440x5 CPU Core User’s Manual Preliminary maclhwsu Multiply Accumulate Low Halfword to Word Saturate Unsigned maclhwsu maclhwsu. maclhwsuo maclhwsuo.
maclhwu Multiply Accumulate Low Halfword to Word Modulo Unsigned PPC440x5 CPU Core User’s Manual Preliminary maclhwu Multiply Accumulate Low Halfword to Word Modulo Unsigned maclhwu maclhwu. maclhwuo maclhwuo. RT, RA, RB RT, RA, RB RT, RA, RB RT, RA, RB 4 0 OE=0, Rc=0 OE=0, Rc=1 OE=1, Rc=0 OE=1, Rc=1 RT 6 RA 11 RB 16 OE 21 22 396 Rc 31 prod0:31 ← (RA)16:31 × (RB)16:31 unsigned temp0:32 ← prod0:31 + (RT) (RT) ← temp1:32 The low-order halfword of RA is multiplied by the low-order halfword of RB.
mbar Memory Barrier PPC440x5 CPU Core User’s Manual Preliminary mbar Memory Barrier mbar 31 0 854 6 21 31 The mbar instruction ensures that all loads and stores preceding mbar complete with respect to main storage before any loads and stores following mbar access main storage. If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
mcrf Move Condition Register Field PPC440x5 CPU Core User’s Manual Preliminary mcrf Move Condition Register Field mcrf BF, BFA 19 0 BF 6 BFA 9 11 0 14 21 31 m ← BFA n ← BF (CR[CRn]) ← (CR[CRm]) The contents of the CR field specified by the BFA field are placed into the CR field specified by the BF field. Registers Altered • CR[CRn] where n is specified by the BF field. Invalid Instruction Forms • Reserved fields Page 358 of 589 instrset.fm.
mcrxr Move to Condition Register from XER PPC440x5 CPU Core User’s Manual Preliminary mcrxr Move to Condition Register from XER mcrxr BF 31 0 BF 6 512 9 21 31 n ← BF (CR[CRn]) ← XER0:3 XER0:3 ← 40 The contents of XER0:3 are placed into the CR field specified by the BF field. XER0:3 are then set to 0. If instruction bit 31 contains 1, the contents of CR[CR0] are undefined. Registers Altered • CR[CRn] where n is specified by the BF field.
mfcr Move From Condition Register PPC440x5 CPU Core User’s Manual Preliminary mfcr Move From Condition Register mfcr RT 31 0 RT 6 19 11 21 31 (RT) ← (CR) The contents of the CR are placed into register RT. If instruction bit 31 contains 1, the contents of CR[CR0] are undefined. Registers Altered • RT Invalid Instruction Forms • Reserved fields Page 360 of 589 instrset.fm.
mfdcr Move from Device Control Register PPC440x5 CPU Core User’s Manual Preliminary mfdcr Move from Device Control Register mfdcr RT, DCRN 31 0 RT 6 DCRF 11 323 21 31 DCRN ← DCRF5:9 || DCRF0:4 (RT) ← (DCR(DCRN)) The contents of the DCR specified by the DCRF field are placed into register RT. If instruction bit 31 contains 1, the contents of CR[CR0] are undefined. Registers Altered • RT Invalid Instruction Forms • Reserved fields Programming Notes Execution of this instruction is privileged.
mfmsr Move From Machine State Register PPC440x5 CPU Core User’s Manual Preliminary mfmsr Move From Machine State Register mfmsr RT 31 0 RT 6 83 11 21 31 (RT) ← (MSR) The contents of the MSR are placed into register RT. If instruction bit 31 contains 1, the contents of CR[CR0] are undefined. Registers Altered • RT Invalid Instruction Forms • Reserved fields Programming Note Execution of this instruction is privileged. Page 362 of 589 instrset.fm.
mfspr Move From Special Purpose Register PPC440x5 CPU Core User’s Manual Preliminary mfspr Move From Special Purpose Register mfspr RT, SPRN 31 0 RT 6 SPRF 11 339 21 31 SPRN ← SPRF5:9 || SPRF0:4 (RT) ← (SPR(SPRN)) The contents of the SPR specified by the SPRF field are placed into register RT. See Special Purpose Registers Sorted by SPR Number on page 454 for a listing of SPR mnemonics and corresponding SPRN values. If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
mfspr Move From Special Purpose Register PPC440x5 CPU Core User’s Manual Preliminary Table 9-19.
mfspr Move From Special Purpose Register PPC440x5 CPU Core User’s Manual Preliminary Table 9-19. Extended Mnemonics for mfspr (continued) Mnemonic Operands Function mfivor5 mfivor6 mfivor7 mfivor8 mfivor9 mfivor10 mfivor11 mfivor12 mfivor13 mfivor14 mfivor15 mfivpr mflr mfmcsr mfmcsrr0 mfmcsrr1 mfmmucr mfpid mfpir mfpvr mfsprg0 mfsprg1 mfsprg2 mfsprg3 mfsprg4 mfsprg5 mfsprg6 mfsprg7 mfsrr0 mfsrr1 mftbl mftbu mftcr mftsr mfusprg0 mfxer instrset.fm.
msync Memory Synchronize PPC440x5 CPU Core User’s Manual Preliminary msync Memory Synchronize msync 31 0 598 6 21 31 The msync instruction guarantees that all instructions initiated by the processor preceding msync will complete before msync completes, and that no subsequent instructions will be initiated by the processor until after msync completes. msync also will not complete until all storage accesses associated with instructions preceding msync have completed.
mtcrf Move to Condition Register Fields PPC440x5 CPU Core User’s Manual Preliminary mtcrf Move to Condition Register Fields mtcrf FXM, RS 31 RS 0 6 FXM 144 11 12 20 21 31 mask ← 4(FXM0) || 4(FXM1) || ... || 4(FXM6) || 4(FXM7) (CR) ← ((RS) ∧ mask) ∨ ((CR) ∧ ¬mask) Some or all of the contents of register RS are placed into the CR as specified by the FXM field. Each bit in the FXM field controls the copying of 4 bits in register RS into the corresponding bits in the CR.
mtdcr Move To Device Control Register PPC440x5 CPU Core User’s Manual Preliminary mtdcr Move To Device Control Register mtdcr DCRN, RS 31 0 RS 6 DCRF 11 451 21 31 DCRN ← DCRF5:9 || DCRF0:4 (DCR(DCRN)) ← (RS) The contents of register RS are placed into the DCR specified by the DCRF field. If instruction bit 31 contains 1, the contents of CR[CR0] are undefined. Registers Altered • DCR(DCRN) Invalid Instruction Forms • Reserved fields Programming Note Execution of this instruction is privileged.
mtmsr Move To Machine State Register PPC440x5 CPU Core User’s Manual Preliminary mtmsr Move To Machine State Register mtmsr RS 31 0 RS 6 146 11 21 31 (MSR) ← (RS) The contents of register RS are placed into the MSR. If instruction bit 31 contains 1, the contents of CR[CR0] are undefined. Registers Altered • MSR Invalid Instruction Forms • Reserved fields Programming Note The mtmsr instruction is privileged and execution synchronizing (see Execution Synchronization on page 83). instrset.fm.
mtspr Move To Special Purpose Register PPC440x5 CPU Core User’s Manual Preliminary mtspr Move To Special Purpose Register mtspr SPRN, RS 31 0 RS 6 SPRF 11 467 21 31 SPRN ← SPRF5:9 || SPRF0:4 (SPR(SPRN)) ← (RS) The contents of register RS are placed into register RT. See Special Purpose Registers Sorted by SPR Number on page 454 for a listing of SPR mnemonics and corresponding SPRN values. If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
mtspr Move To Special Purpose Register PPC440x5 CPU Core User’s Manual Preliminary Table 9-22. Extended Mnemonics for mtspr Mnemonic mtccr0 mtccr1 mtcsrr0 mtcsrr1 mtctr mtdac1 mtdac2 mtdbcr0 mtdbcr1 mtdbcr2 mtdbdr mtdbsr mtdear mtdec mtdecar mtdnv0 mtdnv1 mtdnv2 mtdnv3 mtdtv0 mtdtv1 mtdtv2 mtdtv3 mtdvc1 mtdvc2 mtdvlim mtesr mtiac1 mtiac2 mtiac3 mtiac4 mtinv0 mtinv1 mtinv2 mtinv3 mtitv0 mtitv1 mtitv2 mtitv3 mtivlim mtivor0 mtivor1 mtivor2 mtivor3 mtivor4 instrset.fm.
mtspr Move To Special Purpose Register PPC440x5 CPU Core User’s Manual Preliminary Table 9-22. Extended Mnemonics for mtspr (continued) Mnemonic Operands Function mtivor5 mtivor6 mtivor7 mtivor8 mtivor9 mtivor10 mtivor11 mtivor12 mtivor13 mtivor14 mtivor15 mtivpr mtlr mtmcsr mtmcsrr0 mtmcsrr1 mtmmucr mtpid mtsprg0 mtsprg1 mtsprg2 mtsprg3 mtsprg4 mtsprg5 mtsprg6 mtsprg7 mtsrr0 mtsrr1 mttbl mttbu mttcr mttsr mtusprg0 mtxer Page 372 of 589 instrset.fm.
mulchw Multiply Cross Halfword to Word Signed PPC440x5 CPU Core User’s Manual Preliminary mulchw Multiply Cross Halfword to Word Signed mulchw mulchw. RT, RA, RB RT, RA, RB 4 0 Rc=0 Rc=1 RT 6 RA 11 RB 16 168 21 Rc 31 (RT)0:31 ← (RA)16:31 × (RB)0:15 signed The low-order halfword of RA is multiplied by the high-order halfword of RB, considering both source operands as signed integers. The 32-bit result is placed into register RT.
mulchwu Multiply Cross Halfword to Word Unsigned PPC440x5 CPU Core User’s Manual Preliminary mulchwu Multiply Cross Halfword to Word Unsigned mulchwu mulchwu. RT, RA, RB RT, RA, RB 4 0 Rc=0 Rc=1 RT 6 RA 11 RB 16 136 21 Rc 31 (RT)0:31 ← (RA)16:31 × (RB)0:15 unsigned The low-order halfword of RA is multiplied by the high-order halfword of RB, considering both source operands as unsigned integers. The 32-bit result is placed into register RT.
mulhhw Multiply High Halfword to Word Signed PPC440x5 CPU Core User’s Manual Preliminary mulhhw Multiply High Halfword to Word Signed mulhhw mulhhw. RT, RA, RB RT, RA, RB 4 0 Rc=0 Rc=1 RT 6 RA 11 RB 16 40 21 Rc 31 (RT)0:31 ← (RA)0:15 × (RB)0:15 signed The high-order halfword of RA is multiplied by the high-order halfword of RB, considering both source operands as signed integers. The 32-bit result is placed into register RT.
mulhhwu Multiply High Halfword to Word Unsigned PPC440x5 CPU Core User’s Manual Preliminary mulhhwu Multiply High Halfword to Word Unsigned mulhhwu mulhhwu. RT, RA, RB RT, RA, RB 4 0 Rc=0 Rc=1 RT 6 RA 11 RB 16 8 21 Rc 31 (RT)0:31 ← (RA)0:15 × (RB)0:15 unsigned The high-order halfword of RA is multiplied by the high-order halfword of RB, considering both source operands as unsigned integers. The 32-bit result is placed into register RT.
mulhw Multiply High Word PPC440x5 CPU Core User’s Manual Preliminary mulhw Multiply High Word mulhw mulhw. RT, RA, RB RT, RA, RB 31 0 Rc=0 Rc=1 RT 6 RA 11 RB 16 75 Rc 21 22 31 prod0:63 ← (RA) × (RB) signed (RT) ← prod0:31 The 64-bit signed product of registers RA and RB is formed. The most significant 32 bits of the result is placed into register RT.
mulhwu Multiply High Word Unsigned PPC440x5 CPU Core User’s Manual Preliminary mulhwu Multiply High Word Unsigned mulhwu mulhwu. RT, RA, RB RT, RA, RB 31 0 Rc=0 Rc=1 RT 6 RA 11 RB 16 11 21 22 Rc 31 prod0:63 ← (RA) × (RB) unsigned (RT) ← prod0:31 The 64-bit unsigned product of registers RA and RB is formed. The most significant 32 bits of the result are placed into register RT.
mullhw Multiply Low Halfword to Word Signed PPC440x5 CPU Core User’s Manual Preliminary mullhw Multiply High Halfword to Word Signed mullhw mullhw. RT, RA, RB RT, RA, RB 4 0 Rc=0 Rc=1 RT 6 RA 11 RB 16 424 21 Rc 31 (RT)0:31 ← (RA)16:31 × (RB)16:31 signed The low-order halfword of RA is multiplied by the low-order halfword of RB, considering both source operands as signed integers. The 32-bit result is placed into register RT.
mullhwu Multiply Low Halfword to Word Unsigned PPC440x5 CPU Core User’s Manual Preliminary mullhwu Multiply High Halfword to Word Unsigned mullhwu mullhwu. RT, RA, RB RT, RA, RB 4 0 Rc=0 Rc=1 RT 6 RA 11 RB 16 392 21 Rc 31 (RT)0:31 ← (RA)16:31 × (RB)16:31 unsigned The low-order halfword of RA is multiplied by the low-order halfword of RB, considering both source operands as unsigned integers. The 32-bit result is placed into register RT.
mulli Multiply Low Immediate PPC440x5 CPU Core User’s Manual Preliminary mulli Multiply Low Immediate mulli RT, RA, IM 7 0 RT 6 RA 11 IM 16 31 prod0:47 ← (RA) × IM (RT) ← prod16:47 The 48-bit product of register RA and the 16-bit IM field is formed. The least significant 32 bits of the product are placed into register RT.
mullw Multiply Low Word PPC440x5 CPU Core User’s Manual Preliminary mullw Multiply Low Word mullw mullw. mullwo mullwo. RT, RA, RB RT, RA, RB RT, RA, RB RT, RA, RB 31 0 OE=0, Rc=0 OE=0, Rc=1 OE=1, Rc=0 OE=1, Rc=1 RT 6 RA 11 RB 16 OE 235 Rc 21 22 31 prod0:63 ← (RA) × (RB) signed (RT) ← prod32:63 The 64-bit signed product of register RA and register RB is formed. The least significant 32 bits of the result is placed into register RT.
nand NAND PPC440x5 CPU Core User’s Manual Preliminary nand NAND nand nand. RA, RS, RB RA, RS, RB 31 0 Rc=0 Rc=1 RT 6 RA 11 RB 16 476 21 Rc 31 (RA) ← ¬((RS) ∧ (RB)) The contents of register RS is ANDed with the contents of register RB; the ones complement of the result is placed into register RA. Registers Altered • RA • CR[CR0] if Rc contains 1 instrset.fm.
neg Negate PPC440x5 CPU Core User’s Manual Preliminary neg Negate neg neg. nego nego. RT, RA RT, RA RT, RA RT, RA 31 0 OE=0, Rc=0 OE=0, Rc=1 OE=1, Rc=0 OE=1, Rc=1 RT 6 RA 11 OE 16 21 22 104 Rc 31 (RT) ← ¬(RA) + 1 The twos complement of the contents of register RA are placed into register RT. Registers Altered • RT • CR[CR0] if Rc contains 1 • XER[SO, OV] if OE=1 Invalid Instruction Forms • Reserved fields Page 384 of 589 instrset.fm.
nmacchw Negative Multiply Accumulate Cross Halfword to Word Modulo Signed PPC440x5 CPU Core User’s Manual Preliminary nmacchw Negative Multiply Accumulate Cross Halfword to Word Modulo Signed nmacchw nmacchw. nmacchwo nmacchwo.
nmacchws Negative Multiply Accumulate Cross Halfword to Word Saturate Signed PPC440x5 CPU Core User’s Manual Preliminary nmacchws Negative Multiply Accumulate High Halfword to Word Saturate Signed nmacchws nmacchws. nmacchwso nmacchwso.
nmachhw Negative Multiply Accumulate High Halfword to Word Modulo Signed PPC440x5 CPU Core User’s Manual Preliminary nmachhw Negative Multiply Accumulate High Halfword to Word Modulo Signed nmachhw nmachhw. nmachhwo nmachhwo.
nmachhws Negative Multiply Accumulate High Halfword to Word Saturate Signed PPC440x5 CPU Core User’s Manual Preliminary nmachhws Negative Multiply Accumulate High Halfword to Word Saturate Signed nmachhws nmachhws. nmachhwso nmachhwso.
nmaclhw Negative Multiply Accumulate Low Halfword to Word Modulo Signed PPC440x5 CPU Core User’s Manual Preliminary nmaclhw Negative Multiply Accumulate Low Halfword to Word Modulo Signed nmaclhw nmaclhw. nmaclhwo nmaclhwo.
nmaclhws Negative Multiply Accumulate High Halfword to Word Saturate Signed PPC440x5 CPU Core User’s Manual Preliminary nmaclhws Negative Multiply Accumulate Low Halfword to Word Saturate Signed nmaclhws nmaclhws. nmaclhwso nmaclhwso.
nor NOR PPC440x5 CPU Core User’s Manual Preliminary nor NOR nor nor. RA, RS, RB RA, RS, RB 31 Rc=0 Rc=1 RT 0 6 RA 11 RB 16 124 Rc 21 31 (RA) ← ¬((RS) ∨ (RB)) The contents of register RS is ORed with the contents of register RB; the ones complement of the result is placed into register RA. Registers Altered • RA • CR[CR0] if Rc contains 1 Table 9-23. Extended Mnemonics for nor, nor. Mnemonic Operands RA, RS instrset.fm. September 12, 2002 Other Registers Altered Complement register.
or OR PPC440x5 CPU Core User’s Manual Preliminary or OR or or. RA, RS, RB RA, RS, RB 31 Rc=0 Rc=1 RS 0 6 RA 11 RB 16 444 Rc 21 31 (RA) ← (RS) ∨ (RB) The contents of register RS is ORed with the contents of register RB; the result is placed into register RA. Registers Altered • RA • CR[CR0] if Rc contains 1 Table 9-24. Extended Mnemonics for or, or. Mnemonic Operands RT, RS Page 392 of 589 Other Registers Altered Move register. (RT) ← (RS) mr mr.
orc OR with Complement PPC440x5 CPU Core User’s Manual Preliminary orc OR with Complement orc orc. RA, RS, RB RA, RS, RB 31 0 Rc=0 Rc=1 RT 6 RA 11 RB 16 412 21 Rc 31 (RA) ← (RS) ∨ ¬(RB) The contents of register RS is ORed with the ones complement of the contents of register RB; the result is placed into register RA. Registers Altered • RA • CR[CR0] if Rc contains 1 instrset.fm.
ori OR Immediate PPC440x5 CPU Core User’s Manual Preliminary ori OR Immediate ori RA, RS, IM 24 0 RS 6 RA 11 IM 16 31 (RA) ← (RS) ∨ (160 || IM) The IM field is extended to 32 bits by concatenating 16 0-bits on the left. Register RS is ORed with the extended IM field; the result is placed into register RA. Registers Altered • RA Table 9-25. Extended Mnemonics for ori Mnemonic Operands Function Other Registers Changed Preferred no-op; triggers optimizations based on no-ops.
oris OR Immediate Shifted PPC440x5 CPU Core User’s Manual Preliminary oris OR Immediate Shifted oris RA, RS, IM 25 0 RS 6 RA 11 IM 16 31 (RA) ← (RS) ∨ (IM || 160) The IM Field is extended to 32 bits by concatenating 16 0-bits on the right. Register RS is ORed with the extended IM field and the result is placed into register RA. Registers Altered • RA instrset.fm.
rfci Return From Critical Interrupt PPC440x5 CPU Core User’s Manual Preliminary rfci Return From Critical Interrupt rfci 19 0 51 6 21 31 (PC) ← (CSRR0) (MSR) ← (CSRR1) This instruction is used to return from a critical interrupt. The program counter (PC) is restored with the contents of CSRR0 and the MSR is restored with the contents of CSRR1. Instruction execution returns to the address contained in the PC.
rfi Return From Interrupt PPC440x5 CPU Core User’s Manual Preliminary rfi Return From Interrupt rfi 19 0 50 6 21 31 (PC) ← (SRR0) (MSR) ← (SRR1) This instruction is used to return from a non-critical interrupt. The program counter (PC) is restored with the contents of SRR0 and the MSR is restored with the contents of SRR1. Instruction execution returns to the address contained in the PC.
rfmci Return From Machine Check Interrupt PPC440x5 CPU Core User’s Manual Preliminary rfmci Return From Critical Interrupt rfmci 19 0 38 6 21 31 (PC) ← (MCSRR0) (MSR) ← (MCSRR1) This instruction is used to return from a machine check interrupt. The program counter (PC) is restored with the contents of MCSRR0 and the MSR is restored with the contents of MCSRR1. Instruction execution returns to the address contained in the PC.
rlwimi Rotate Left Word Immediate then Mask Insert PPC440x5 CPU Core User’s Manual Preliminary rlwimi Rotate Left Word Immediate then Mask Insert rlwimi rlwimi. RA, RS, SH, MB, ME RA, RS, SH, MB, ME 20 RS 0 Rc=0 Rc=1 RA 6 11 SH 16 MB 21 ME 26 Rc 31 r ← ROTL((RS), SH) m ← MASK(MB, ME) (RA) ← (r ∧ m) ∨ ((RA) ∧ ¬m) The contents of register RS are rotated left by the number of bit positions specified in the SH field.
rlwinm Rotate Left Word Immediate then AND with Mask PPC440x5 CPU Core User’s Manual Preliminary rlwinm Rotate Left Word Immediate then AND with Mask rlwinm rlwinm. RA, RS, SH, MB, ME RA, RS, SH, MB, ME 21 RS 0 6 Rc=0 Rc=1 RA 11 SH 16 MB 21 ME 26 Rc 31 r ← ROTL((RS), SH) m ← MASK(MB, ME) (RA) ← r ∧ m The contents of register RS are rotated left by the number of bit positions specified in the SH field.
rlwinm Rotate Left Word Immediate then AND with Mask PPC440x5 CPU Core User’s Manual Preliminary Table 9-27. Extended Mnemonics for rlwinm, rlwinm. (continued) Mnemonic Operands RA, RS, n rlwinm RA,RS,0,0,31−n Extended mnemonic for rlwinm. RA,RS,0,0,31−n clrrwi. CR[CR0] Extract and left justify immediate. (n > 0) (RA)0:n-1 ← (RS)b:b+n-1 32-n (RA)n:31 ← 0 extlwi RA, RS, n, b Extended mnemonic for rlwinm RA,RS,b,0,n−1 Extended mnemonic for rlwinm. RA,RS,b,0,n−1 extlwi.
rlwinm Rotate Left Word Immediate then AND with Mask PPC440x5 CPU Core User’s Manual Preliminary Table 9-27. Extended Mnemonics for rlwinm, rlwinm. (continued) Mnemonic Operands RA, RS, n Page 402 of 589 Other Registers Altered Shift right immediate. (n < 32) (RA)n:31 ← (RS)0:31-n n (RA)0:n-1 ← 0 srwi srwi. Function Extended mnemonic for rlwinm RA,RS,32−n,n,31 Extended mnemonic for rlwinm. RA,RS,32−n,n,31 CR[CR0] instrset.fm.
rlwnm Rotate Left Word then AND with Mask PPC440x5 CPU Core User’s Manual Preliminary rlwnm Rotate Left Word then AND with Mask rlwnm rlwnm. RA, RS, RB, MB, ME RA, RS, RB, MB, ME 23 RS 0 6 Rc=0 Rc=1 RA 11 RB 16 MB 21 ME 26 Rc 31 r ← ROTL((RS), (RB)27:31) m ← MASK(MB, ME) (RA) ← r ∧ m The contents of register RS are rotated left by the number of bit positions specified by the contents of register RB27:31.
sc System Call PPC440x5 CPU Core User’s Manual Preliminary sc System Call sc 17 0 1 6 30 31 SRR1 ← MSR SRR0 ← 4 + address of sc instruction PC ← IVPR0:15 || IVOR816:27 || 40 MSR[WE, EE, PR, FP, FE0, FE1, DWE, DS, IS] ← 90 A System Call exception is generated, and a System Call interrupt occurs (see System Call Interrupt on page 190 for more information on System Call interrupts). The contents of the MSR are copied into SRR1 and (4 + address of sc instruction) is placed into SRR0.
slw Shift Left Word PPC440x5 CPU Core User’s Manual Preliminary slw Shift Left Word slw slw. RA, RS, RB RA, RS, RB 31 0 Rc=0 Rc=1 RS 6 RA 11 RB 16 24 Rc 21 31 n ← (RB)26:31 r ← ROTL((RS), n) if n < 32 then m ← MASK(0, 31 – n) else m ← 320 (RA) ← r ∧ m The contents of register RS are shifted left by the number of bits specified by the contents of register RB26:31. Bits shifted left out of the most significant bit are lost, and 0-bits fill vacated bit positions on the right.
sraw Shift Right Algebraic Word PPC440x5 CPU Core User’s Manual Preliminary sraw Shift Right Algebraic Word sraw sraw. RA, RS, RB RA, RS, RB 31 0 Rc=0 Rc=1 RS 6 RA 11 RB 16 792 Rc 21 31 n ← (RB)26:31 r ← ROTL((RS), 32 – n) if n < 32 then m ← MASK(n, 31) else m ← 320 s ← (RS)0 (RA) ← (r ∧ m) ∨ (32s ∧ ¬m) XER[CA] ← s ∧ ((r ∧ ¬m) ≠ 0) The contents of register RS are shifted right by the number of bits specified the contents of register RB26:31.
srawi Shift Right Algebraic Word Immediate PPC440x5 CPU Core User’s Manual Preliminary srawi Shift Right Algebraic Word Immediate srawi srawi. RA, RS, SH RA, RS, SH 31 0 Rc=0 Rc=1 RS 6 RA 11 SH 16 824 21 Rc 31 n ← SH r ← ROTL((RS), 32 – n) m ← MASK(n, 31) s ← (RS)0 (RA) ← (r ∧ m) ∨ (32s ∧ ¬m) XER[CA] ← s ∧ ((r ∧ ¬m)≠0) The contents of register RS are shifted right by the number of bits specified in the SH field. Bits shifted out of the least significant bit are lost.
srw Shift Right Word PPC440x5 CPU Core User’s Manual Preliminary srw Shift Right Word srw srw. RA, RS, RB RA, RS, RB 31 0 Rc=0 Rc=1 RS 6 RA 11 RB 16 536 Rc 21 31 n ← (RB)26:31 r ← ROTL((RS), 32 – n) if n < 32 then m ← MASK(n, 31) else m ← 320 (RA) ← r ∧ m The contents of register RS are shifted right by the number of bits specified the contents of register RB26:31. Bits shifted right out of the least significant bit are lost, and 0-bits fill the vacated bit positions on the left.
stb Store Byte PPC440x5 CPU Core User’s Manual Preliminary stb Store Byte stb RS, D(RA) 38 0 RS 6 RA 11 D 16 31 EA ← (RA|0) + EXTS(D) MS(EA, 1) ← (RS)24:31 An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits. The base address is 0 when the RA field is 0, and is the contents of register RA otherwise. The least significant byte of register RS is stored into the byte at the EA.
stbu Store Byte with Update PPC440x5 CPU Core User’s Manual Preliminary stbu Store Byte with Update stbu RS, D(RA) 39 0 RS 6 RA 11 D 16 31 EA ← (RA|0) + EXTS(D) MS(EA, 1) ← (RS)24:31 (RA) ← EA An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits. The base address is 0 when the RA field is 0, and is the contents of register RA otherwise.
stbux Store Byte with Update Indexed PPC440x5 CPU Core User’s Manual Preliminary stbux Store Byte with Update Indexed stbux RS, RA, RB 31 0 RS 6 RA 11 RB 16 247 21 31 EA ← (RA|0) + (RB) MS(EA, 1) ← (RS)24:31 (RA) ← EA An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB. The base address is 0 when the RA field is 0, and is the contents of register RA otherwise.
stbx Store Byte Indexed PPC440x5 CPU Core User’s Manual Preliminary stbx Store Byte Indexed stbx RS, RA, RB 31 0 RS 6 RA 11 RB 16 215 21 31 EA ← (RA|0) + (RB) MS(EA, 1) ← (RS)24:31 An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB. The base address is 0 when the RA field is 0, and is the contents of register RA otherwise. The least significant byte of register RS is stored into the byte at the EA.
sth Store Halfword PPC440x5 CPU Core User’s Manual Preliminary sth Store Halfword sth RS, D(RA) 44 0 RS 6 RA 11 D 16 31 EA ← (RA|0) + EXTS(D) MS(EA, 2) ← (RS)16:31 An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits. The base address is 0 when the RA field is 0 and is the contents of register RA otherwise.
sthbrx Store Halfword Byte-Reverse Indexed PPC440x5 CPU Core User’s Manual Preliminary sthbrx Store Halfword Byte-Reverse Indexed sthbrx RS, RA, RB 31 0 RS 6 RA 11 RB 16 918 21 31 EA ← (RA|0) + (RB) MS(EA, 2) ← BYTE_REVERSE((RS)16:31) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB. The base address is 0 when the RA field is 0 and is the contents of register RA otherwise.
sthu Store Halfword with Update PPC440x5 CPU Core User’s Manual Preliminary sthu Store Halfword with Update sthu RS, D(RA) 45 0 RS 6 RA 11 D 16 31 EA ← (RA|0) + EXTS(D) MS(EA, 2) ← (RS)16:31 (RA) ← EA An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits. The base address is 0 when the RA field is 0, and is the contents of register RA otherwise.
sthux Store Halfword with Update Indexed PPC440x5 CPU Core User’s Manual Preliminary sthux Store Halfword with Update Indexed sthux RS, RA, RB 31 0 RS 6 RA 11 RB 16 439 21 31 EA ← (RA|0) + (RB) MS(EA, 2) ← (RS)16:31 (RA) ← EA An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB. The base address is 0 when the RA field is 0, and is the contents of register RA otherwise.
sthx Store Halfword Indexed PPC440x5 CPU Core User’s Manual Preliminary sthx Store Halfword Indexed sthx RS, RA, RB 31 0 RS 6 RA 11 RB 16 407 21 31 EA ← (RA|0) + (RB) MS(EA, 2) ← (RS)16:31 An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB. The base address is 0 when the RA field is 0, and is the contents of register RA otherwise. The least significant halfword of register RS is stored into the halfword at the EA.
stmw Store Multiple Word PPC440x5 CPU Core User’s Manual Preliminary stmw Store Multiple Word stmw RS, D(RA) 47 0 RS 6 RA 11 D 16 31 EA ← (RA|0) + EXTS(D) r ← RS do while r ≤ 31 MS(EA, 4) ← (GPR(r)) r ← r + 1 EA ← EA + 4 An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits. The base address is 0 when the RA field is 0, and is the contents of register RA otherwise.
stswi Store String Word Immediate PPC440x5 CPU Core User’s Manual Preliminary stswi Store String Word Immediate stswi RS, RA, NB 31 0 RS 6 RA 11 NB 16 725 21 31 EA ← (RA|0) if NB = 0 then n ← 32 else n ← NB r ← RS – 1 i ← 0 do while n > 0 if i = 0 then r ← r + 1 if r = 32 then r ← 0 MS(EA,1) ← (GPR(r)i:i+7) i ← i + 8 if i = 32 then i ← 0 EA ← EA + 1 n ← n – 1 An effective address (EA) is determined by the RA field.
stswi Store String Word Immediate PPC440x5 CPU Core User’s Manual Preliminary Programming Note This instruction can be restarted, meaning that it could be interrupted after having already stored some of the register values to memory, and then re-executed from the beginning (after returning from the interrupt), in which case the registers which had already been stored prior to the interrupt will be stored a second time. Page 420 of 589 instrset.fm.
stswx Store String Word Indexed PPC440x5 CPU Core User’s Manual Preliminary stswx Store String Word Indexed stswx RS, RA, RB 31 0 RS 6 RA 11 RB 16 661 21 31 EA ← (RA|0) + (RB) n ← XER[TBC] r ← RS – 1 i ← 0 do while n > 0 if i = 0 then r ← r + 1 if r = 32 then r ← 0 MS(EA, 1) ← (GPR(r)i:i+7) i ← i + 8 if i = 32 then i ← 0 EA ← EA + 1 n ← n – 1 An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
stw Store Word PPC440x5 CPU Core User’s Manual Preliminary stw Store Word stw RS, D(RA) 36 0 RS 6 RA 11 D 16 31 EA ← (RA|0) + EXTS(D) MS(EA, 4) ← (RS) An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits. The base address is 0 when the RA field is 0, and is the contents of register RA otherwise. The contents of register RS are stored at the EA.
stwbrx Store Word Byte-Reverse Indexed PPC440x5 CPU Core User’s Manual Preliminary stwbrx Store Word Byte-Reverse Indexed stwbrx RS, RA, RB 31 0 RS 6 RA 11 RB 16 662 21 31 EA ← (RA|0) + (RB) MS(EA, 4) ← BYTE_REVERSE((RS)0:31) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB. The base address is 0 when the RA field is 0 and is the contents of register RA otherwise.
stwcx. Store Word Conditional Indexed PPC440x5 CPU Core User’s Manual Preliminary stwcx. Store Word Conditional Indexed stwcx. RS, RA, RB 31 RS 0 6 RA 11 RB 16 150 1 21 31 EA ← (RA|0) + (RB) if RESERVE = 1 then MS(EA, 4) ← (RS) RESERVE ← 0 (CR[CR0]) ← 20 || 1 || XER[SO] else (CR[CR0]) ← 20 || 0 || XER[SO] An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB.
stwcx. Preliminary Store Word Conditional Indexed PPC440x5 CPU Core User’s Manual The PowerPC Book-E architecture also specifies that it is implementation-dependent as to whether a Data Storage, Data TLB Error, Alignment, or Debug interrupt occurs when the reservation bit is off at the time of execution of an stwcx. instruction, and when the conditions are such that a non-stwcx. store-type storage access instruction would have resulted in such an interrupt. The PPC440x5 implements stwcx.
stwu Store Word with Update PPC440x5 CPU Core User’s Manual Preliminary stwu Store Word with Update stwu RS, D(RA) 37 0 RS 6 RA 11 D 16 31 EA ← (RA|0) + EXTS(D) MS(EA, 4) ← (RS) (RA) ← EA An effective address (EA) is formed by adding a displacement to a base address. The displacement is obtained by sign-extending the 16-bit D field to 32 bits. The base address is 0 when the RA field is 0, and is the contents of register RA otherwise. The contents of register RS are stored into the word at the EA.
stwux Store Word with Update Indexed PPC440x5 CPU Core User’s Manual Preliminary stwux Store Word with Update Indexed stwux RS, RA, RB 31 0 RS 6 RA 11 RB 16 183 21 31 EA ← (RA|0) + (RB) MS(EA, 4) ← (RS) (RA) ← EA An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB. The base address is 0 when the RA field is 0, and is the contents of register RA otherwise. The contents of register RS are stored into the word at the EA.
stwx Store Word Indexed PPC440x5 CPU Core User’s Manual Preliminary stwx Store Word Indexed stwx RS, RA, RB 31 0 RS 6 RA 11 RB 16 151 21 31 EA ← (RA|0) + (RB) MS(EA,4) ← (RS) An effective address (EA) is formed by adding an index to a base address. The index is the contents of register RB. The base address is 0 when the RA field is 0, and is the contents of register RA otherwise. The contents of register RS are stored into the word at the EA.
subf Subtract From PPC440x5 CPU Core User’s Manual Preliminary subf Subtract From subf subf. subfo subfo. RT, RA, RB RT, RA, RB RT, RA, RB RT, RA, RB 31 OE=0, Rc=0 OE=0, Rc=1 OE=1, Rc=0 OE=1, Rc=1 RT 0 RA 6 11 RB 16 OE 40 Rc 21 22 31 (RT) ← ¬(RA) + (RB) + 1 The sum of the ones complement of register RA, register RB, and 1 is stored into register RT. Registers Altered • RT • CR[CR0] if Rc contains 1 • XER[SO, OV] if OE contains 1 Table 9-29. Extended Mnemonics for subf, subf.
subfc Subtract From Carrying PPC440x5 CPU Core User’s Manual Preliminary subfc Subtract From Carrying subfc subfc. subfco subfco. RT, RA, RB RT, RA, RB RT, RA, RB RT, RA, RB 31 OE=0, Rc=0 OE=0, Rc=1 OE=1, Rc=0 OE=1, Rc=1 RT 0 RA 6 11 RB 16 OE 8 Rc 21 22 31 (RT) ← ¬(RA) + (RB) + 1 if ¬(RA) + (RB) + 1 >u 232 – 1 then XER[CA] ← 1 else XER[CA] ← 0 The sum of the ones complement of register RA, register RB, and 1 is stored into register RT.
subfe Subtract From Extended PPC440x5 CPU Core User’s Manual Preliminary subfe Subtract From Extended subfe subfe. subfeo subfeo. RT, RA, RB RT, RA, RB RT, RA, RB RT, RA, RB 31 0 OE=0, Rc=0 OE=0, Rc=1 OE=1, Rc=0 OE=1, Rc=1 RT 6 RA 11 RB 16 OE 136 Rc 21 22 31 (RT) ← ¬(RA) + (RB) + XER[CA] if ¬(RA) + (RB) + XER[CA] >u 232 – 1 then XER[CA] ← 1 else XER[CA] ← 0 The sum of the ones complement of register RA, register RB, and XER[CA] is placed into register RT.
subfic Subtract From Immediate Carrying PPC440x5 CPU Core User’s Manual Preliminary subfic Subtract From Immediate Carrying subfic RT, RA, IM 8 0 RT 6 RA 11 IM 16 31 (RT) ← ¬(RA) + EXTS(IM) + 1 if ¬(RA) + EXTS(IM) + 1 >u 232 – 1 then XER[CA] ← 1 else XER[CA] ← 0 The sum of the ones complement of RA, the IM field sign-extended to 32 bits, and 1 is placed into register RT. XER[CA] is set to a value determined by the unsigned magnitude of the result of the subtract operation.
subfme Subtract from Minus One Extended PPC440x5 CPU Core User’s Manual Preliminary subfme Subtract from Minus One Extended subfme subfme. subfmeo subfmeo. RT, RA RT, RA RT, RA RT, RA 31 0 OE=0, Rc=0 OE=0, Rc=1 OE=1, Rc=0 OE=1, Rc=1 RT 6 RA 11 OE 16 232 Rc 21 22 31 (RT) ← ¬(RA) – 1 + XER[CA] if ¬(RA) + 0xFFFF FFFF + XER[CA] >u 232 – 1 then XER[CA] ← 1 else XER[CA] ← 0 The sum of the ones complement of register RA, –1, and XER[CA] is placed into register RT.
subfze Subtract from Zero Extended PPC440x5 CPU Core User’s Manual Preliminary subfze Subtract from Zero Extended subfze subfze. subfzeo subfzeo. RT, RA RT, RA RT, RA RT, RA 31 0 OE=0, Rc=0 OE=0, Rc=1 OE=1, Rc=0 OE=1, Rc=1 RT 6 RA 11 OE 16 200 Rc 21 22 31 (RT) ← ¬(RA) + XER[CA] if ¬(RA) + XER[CA] >u 232 – 1 then XER[CA] ← 1 else XER[CA] ← 0 The sum of the ones complement of register RA and XER[CA] is stored into register RT.
tlbre TLB Read Entry PPC440x5 CPU Core User’s Manual Preliminary tlbre TLB Read Entry tlbre RT, RA, WS 31 0 RT 6 RA 11 WS 16 946 21 31 tlbentry ← TLB[(RA)26:31] if WS =0 (RT)0:27 ← tlbentry[EPN,V,TS,SIZE] if CCR0[CRPE] = 0 (RT)28:31 ← 40 else (RT)28:31 ← TPAR MMUCR[STID] ← tlbentry[TID] else if WS = 1 (RT)0:21 ← tlbentry[RPN] if CCR0[CRPE] = 0 (RT)22:23 ← 20 else (RT)22:23 ← PAR1 (RT)24:27 ← 40 (RT)28:31 ← tlbentry[ERPN] else if WS = 2 if CCR0[CRPE] = 0 (RT)0:1 ← 20 else (RT)0:1 ← PAR2 (RT)2:15 ←
tlbre TLB Read Entry PPC440x5 CPU Core User’s Manual Preliminary Registers Altered • RT • MMUCR[STID] (if WS = 0) Invalid Instruction Forms • Reserved fields • Invalid WS value Programming Notes Execution of this instruction is privileged. The PPC440x5 core does not automatically synchronize the context of the MMUCR[STID] field between a tlbre instruction which updates the field, and a tlbsx[.] instruction which uses it as a source operand.
tlbsx TLB Search Indexed PPC440x5 CPU Core User’s Manual Preliminary tlbsx TLB Search Indexed tlbsx tlbsx. RT, RA, RB RT, RA, RB 31 0 Rc=0 Rc=1 RT 6 RA 11 RB 16 914 21 Rc 31 EA ← (RA|0) + (RB) if Rc = 1 CR[CR0]0 ← 0 CR[CR0]1 ← 0 CR[CR0]3 ← XER[SO} if Valid TLB entry matching EA and MMUCR[STID,STS] is in the TLB then (RT) ← Index of matching TLB Entry if Rc = 1 CR[CR0]2 ← 1 else (RT) ← Undefined if Rc = 1 CR[CR0]2 ← 0 An effective address is formed by adding an index to a base address.
tlbsync TLB Synchronize PPC440x5 CPU Core User’s Manual Preliminary tlbsync TLB Synchronize tlbsync 31 0 566 6 21 31 The tlbsync instruction is provided by the PowerPC Book-E architecture to support synchronization of TLB operations between processors in a coherent multi-processor system. Since the PPC440x5 core does not support coherent multi-processing, this instruction performs no operation, and is provided only to facilitate code portability.
tlbwe TLB Write Entry PPC440x5 CPU Core User’s Manual Preliminary tlbwe TLB Write Entry tlbwe RS, RA, WS 31 0 RS 6 RA 11 WS 16 978 21 31 tlbentry ← TLB[(RA)26:31] if WS = 0 tlbentry[EPN,V,TS,SIZE] ← (RS)0:27 tlbentry[TID] ← MMUCR[STID] else if WS = 1 tlbentry[RPN] ← (RS)0:21 tlbentry[ERPN] ← (RS)28:31 else if WS = 2 tlbentry[U0,U1,U2,U3,W,I,M,G,E] ← (RS)16:24 tlbentry[UX,UW,UR,SX,SW,SR] ← (RS)26:31 else tlbentry ← undefined The contents of the specified portion of the selected TLB entry are repla
tw Trap Word PPC440x5 CPU Core User’s Manual Preliminary tw Trap Word tw TO, RA, RB 31 0 TO 6 RA 11 RB 16 4 21 31 ((RA) < (RB) ∧ TO0 = 1) ∨ ((RA) > (RB) ∧ TO1 = 1) ∨ ((RA) = (RB) ∧ TO2 = 1) ∨ u ((RA) < (RB) ∧ TO3 = 1) ∨ ((RA) >u (RB) ∧ TO4 = 1) ) SRR0 ← address of tw instruction SRR1 ← MSR ESR[PTR] ← 1 (other bits cleared) MSR[WE, EE, PR, FP, FE0, FE1, DWE, DS, IS]) ← 90 PC ← IVPR0:15 || IVOR616:27 || 40 else no operation if ( Register RA is compared with register RB.
tw Trap Word PPC440x5 CPU Core User’s Manual Preliminary The enabling of trap debug events may affect the interrupt type caused by the execution of tw instruction. Specifically, trap instructions may be enabled to cause Debug interrupts instead of Program interrupts. See Trap (TRAP) Debug Event on page 234 for more details. Table 9-31. Extended Mnemonics for tw Mnemonic Operands Function Other Registers Altered Trap unconditionally. Extended mnemonic for tw 31,0,0 trap Trap if (RA) equal to (RB).
tw Trap Word PPC440x5 CPU Core User’s Manual Preliminary Table 9-31. Extended Mnemonics for tw (continued) Mnemonic Operands Function Other Registers Altered Trap if (RA) not greater than (RB). twng RA, RB twnl RA, RB Extended mnemonic for tw 20,RA,RB Trap if (RA) not less than (RB). Page 442 of 589 Extended mnemonic for tw 12,RA,RB instrset.fm.
twi Trap Word Immediate PPC440x5 CPU Core User’s Manual Preliminary twi Trap Word Immediate twi TO, RA, IM 3 0 TO 6 RA 11 IM 16 31 ((RA) < EXTS(IM) ∧ TO0 = 1) ∨ ((RA) > EXTS(IM) ∧ TO1 = 1) ∨ ((RA) = EXTS(IM) ∧ TO2 = 1) ∨ u ((RA) < EXTS(IM) ∧ TO3 = 1) ∨ u ((RA) > EXTS(IM) ∧ TO4 = 1) ) SRR0 ← address of twi instruction SRR1 ← MSR ESR[PTR] ← 1 (other bits cleared) MSR[WE, EE, PR, FP, FE0, FE1, DWE, DS, IS]) ← 90 PC ← IVPR0:15 || IVOR616:27 || 40 else no operation if ( Register RA is compared with th
twi Trap Word Immediate PPC440x5 CPU Core User’s Manual Preliminary The enabling of trap debug events may affect the interrupt type caused by the execution of tw instruction. Specifically, trap instructions may be enabled to cause Debug interrupts instead of Program interrupts. See Trap (TRAP) Debug Event on page 234 for more details. Table 9-32. Extended Mnemonics for twi Mnemonic Operands Function Other Registers Altered Trap if (RA) equal to EXTS(IM).
twi Trap Word Immediate PPC440x5 CPU Core User’s Manual Preliminary Table 9-32. Extended Mnemonics for twi (continued) Mnemonic Operands Function Other Registers Altered Trap if (RA) not less than EXTS(IM). twnli instrset.fm.
wrtee Write External Enable PPC440x5 CPU Core User’s Manual Preliminary wrtee Write External Enable wrtee RS 31 RS 0 6 131 11 21 31 MSR[EE] ← (RS)16 MSR[EE] is set to the value specified by bit 16 of register RS. If instruction bit 31 contains 1, the contents of CR[CR0] are undefined. Registers Altered • MSR[EE] Invalid Instruction Forms: • Reserved fields Programming Notes Execution of this instruction is privileged.
wrteei Write External Enable Immediate PPC440x5 CPU Core User’s Manual Preliminary wrteei Write External Enable Immediate wrteei E 31 E 0 6 16 17 163 21 31 MSR[EE] ← E MSR[EE] is set to the value specified by the E field. If instruction bit 31 contains 1, the contents of CR[CR0] are undefined. Registers Altered • MSR[EE] Invalid Instruction Forms: • Reserved fields Programming Notes Execution of this instruction is privileged.
xor XOR PPC440x5 CPU Core User’s Manual Preliminary xor XOR xor xor. RA, RS, RB RA, RS, RB 31 0 Rc=0 Rc=1 RS 6 RA 11 RB 16 316 21 Rc 31 (RA) ← (RS) ⊕ (RB) The contents of register RS are XORed with the contents of register RB; the result is placed into register RA. Registers Altered • RA • CR[CR0] if Rc contains 1 Page 448 of 589 instrset.fm.
xori XOR Immediate PPC440x5 CPU Core User’s Manual Preliminary xori XOR Immediate xori RA, RS, IM 26 0 RS 6 RA 11 IM 16 31 (RA) ← (RS) ⊕ (160 || IM) The IM field is extended to 32 bits by concatenating 16 0-bits on the left. The contents of register RS are XORed with the extended IM field; the result is placed into register RA. Registers Altered • RA instrset.fm.
xoris XOR Immediate Shifted PPC440x5 CPU Core User’s Manual Preliminary xoris XOR Immediate Shifted xoris RA, RS, IM 27 0 RS 6 RA 11 IM 16 31 (RA) ← (RS) ⊕ (IM || 160) The IM field is extended to 32 bits by concatenating 16 0-bits on the right. The contents of register RS are XORed with the extended IM field; the result is placed into register RA. Registers Altered • RA Page 450 of 589 instrset.fm.
User’s Manual Preliminary PPC440x5 CPU Core 10. Register Summary This chapter provides an alphabetical listing of and bit definitions for the registers contained in the PPC440x5 core. The registers, of five types, are grouped into several functional categories according to the processor functions with which they are associated. More information about the registers and register categories is provided in Section 2.
User’s Manual PPC440x5 CPU Core Preliminary Table 10-1.
User’s Manual Preliminary PPC440x5 CPU Core Table 10-1. Register Categories Register Category Register(s) DEC DECAR Type SPR Page 211 Supervisor, write-only SPR 211 User read, Supervisor write SPR 209 TCR Supervisor SPR 215 TSR Supervisor SPR 216 Timer TBL, TBU regsummIntro.fm.
User’s Manual PPC440x5 CPU Core Preliminary Table 10-2 Special Purpose Registers Sorted by SPR Number on page 454, lists the Special Purpose Registers (SPRs) in order by SPR number (SPRN). The table provides mnemonics, names, SPRN, model (user or supervisor), and access. All SPR numbers not listed are reserved, and should be neither read nor written. Note that three registers, DBSR, MCSR, and TSR, are indicated as having the access type of read/clear.
User’s Manual Preliminary PPC440x5 CPU Core Table 10-2.
User’s Manual PPC440x5 CPU Core Preliminary Table 10-2.
User’s Manual Preliminary PPC440x5 CPU Core 10.2 Reserved Fields For all registers with fields marked as reserved, the reserved fields should be written as zero and read as undefined. That is, when writing to a reserved field, write a zero to that field. When reading from a reserved field, ignore that field.
User’s Manual PPC440x5 CPU Core Page 458 of 589 Preliminary regsummIntro.fm.
Preliminary PPC440x5 CPU Core User’s Manual 0.Register Summary 10.4 Alphabetical Register Listing The following pages list the registers available in the PPC440x5 core.
CCR0 Core Configuration Register 0 PPC440x5 CPU Core User’s Manual Preliminary CCR0 SPR 0x3B3 Supervisor R/W See Core Configuration Register 0 (CCR0) on page 108. PRE 0 1 DSTG 2 3 4 5 9 10 11 12 CRPE DTB GDCBT ICSLC 15 16 17 18 19 22 23 24 GICBT FLSTA DAPUIB 27 28 29 30 31 ICSLT Figure 10-1.
CCR0 (cont.) Core Configuration Register 0 PPC440x5 CPU Core User’s Manual Preliminary 23 FLSTA 24:27 28:29 30:31 Force Load/Store Alignment 0 No Alignment exception on integer storage access instructions, regardless of alignment 1 An alignment exception occurs on integer storage access instructions if data address is not on an operand boundary. See Load and Store Alignment on page 117. Reserved ICSLC ICSLT regsumm440core.fm.
CCR1 Core Configuration Register 1 PPC440x5 CPU Core User’s Manual Preliminary CCR1 SPR 0x378 Supervisor R/W See Core Configuration Register 1 (CCR1) on page 110. DCTPEI DCUPEI FCOM ICDPEI 0 7 8 FFF 9 10 11 12 13 14 15 16 ICTPEI DCDPEI DCMPEI 19 20 21 MMUPEI 23 24 25 31 TCS Figure 10-2.
CCR1 (cont.) Core Configuration Register 1 PPC440x5 CPU Core User’s Manual Preliminary 24 TCS 25:31 regsumm440core.fm. September 12, 2002 Timer Clock Select 0 CPU timer advances by one at each rising edge of the CPU input clock (CPMC440CLOCK). 1 CPU timer advances by one for each rising edge of the CPU timer clock (CPMC440TIMERCLOCK). When TCS = 1, CPU timer clock input can toggle at up to half of the CPU clock frequency.
CR Condition Register PPC440x5 CPU Core User’s Manual Preliminary CR User Read/Write See Condition Register (CR) on page 67. CR2 CR0 0 3 4 7 8 CR6 CR4 11 12 CR1 15 16 CR3 19 20 23 24 CR5 27 28 31 CR7 Figure 10-3.
CSRR0 Critical Save/Restore Register 0 PPC440x5 CPU Core User’s Manual Preliminary CSRR0 SPR 0x03A Supervisor R/W See Critical Save/Restore Register 0 (CSRR0) on page 168. 0 29 30 31 Figure 10-4. Critical Save/Restore Register 0 (CSRR0) 0:29 Return address for critical interrupts 30:31 Reserved regsumm440core.fm.
CSRR1 Critical Save/Restore Register 1 PPC440x5 CPU Core User’s Manual Preliminary CSRR1 SPR 0x03B Supervisor R/W See Critical Save/Restore Register 1 (CSRR1) on page 168. EE WE 0 FP FE0 IS DE 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 CE PR ME DWE FE1 31 DS Figure 10-5. Critical Save/Restore Register 1 (CSRR1) 0:31 Page 466 of 589 Copy of the MSR when a critical interrupt is taken regsumm440core.fm.
CTR Count Register PPC440x5 CPU Core User’s Manual Preliminary CTR SPR 0x009 User R/W See Count Register (CTR) on page 67. 0 31 Figure 10-6. Count Register (CTR) 0:31 regsumm440core.fm.
DAC1–DAC2 Data Address Compare Registers PPC440x5 CPU Core User’s Manual Preliminary DAC1–DAC2 SPR 0x13C–0x13D Supervisor R/W See Data Address Compare Registers (DAC1–DAC2) on page 246. 0 31 Figure 10-7. Data Address Compare Registers (DAC1–DAC2) 0:31 Page 468 of 589 Data Address Compare (DAC) byte address regsumm440core.fm.
DBCR0 Debug Control Register 0 PPC440x5 CPU Core User’s Manual Preliminary DBCR0 SPR 0x134 Supervisor R/W See Debug Control Register 0 (DBCR0) on page 239. EDM 0 RST 1 IDM 2 3 BRT TRAP IAC2 4 5 6 7 8 IAC4 DAC1W DAC2W FT 9 10 11 12 13 14 15 16 17 30 31 ICMP IRPT IAC1 IAC3 DAC1R DAC2R RET Figure 10-8. Debug Control Register 0 (DBCR0) 0 EDM External Debug Mode 0 Disable external debug mode. 1 Enable external debug mode. 1 IDM Internal Debug Mode 0 Disable internal debug mode.
DBCR0 (cont.) Debug Control Register 0 PPC440x5 CPU Core User’s Manual 12 DAC1R Data Address Compare (DAC) 1 Read Debug Event 0 Disable DAC 1 read debug event. 1 Enable DAC 1 read debug event. 13 DAC1W DAC 1 Write Debug Event 0 Disable DAC 1 write debug event. 1 Enable DAC 1 write debug event. 14 DAC2R DAC 2 Read Debug Event 0 Disable DAC 2 read debug event. 1 Enable DAC 2 read debug event. 15 DAC2W DAC 2 Write Debug Event 0 Disable DAC 2 write debug event. 1 Enable DAC 2 write debug event.
DBCR1 Debug Control Register 1 PPC440x5 CPU Core User’s Manual Preliminary DBCR1 SPR 0x135 Supervisor R/W See Debug Control Register 1 (DBCR1) on page 240. IAC1US 0 1 IAC2US 2 3 4 5 IAC1ER IAC12M 6 7 8 9 10 IAC2ER IAC3US IAC4US IAC34M 14 15 16 17 18 19 20 21 22 23 24 25 26 IAC12AT IAC3ER 30 31 IAC4ER IAC34AT Figure 10-9.
DBCR1 (cont.
DBCR2 Debug Control Register 2 PPC440x5 CPU Core User’s Manual Preliminary DBCR2 SPR 0x136 Supervisor R/W See Debug Control Register 2 (DBCR2) on page 243. 0 1 DAC12M DAC2US DAC1US 2 3 4 DAC1ER 5 6 7 8 DAC2ER DVC1BE DVC1M 9 10 11 12 13 14 15 16 DAC12A 19 20 23 24 DVC2M 27 28 31 DVC2BE Figure 10-10.
DBCR2 (cont.) Debug Control Register 2 PPC440x5 CPU Core User’s Manual Preliminary DVC 2 Mode 00 Reserved 14:15 DVC2M 01 AND all bytes enabled by DVC2BE 10 OR all bytes enabled by DVC2BE 11 AND-OR pairs of bytes enabled by DVC2BE Reserved 16:19 20:23 DVC1BE 24:27 28:31 (0 AND 1) OR (2 AND 3) DVC 1 Byte Enables 0:3 Reserved DVC2BE Page 474 of 589 DVC 2 Byte Enables 0:3 regsumm440core.fm.
DBDR Debug Data Register PPC440x5 CPU Core User’s Manual Preliminary DBDR SPR 0x3F3 Supervisor R/W See Debug Data Register (DBDR) on page 247. 0 31 Figure 10-11. Debug Data Register (DBDR) 0:31 regsumm440core.fm.
DBSR Debug Status Register PPC440x5 CPU Core User’s Manual Preliminary DBSR SPR 0x130 Supervisor Read/Clear See Debug Status Register (DBSR) on page 244. IDE 0 BRT TRAP IAC2 MRR 1 UDE 2 3 4 5 6 7 8 IAC4 DAC1W DAC2W 9 10 11 12 13 14 15 16 17 ICMP IRPT IAC1 IAC3 DAC1R DAC2R RET IAC34ATS 29 30 31 IAC12ATS Figure 10-12.
DBSR (cont.
DCDBTRH Data Cache Debug Tag Register High PPC440x5 CPU Core User’s Manual Preliminary DCDBTRH SPR 0x39D Supervisor Read-Only See dcread Operation on page 127. TERA TRA 0 23 24 25 27 28 31 V Figure 10-13. Data Cache Debug Tag Register High (DCDBTRH) 0:23 TRA Tag Real Address Bits 0:23 of the lower 32 bits of the 36-bit real address associated with the cache line read by dcread. 24 V Cache Line Valid 0 Cache line is not valid. 1 Cache line is valid.
DCDBTRL Data Cache Debug Tag Register Low PPC440x5 CPU Core User’s Manual Preliminary DCDBTRL SPR 0x39C Supervisor Read-Only See dcread Operation on page 127. UPAR 0 12 13 14 15 16 DPAR D 19 20 TPAR 23 24 MPAR U1 U3 27 28 29 30 31 U0 U2 Figure 10-14. Data Cache Debug Tag Register Low (DCDBTRL) 0:12 Reserved 13 UPAR U bit parity The parity for the U0-U3 bits in the cache line read by dcread if CCR0[CRPE] = 1, otherwise 0.
DEAR Data Exception Address Register PPC440x5 CPU Core User’s Manual Preliminary DEAR SPR 0x03D Supervisor R/W See Data Exception Address Register (DEAR) on page 170. 0 31 Figure 10-15. Data Exception Address Register (DEAR) 0:31 Page 480 of 589 Address of data exception for Data Storage, Alignment, and Data TLB Error interrupts regsumm440core.fm.
DEC Decrementer PPC440x5 CPU Core User’s Manual Preliminary DEC SPR 0x016 Supervisor R/W See Decrementer (DEC) on page 211. 0 31 Figure 10-16. Decrementer (DEC) 0:31 regsumm440core.fm.
DECAR Decrementer Auto-Reload PPC440x5 CPU Core User’s Manual Preliminary DECAR SPR 0x036 Supervisor Write-Only See Decrementer (DEC) on page 211. 0 31 Figure 10-17. Decrementer Auto-Reload (DECAR) 0:31 Page 482 of 589 Decrementer auto-reload value Copied to DEC at next time base clock when DEC = 1 and auto-reload is enabled (TCR[ARE] = 1). regsumm440core.fm.
DNV0–DNV3 Data Cache Normal Victim 0–3 PPC440x5 CPU Core User’s Manual Preliminary DNV0–DNV3 SPR 0x390–0x393 Supervisor R/W See Cache Line Replacement Policy on page 96. VNDXA 0 VNDXC 7 8 15 16 23 24 VNDXB 31 VNDXD Figure 10-18.
DTV0–DTV3 Data Cache Transient Victim 0–3 PPC440x5 CPU Core User’s Manual Preliminary DTV0–DTV3 SPR 0x394–0x397 Supervisor R/W See Cache Line Replacement Policy on page 96. VNDXA 0 VNDXC 7 8 15 16 23 24 VNDXB 31 VNDXD Figure 10-19.
DVC1–DVC2 Data Value Compare Registers PPC440x5 CPU Core User’s Manual Preliminary DVC1–DVC2 SPR 0x13E–0x13F Supervisor R/W See Data Value Compare Registers (DVC1–DVC2) on page 246. 0 31 Figure 10-20. Data Value Compare Registers (DVC1–DVC2) 0:31 regsumm440core.fm.
DVLIM Data Cache Victim Limit PPC440x5 CPU Core User’s Manual Preliminary DVLIM SPR 0x398 Supervisor R/W See Cache Locking and Transient Mechanism on page 99. TFLOOR 0 1 2 NFLOOR 9 10 12 13 20 21 23 24 31 TCEILING Figure 10-21. Data Cache Victim Limit (DVLIM) 0:1 2:9 Reserved TFLOOR 10:12 13:20 Transient Floor The number of bits in the TFLOOR field varies, depending on the implemented cache size. See Table 4-3, on page -98 for more information.
ESR Exception Syndrome Register PPC440x5 CPU Core User’s Manual Preliminary ESR SPR 0x03E Supervisor R/W See Exception Syndrome Register (ESR) on page 172. MCI 0 PIL 1 3 4 PTR 5 6 PPR ST 7 8 FP AP BO PCRE 9 10 11 12 13 14 15 16 DLK PUO PIE PCRF 26 27 28 29 31 PCMP Figure 10-22. Exception Syndrome Register (ESR) 0 MCI 1:3 Machine Check—Instruction Fetch Exception 0 Instruction Machine Check exception did not occur. 1 Instruction Machine Check exception occurred.
ESR (cont.) Exception Syndrome Register PPC440x5 CPU Core User’s Manual 14 15 BO Byte Ordering Exception 0 Byte Ordering exception did not occur. 1 Byte Ordering exception occurred. PIE Program Interrupt—Imprecise Exception 0 Exception occurred precisely; SRR0 contains the address of the instruction that caused the exception. 1 Exception occurred imprecisely; SRR0 contains the address of an instruction after the one which caused the exception.
GPR General Purpose Registers PPC440x5 CPU Core User’s Manual Preliminary GPR0–GPR31 User R/W See General Purpose Registers (GPRs) on page 71. 0 31 Figure 10-23. General Purpose Registers (R0-R31) 0:31 regsumm440core.fm.
IAC1–IAC4 Instruction Address Compare Registers PPC440x5 CPU Core User’s Manual Preliminary IAC1–IAC4 SPR 0x138–0x13B Supervisor R/W See Instruction Address Compare Registers (IAC1–IAC4) on page 245. 0 29 30 31 Figure 10-24. Instruction Address Compare Registers (IAC1–IAC4) 0:29 Instruction Address Compare (IAC) word address 30:31 Reserved Page 490 of 589 regsumm440core.fm.
ICDBDR Instruction Cache Debug Data Register PPC440x5 CPU Core User’s Manual Preliminary ICDBDR SPR 0x3D3 Supervisor Read-Only See icread Operation on page 112. 0 31 Figure 10-25. Instruction Cache Debug Data Register (ICDBDR) 0:31 regsumm440core.fm.
ICDBTRH Instruction Cache Debug Tag Register High PPC440x5 CPU Core User’s Manual Preliminary ICDBTRH SPR 0x39F Supervisor Read-Only See icread Operation on page 112. TPAR TEA 0 23 24 25 26 27 28 V 31 DAPAR Figure 10-26. Instruction Cache Debug Tag Register High (ICDBTRH) 0:23 Tag Effective Address Bits 0:23 of the 32-bit effective address associated with the cache line read by icread. 24 V Cache Line Valid 0 Cache line is not valid. 1 Cache line is valid.
ICDBTRL Instruction Cache Debug Tag Register Low PPC440x5 CPU Core User’s Manual Preliminary ICDBTRL SPR 0x39E Supervisor Read-Only See icread Operation on page 112. TID TS 0 21 22 23 24 31 TD Figure 10-27. Instruction Cache Debug Tag Register Low (ICDBTRL) 0:21 Reserved 22 TS Translation Space The address space portion of the virtual address associated with the cache line read by icread.
INV0–INV3 Instruction Cache Normal Victim 0–3 PPC440x5 CPU Core User’s Manual Preliminary INV0–INV3 SPR 0x370–0x373 Supervisor R/W See Cache Line Replacement Policy on page 96. VNDXA 0 VNDXC 7 8 15 16 23 24 VNDXB 31 VNDXD Figure 10-28.
ITV0–ITV3 Instruction Cache Transient Victim 0–3 PPC440x5 CPU Core User’s Manual Preliminary ITV0–ITV3 SPR 0x374–0x377 Supervisor R/W See Cache Line Replacement Policy on page 96. VNDXA 0 VNDXC 7 8 15 16 23 24 VNDXB 31 VNDXD Figure 10-29.
IVLIM Instruction Cache Victim Limit PPC440x5 CPU Core User’s Manual Preliminary IVLIM SPR 0x399 Supervisor R/W See Cache Locking and Transient Mechanism on page 99. TFLOOR 0 1 2 NFLOOR 9 10 12 13 20 21 23 24 31 TCEILING Figure 10-30. Instruction Cache Victim Limit (IVLIM) 0:1 2:9 Reserved TFLOOR 10:12 13:20 Transient Floor The number of bits in the TFLOOR field varies, depending on the implemented cache size. See Table 4-3, on page -98 for more information.
IVOR0–IVOR15 Interrupt Vector Offset Registers PPC440x5 CPU Core User’s Manual Preliminary IVOR0–IVOR15 SPR 0x190–0x19F Supervisor R/W See Interrupt Vector Offset Registers (IVOR0–IVOR15) on page 170. IVO 0 15 16 27 28 31 Figure 10-31. Interrupt Vector Offset Registers (IVOR0–IVOR15) 0:15 16:27 Reserved IVO 28:31 Interrupt Vector Offset Reserved Table 10-3.
IVPR Interrupt Vector Prefix Register PPC440x5 CPU Core User’s Manual Preliminary IVPR SPR 0x03F Supervisor R/W See Interrupt Vector Prefix Register (IVPR) on page 171. IVP 0 15 16 31 Figure 10-32. Interrupt Vector Prefix Register (IVPR) 0:15 IVP 16:31 Page 498 of 589 Interrupt Vector Prefix Reserved regsumm440core.fm.
LR Link Register PPC440x5 CPU Core User’s Manual Preliminary LR SPR 0x008 User R/W See Link Register (LR) on page 66. 0 31 Figure 10-33. Link Register (LR) 0:31 regsumm440core.fm.
MCSR Machine Check Status Register PPC440x5 CPU Core User’s Manual Preliminary MCSR SPR 0x23C Supervisor Read/Clear See Machine Check Status Register (MCSR) on page 174. MCS DRB TLBP DCSP IMPE 0 1 IB 2 3 4 DWB 5 ICP 6 7 8 9 31 DCFP Figure 10-34. Machine Check Status Register (MCSR) Set when a machine check exception occurs that is handled in the asynchronous fashion. One of MCSR bits 1:7 will be set simultaneously to indicate the exception type.
MCSRR0 Machine Check Save/Restore Register 0 PPC440x5 CPU Core User’s Manual Preliminary MCSRR0 SPR 0x23A Supervisor R/W See Machine Check Save/Restore Register 0 (MCSRR0) on page 169. 0 29 30 31 Figure 10-35. Machine Check Save/Restore Register 0 (MCSRR0) 0:29 Return address for machine check interrupts 30:31 Reserved regsumm440core.fm.
MCSRR1 Machine Check Save/Restore Register 1 PPC440x5 CPU Core User’s Manual Preliminary MCSRR1 SPR 0x23B Supervisor R/W See Machine Check Save/Restore Register 1 (MCSRR1) on page 169. EE WE 0 FP FE0 IS DE 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 CE PR ME DWE FE1 31 DS Figure 0-2. Machine Check Save/Restore Register 1 (MCSRR1) 0:31 Page 502 of 589 Copy of the MSR at the time of a machine check interrupt. regsumm440core.fm.
MMUCR Memory Management Control Register PPC440x5 CPU Core User’s Manual Preliminary MMUCR SPR 0x3B2 Supervisor R/W See Memory Management Unit Control Register (MMUCR) on page 148. SWOA U2SWOAE 0 6 7 8 STID IULXE 9 10 11 12 13 14 15 16 U1TE DULXE 23 24 31 STS Figure 10-36. Memory Management Unit Control Register (MMUCR) 0:6 Reserved 7 Store Without Allocate 0 Cacheable store misses allocate a line in the data cache. 1 Cacheable store misses do not allocate a line in the data cache.
MSR Machine State Register PPC440x5 CPU Core User’s Manual Preliminary MSR Supervisor R/W See Machine State Register (MSR) on page 165. EE WE 0 FP FE0 IS DE 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 CE PR ME DWE FE1 31 DS Figure 10-37. Machine State Register (MSR) 0:12 13 14 Reserved WE Wait State Enable 0 The processor is not in the wait state. 1 The processor is in the wait state. CE Critical Interrupt Enable 0 Critical Input and Watchdog Timer interrupts are disabled.
MSR (cont.) Machine State Register PPC440x5 CPU Core User’s Manual Preliminary 23 FE1 Floating-point exception mode 1 0 If MSR[FE0] = 0, ignore exceptions mode; if MSR[FE0] = 1, imprecise recoverable mode 1 If MSR[FE0] = 0, imprecise non-recoverable mode; if MSR[FE0] = 1, precise mode 24:25 Reserved 26 IS Instruction Address Space 0 All instruction storage accesses are directed to address space 0 (TS = 0 in the relevant TLB entry).
PID Process ID PPC440x5 CPU Core User’s Manual Preliminary PID SPR 0x030 Supervisor R/W See Process ID (PID) on page 151. PID 0 23 24 31 Figure 10-38. Process ID (PID) 0:23 24:31 Reserved PID Page 506 of 589 Process ID regsumm440core.fm.
PIR Processor Identification Register PPC440x5 CPU Core User’s Manual Preliminary PIR SPR 0x11E Supervisor Read-Only See Processor Identification Register (PIR) on page 76. PIN 0 27 28 31 Figure 10-39. Processor Identification Register (PIR) 0:27 28:31 Reserved PIN regsumm440core.fm.
PVR Processor Version Register PPC440x5 CPU Core User’s Manual Preliminary PVR SPR 0x11F Supervisor Read-Only See Processor Version Register (PVR) on page 75. OWN 0 11 12 31 PVN Figure 10-40. Processor Version Register (PVR) 0:11 OWN Owner Identifier Identifies the owner of a core. 12:31 PVN Processor Version Number Implementation-specific value identifying the specific version and use of a processor core within a chip. Page 508 of 589 regsumm440core.fm.
RSTCFG Reset Configuration PPC440x5 CPU Core User’s Manual Preliminary RSTCFG SPR 39B Supervisor Read-Only See Reset Configuration (RSTCFG) on page 79. U0 0 U2 E 15 16 17 18 19 20 U1 23 24 25 U3 27 28 31 ERPN Figure 10-41. Reset Configuration 0:15 Reserved 16 U0 U0 Storage Attribute 0 U0 storage attribute is disabled 1 U0 storage attribute is enabled See Table 5-1 on page 135.
SPRG0–SPRG7 Special Purpose Register General PPC440x5 CPU Core User’s Manual Preliminary SPRG0–SPRG7 SPR 0x104–0x107 (User/Supervisor Read-Only); SPR 0x110–0x113 (Supervisor R/W); SPR 0x114–0x117 (Supervisor Write-Only) See Special Purpose Registers General (USPRG0, SPRG0–SPRG7) on page 75. 0 31 Figure 10-42. Special Purpose Registers General (SPRG0–SPRG7) 0:31 Page 510 of 589 General data Software value; no hardware usage. regsumm440core.fm.
SRR0 Save/Restore Register 0 PPC440x5 CPU Core User’s Manual Preliminary SRR0 SPR 0x01A Supervisor R/W See Save/Restore Register 0 (SRR0) on page 167. 0 29 30 31 Figure 10-43. Save/Restore Register 0 (SRR0) 0:29 Return address for non-critical interrupts 30:31 Reserved regsumm440core.fm.
SRR1 Save/Restore Register 1 PPC440x5 CPU Core User’s Manual Preliminary SRR1 SPR 0x01B Supervisor R/W See Save/Restore Register 1 (SRR1) on page 167. EE WE 0 FP FE0 IS DE 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 CE PR ME DWE FE1 31 DS Figure 10-44. Save/Restore Register 1 (SRR1) 0:31 Page 512 of 589 Copy of the MSR at the time of a non-critical interrupt. regsumm440core.fm.
TBL Time Base Lower PPC440x5 CPU Core User’s Manual Preliminary TBL SPR 0x10C (User/Supervisor Read-Only); SPR 0x11C (Supervisor Write-Only) See Time Base on page 209. 0 31 Figure 10-45. Time Base Lower (TBL) 0:31 regsumm440core.fm. September 12, 2002 Time Base Lower Low-order 32 bits of time base.
TBU Time Base Upper PPC440x5 CPU Core User’s Manual Preliminary TBU SPR 0x10D (User/Supervisor Read-Only); SPR 0x11D (Supervisor Write-Only) See Time Base on page 209. 0 31 Figure 10-46. Time Base Upper (TBU) 0:31 Page 514 of 589 Time Base Upper High-order 32 bits of time base. regsumm440core.fm.
TCR Timer Control Register PPC440x5 CPU Core User’s Manual Preliminary TCR SPR 0x154 Supervisor R/W See Timer Control Register (TCR) on page 215. WP 0 1 WIE 2 3 4 WRC FP FIE 5 DIE 6 7 8 9 10 31 ARE Figure 10-47. Timer Control Register (TCR) Watchdog Timer Period 00 221 time base clocks 0:1 WP 01 225 time base clocks 10 229 time base clocks 11 233 time base clocks Watchdog Timer Reset Control 00 No Watchdog Timer reset will occur.
TSR Timer Status Register PPC440x5 CPU Core User’s Manual Preliminary TSR SPR 0x150 Supervisor Read/Clear See Timer Status Register (TSR) on page 216. ENW 0 WRS 1 WIS 2 FIS 3 4 5 6 31 DIS Figure 10-48. Timer Status Register (TSR) 0 ENW Enable Next Watchdog Timer Exception 0 Action on next Watchdog Timer exception is to set TSR[ENW] = 1. 1 Action on next Watchdog Timer exception is governed by TSR[WIS]. 1 WIS Watchdog Timer Interrupt Status 0 Watchdog Timer exception has not occurred.
USPRG0 User Special Purpose Register General 0 PPC440x5 CPU Core User’s Manual Preliminary USPRG0 SPR 0x100 (User R/W) See Special Purpose Registers General (USPRG0, SPRG0–SPRG7) on page 75. 0 31 Figure 10-49. User Special Purpose Register General (USPRG0) 0:31 regsumm440core.fm. September 12, 2002 General data Software value; no hardware usage.
XER Integer Exception Register PPC440x5 CPU Core User’s Manual Preliminary XER SPR 0x001 User R/W See Integer Exception Register (XER) on page 72. TBC CA SO 0 1 2 3 24 25 31 OV Figure 10-50. Integer Exception Register (XER) 0 1 2 SO Summary Overflow 0 No overflow has occurred. 1 Overflow has occurred. Can be set by mtspr or by integer or auxiliary processor instructions with the [o] option; can be reset by mtspr or by mcrxr. OV Overflow 0 No overflow has occurred.
User’s Manual Preliminary PPC440x5 CPU Core Appendix A. Instruction Summary This appendix describes the various instruction formats, and lists all of the PPC440x5 instructions summarized alphabetically and by opcode. Appendix A.1 on page 519 illustrates the PPC440x5 instruction forms (allowed arrangements of fields within instructions). Appendix A.2 on page 524 lists all PPC440x5 mnemonics, including extended mnemonics. A short functional description is included for each mnemonic. Appendix A.
User’s Manual PPC440x5 CPU Core Preliminary A.1.1 Instruction Fields PPC440x5 instructions contain various combinations of the following fields, as indicated in the instruction format diagrams that follow the field definitions. Numbers, enclosed in parentheses, that follow the field names indicate bit positions; bit fields are indicated by starting and stopping bit positions separated by colons. AA (30) Absolute address bit.
User’s Manual Preliminary PPC440x5 CPU Core Used in rotate-and-mask instructions to specify the ending bit of a mask. NB (16:20) Specifies the number of bytes to move in an immediate string load or store. OPCD (0:5) Primary opcode. Primary opcodes, in decimal, appear in the instruction format diagrams presented with individual instructions. The OPCD field name does not appear in instruction descriptions.
User’s Manual PPC440x5 CPU Core Preliminary A.1.2.1 I-Form OPCD 0 LI 6 31 Figure A-1. I Instruction Format A.1.2.2 B-Form OPCD 0 BO BI 6 11 BD 16 AA LK 30 31 Figure A-2. B Instruction Format A.1.2.3 SC-Form OPCD 0 /// /// 6 11 /// 1 16 / 30 31 Figure A-3. SC Instruction Format A.1.2.4 D-Form OPCD RT RA D OPCD RS RA SI OPCD RS RA D OPCD RS RA UI OPCD BF / L RA SI OPCD BF / L RA UI RA SI OPCD 0 TO 6 11 16 31 Figure A-4.
User’s Manual Preliminary PPC440x5 CPU Core A.1.2.
User’s Manual PPC440x5 CPU Core Preliminary A.1.2.6 XL-Form OPCD BT BA BB XO / OPCD BC BI /// XO LK /// XO / /// XO / OPCD BF OPCD 0 // BFA /// 6 // /// 11 16 21 31 Figure A-6. XL Instruction Format A.1.2.7 XFX-Form OPCD RT SPRF XO / OPCD RT DCRF XO / OPCD RT XO / OPCD RS SPRF XO / OPCD RS DCRF XO / 0 6 / FXM 11 / 16 21 31 Figure A-7. XFX Instruction Format A.1.2.
User’s Manual Preliminary PPC440x5 CPU Core Table A-1 summarizes the PPC440x5 instruction set, including required extended mnemonics. All mnemonics are listed alphabetically, without regard to whether the mnemonic is realized in hardware or software. When an instruction supports multiple hardware mnemonics (for example, b, ba, bl, bla are all forms of b), the instruction is alphabetized under the root form.
User’s Manual PPC440x5 CPU Core Preliminary Table A-1. PPC440x5 Instruction Syntax Summary (continued) Mnemonic addis Operands Function Other Registers Changed RT, RA, IM Add (IM || Place result in RT. Add XER[CA], (RA), (-1). Place result in RT. Place carry-out in XER[CA]. CR[CR0] RT, RA Add XER[CA] to (RA). Place result in RT. Place carry-out in XER[CA]. CR[CR0] 160) to (RA|0). Page 261 addme addme. addmeo addmeo. XER[SO, OV] 262 CR[CR0] XER[SO, OV] addze addze. addzeo RT, RA addzeo.
User’s Manual Preliminary PPC440x5 CPU Core Table A-1. PPC440x5 Instruction Syntax Summary (continued) Mnemonic Operands bclr bclrl BO, BI Function Branch conditional to address in LR. Using (LR) at entry to instruction, NIA ← LR0:29 || 20 Other Registers Changed Page CTR if BO2 = 0 CTR if BO2 = 0 (LR) ← CIA + 4 278 Branch unconditionally to address in CTR. bctr Extended mnemonic for bcctr 20,0 bctrl Extended mnemonic for bcctrl 20,0 (LR) ← CIA + 4 Decrement CTR.
User’s Manual PPC440x5 CPU Core Preliminary Table A-1. PPC440x5 Instruction Syntax Summary (continued) Mnemonic Operands Other Registers Changed Extended mnemonic for bc 8,cr_bit,target cr_bit, target Extended mnemonic for bca 8,cr_bit,target 269 bdnztl Extended mnemonic for bcl 8,cr_bit,target (LR) ← CIA + 4 bdnztla Extended mnemonic for bcla 8,cr_bit,target (LR) ← CIA + 4 Decrement CTR. Branch if CTR ≠ 0 AND CRcr_bit = 1 to address in LR.
User’s Manual Preliminary PPC440x5 CPU Core Table A-1. PPC440x5 Instruction Syntax Summary (continued) Mnemonic Operands Other Registers Changed Extended mnemonic for bc 10,cr_bit,target cr_bit, target Extended mnemonic for bca 10,cr_bit,target 269 bdztl Extended mnemonic for bcl 10,cr_bit,target (LR) ← CIA + 4 bdztla Extended mnemonic for bcla 10,cr_bit,target (LR) ← CIA + 4 Decrement CTR. Branch if CTR = 0 AND CRcr_bit = 1to address in LR.
User’s Manual PPC440x5 CPU Core Preliminary Table A-1. PPC440x5 Instruction Syntax Summary (continued) Mnemonic Operands Function Other Registers Changed Page Branch if CRcr_bit = 0 to address in CTR. bfctr cr_bit Extended mnemonic for bcctr 4,cr_bit Extended mnemonic for bcctrl 4,cr_bit bfctrl 275 (LR) ← CIA + 4 Branch if CRcr_bit = 0 to address in LR. bflr cr_bit Extended mnemonic for bclrl 4,cr_bit bflrl 278 (LR) ← CIA + 4 Branch if greater than or equal.
User’s Manual Preliminary PPC440x5 CPU Core Table A-1. PPC440x5 Instruction Syntax Summary (continued) Mnemonic Operands Other Registers Changed Page Branch if greater than to address in LR. Use CR[CR0] if cr_field is omitted. bgtlr [cr_field] Extended mnemonic for bclr 12,4∗cr_field+1 Extended mnemonic for bclrl 12,4∗cr_field+1 bgtlrl 278 (LR) ← CIA + 4 Branch if less than or equal. Use CR[CR0] if cr_field is omitted.
User’s Manual PPC440x5 CPU Core Preliminary Table A-1. PPC440x5 Instruction Syntax Summary (continued) Mnemonic Operands Other Registers Changed [cr_field] Extended mnemonic for bcctr 12,4∗cr_field+0 Extended mnemonic for bcctrl 12,4∗cr_field+0 bltctrl 275 (LR) ← CIA + 4 Branch if less than to address in LR. Use CR[CR0] if cr_field is omitted. bltlr [cr_field] Extended mnemonic for bclr 12,4∗cr_field+0 Extended mnemonic for bclrl 12,4∗cr_field+0 bltlrl 278 (LR) ← CIA + 4 Branch if not equal.
User’s Manual Preliminary PPC440x5 CPU Core Table A-1. PPC440x5 Instruction Syntax Summary (continued) Mnemonic Operands Other Registers Changed [cr_field] Extended mnemonic for bcctr 4,4∗cr_field+1 Extended mnemonic for bcctrl 4,4∗cr_field+1 bngctrl 275 (LR) ← CIA + 4 Branch if not greater than to address in LR. Use CR[CR0] if cr_field is omitted.
User’s Manual PPC440x5 CPU Core Preliminary Table A-1. PPC440x5 Instruction Syntax Summary (continued) Mnemonic Operands [cr_field] Extended mnemonic for bcctr 4,4∗cr_field+3 Extended mnemonic for bcctrl 4,4∗cr_field+3 bnsctrl [cr_field] 275 (LR) ← CIA + 4 Extended mnemonic for bclr 4,4∗cr_field+3 Extended mnemonic for bclrl 4,4∗cr_field+3 bnslrl 278 (LR) ← CIA + 4 Branch if not unordered. Use CR[CR0] if cr_field is omitted.
User’s Manual Preliminary PPC440x5 CPU Core Table A-1. PPC440x5 Instruction Syntax Summary (continued) Mnemonic Operands Function Other Registers Changed Page Branch if summary overflow to address in CTR. UseCR[CR0] if cr_field is omitted. bsoctr [cr_field] Extended mnemonic for bcctr 12,4∗cr_field+3 Extended mnemonic for bcctrl 12,4∗cr_field+3 bsoctrl bsolr [cr_field] (LR) ← CIA + 4 Branch if summary overflow to address in LR. UseCR[CR0] if cr_field is omitted.
User’s Manual PPC440x5 CPU Core Preliminary Table A-1. PPC440x5 Instruction Syntax Summary (continued) Mnemonic Operands Function Other Registers Changed Page Branch if unordered, to address in LR. Use CR[CR0] if cr_field is omitted. bunlr [cr_field] Extended mnemonic for bclr 12,4∗cr_field+3 Extended mnemonic for bclrl 12,4∗cr_field+3 bunlrl 278 (LR) ← CIA + 4 Clear left immediate.
User’s Manual Preliminary PPC440x5 CPU Core Table A-1. PPC440x5 Instruction Syntax Summary (continued) Mnemonic cmpwi cntlzw Operands [BF,] RA, IM Function Other Registers Changed Compare Word Immediate. UseCR[CR0] if BF is omitted. Page 283 Extended mnemonic for cmpi BF,0,RA,IM RA, RS Count leading zeros in RS. Place result in RA. crand BT, BA, BB AND bit (CRBA) with (CRBB). Place result in CRBT.
User’s Manual PPC440x5 CPU Core Preliminary Table A-1. PPC440x5 Instruction Syntax Summary (continued) Mnemonic dcread Operands Function RT, RA, RB Read tag and data information from the data cache line selected using effective address bits 17:26. The effective address is calculated by (RA|0) + (RB). Place the data word selected by effective address bits 27:29 in GPR RT; place the tag information in DCDBTRH and DCDBTRL. RT, RA, RB Divide (RA) by (RB), signed. Place result in RT.
User’s Manual Preliminary PPC440x5 CPU Core Table A-1. PPC440x5 Instruction Syntax Summary (continued) Mnemonic extsb Operands Function Other Registers Changed Page RA, RS Extend the sign of byte (RS)24:31. Place the result in RA. CR[CR0] RA, RS Extend the sign of halfword (RS)16:31. Place the result in RA. CR[CR0] icbi RA, RB Invalidate the instruction cache block which contains the effective address (RA|0) + (RB).
User’s Manual PPC440x5 CPU Core Preliminary Table A-1. PPC440x5 Instruction Syntax Summary (continued) Mnemonic Operands Function Other Registers Changed Page RT, D(RA) Load halfword from EA = (RA|0) + EXTS(D) and sign extend, (RT) ← EXTS(MS(EA,2)). Update the base address, (RA) ← EA. 326 lhaux RT, RA, RB Load halfword from EA = (RA|0) + (RB) and sign extend, (RT) ← EXTS(MS(EA,2)). Update the base address, (RA) ← EA.
User’s Manual Preliminary PPC440x5 CPU Core Table A-1. PPC440x5 Instruction Syntax Summary (continued) Mnemonic Operands Function Other Registers Changed Page lswx RT, RA, RB Load consecutive bytes from EA=(RA|0)+(RB). Number of bytes n=XER[TBC]. Stack bytes into words in CEIL(n/4) consecutive registers starting with RT, to RFINAL ← ((RT + CEIL(n/4) – 1) % 32). GPR(0) is consecutive to GPR(31). RA is not altered unless RA = RFINAL. RB is not altered unless RB = RFINAL.
User’s Manual PPC440x5 CPU Core Preliminary Table A-1. PPC440x5 Instruction Syntax Summary (continued) Mnemonic Operands Function Other Registers Changed Page machhw machhw. machhwo RT, RA, RB machhwo. prod0:31 ← (RA)16:31 × (RB)0:15 temp0:32 ← prod0:31 + (RT) (RT) ← temp1:32 CR[CR0] prod0:31 ← (RA)16:31 × (RB)0:15 temp0:32 ← prod0:31 + (RT) (RT) ← temp1:32 CR[CR0] XER[SO, OV] CR[CR0] XER[SO, OV] machhwu 352 machhwu. machhwuo RT, RA, RB machhwuo. machhws machhws.
User’s Manual Preliminary PPC440x5 CPU Core Table A-1. PPC440x5 Instruction Syntax Summary (continued) Mnemonic Operands Function Other Registers Changed Page mfcr RT Move from CR to RT, (RT) ← (CR). 360 mfdcr RT, DCRN Move from DCR to RT, (RT) ← (DCR(DCRN)). 361 mfmsr RT Move from MSR to RT, (RT) ← (MSR). 362 instalfa.fm.
User’s Manual PPC440x5 CPU Core Preliminary Table A-1. PPC440x5 Instruction Syntax Summary (continued) Mnemonic Operands Function Other Registers Changed Page mfccr0 mfccr1 mfctr mfdac1 mfdac2 mfdbcr0 mfdbcr1 mfdbsr mfdccr mfdcwr mfdvc1 mfdvc2 mfesr mfiac1 mfiac2 mfiac3 mfiac4 mficcr mficdbdr mfivpr mflr mfmcsr mfmcsrr0 mfmcsrr1 Move from special purpose register (SPR) SPRN.
User’s Manual Preliminary PPC440x5 CPU Core Table A-1. PPC440x5 Instruction Syntax Summary (continued) Mnemonic Operands Function Other Registers Changed Page Move register. (RT) ← (RS) mr RT, RS Extended mnemonic for or RT,RS,RS Extended mnemonic for or. RT,RS,RS mr. Synchronization. All instructions that precede msync complete before any instructions that follow msync begin. When msync completes, all storage accesses initiated prior to msync will have completed.
User’s Manual PPC440x5 CPU Core Preliminary Table A-1. PPC440x5 Instruction Syntax Summary (continued) Mnemonic Operands Function Other Registers Changed Page mtccr0 mtccr1 mtctr mtdac1 mtdac2 mtdbcr0 mtdbcr1 mtdbsr mtdccr mtdcwr mtdvc1 mtdvc2 mtesr mtiac1 mtiac2 mtiac3 mtiac4 mticcr mticdbdr mtivpr mtlr mtmcsr mtmcsrr0 mtmcsrr1 mtpid mtpit mtpvr mtsgr mtsprg0 mtsprg1 mtsprg2 mtsprg3 mtsprg4 mtsprg5 mtsprg6 mtsprg7 mtsrr0 mtsrr1 mtsrr2 mtsrr3 Move to SPR SPRN.
User’s Manual Preliminary PPC440x5 CPU Core Table A-1. PPC440x5 Instruction Syntax Summary (continued) Mnemonic mtspr mulchw mulchw. mulchwu mulchwu. mulhhw mulhhw. mulhhwu mulhhwu. Operands Move to SPR from RS, (SPR(SPRN)) ← (RS).
User’s Manual PPC440x5 CPU Core Preliminary Table A-1. PPC440x5 Instruction Syntax Summary (continued) Mnemonic Operands nmacchws nmacchws. nmacchwso RT, RA, RB nmacchwso. Function prod0:31 ← (RA)16:31 × (RB)0:15 temp0:32 ← –prod0:31 + (RT) if ((prod0 = RT0) ∧ (RT0 ≠ temp1)) then (RT) ← (RT0 ∨ 31(¬RT0)) else (RT) ← temp1:32 Other Registers Changed Page CR[CR0] XER[SO, OV] 386 CR[CR0] XER[SO, OV] nmachhw nmachhw. nmachhwo RT, RA, RB nmachhwo. nmachhws nmachhws.
User’s Manual Preliminary PPC440x5 CPU Core Table A-1. PPC440x5 Instruction Syntax Summary (continued) Mnemonic Operands Function Other Registers Changed Page rfi Return from interrupt. (PC) ← (SRR0). (MSR) ← (SRR1). 397 rfmci Return from machine check interrupt (PC) ← (MCSRR0). (MSR) ← (MCSRR1). 398 rlwimi rlwimi. RA, RS, SH, MB, ME Rotate left word immediate, then insert according to mask.
User’s Manual PPC440x5 CPU Core Preliminary Table A-1. PPC440x5 Instruction Syntax Summary (continued) Mnemonic Operands RA, RS, n sraw RA, RS, RB Shift right algebraic (RS) by (RB)27:31. n ← (RB)27:31. r ← ROTL((RS), 32 – n). if (RB)26 = 0 then m ← MASK(n, 31) else m ← 320 s ← (RS)0 (RA) ← (r ∧ m) ∨ (32s ∧ ¬m). XER[CA] ← s ∧ ((r ∧ ¬m) ≠ 0). RA, RS, SH Shift right algebraic (RS) by SH. n ← SH. r ← ROTL((RS), 32 – n). m ← MASK(n, 31). s ← (RS)0 (RA) ← (r ∧ m) ∨ (32s ∧ ¬m).
User’s Manual Preliminary PPC440x5 CPU Core Table A-1. PPC440x5 Instruction Syntax Summary (continued) Mnemonic Operands Function Other Registers Changed Page RS, D(RA) Store halfword (RS)16:31 in memory at EA = (RA|0) + EXTS(D). Update the base address, (RA) ← EA. 415 sthux RS, RA, RB Store halfword (RS)16:31 in memory at EA = (RA|0) + (RB). Update the base address, (RA) ← EA. 416 sthx RS, RA, RB Store halfword (RS)16:31 in memory at EA = (RA|0) + (RB).
User’s Manual PPC440x5 CPU Core Preliminary Table A-1. PPC440x5 Instruction Syntax Summary (continued) Mnemonic Operands Function Other Registers Changed Subtract (RB) from (RA). (RT) ← ¬(RB) + (RA) + 1. sub Extended mnemonic for subf RT,RB,RA Extended mnemonic for subf. RT,RB,RA CR[CR0] subo Extended mnemonic for subfo RT,RB,RA XER[SO, OV] subo. Extended mnemonic for subfo. RT,RB,RA CR[CR0] XER[SO, OV] sub. Page RT, RA, RB 429 Subtract (RB) from (RA). (RT) ← ¬(RB) + (RA) + 1.
User’s Manual Preliminary PPC440x5 CPU Core Table A-1. PPC440x5 Instruction Syntax Summary (continued) Mnemonic Operands Function Other Registers Changed Page subfze subfze. subfzeo RT, RA, RB Subtract (RA) from zero with carry-in. (RT) ← ¬(RA) + XER[CA]. Place carry-out in XER[CA]. subfzeo. subi subic RT, RA, IM RT, RA, IM CR[CR0] XER[SO, OV] 434 CR[CR0] XER[SO, OV] Subtract EXTS(IM) from (RA|0). Place result in RT. 258 Extended mnemonic for addi RT,RA,−IM Subtract EXTS(IM) from (RA).
User’s Manual PPC440x5 CPU Core Preliminary Table A-1. PPC440x5 Instruction Syntax Summary (continued) Mnemonic Operands Function Other Registers Changed Page tlbsync tlbsync does not complete until all previous TLB-update instructions executed by this processor have been received and completed by all other processors. For the PPC440x5 core, tlbsync is a no-op.
User’s Manual Preliminary PPC440x5 CPU Core Table A-1. PPC440x5 Instruction Syntax Summary (continued) Mnemonic Operands Function Other Registers Changed Page Trap unconditionally. Extended mnemonic for tw 31,0,0 trap Trap if (RA) equal to (RB). Extended mnemonic for tw 4,RA,RB tweq Trap if (RA) greater than or equal to (RB). Extended mnemonic for tw 12,RA,RB twge Trap if (RA) greater than (RB). Extended mnemonic for tw 8,RA,RB twgt Trap if (RA) less than or equal to (RB).
User’s Manual PPC440x5 CPU Core Preliminary Table A-1. PPC440x5 Instruction Syntax Summary (continued) Mnemonic Operands Function Other Registers Changed Page Trap if (RA) equal to EXTS(IM). Extended mnemonic for wi 4,RA,IM tweqi Trap if (RA) greater than or equal to EXTS(IM). Extended mnemonic for twi 12,RA,IM twgei Trap if (RA) greater than EXTS(IM). Extended mnemonic for twi 8,RA,IM twgti Trap if (RA) less than or equal to EXTS(IM).
User’s Manual Preliminary PPC440x5 CPU Core Table A-1. PPC440x5 Instruction Syntax Summary (continued) Mnemonic Operands Other Registers Changed Function (160 xori RA, RS, IM XOR (RS) with Place result in RA. xoris RA, RS, IM XOR (RS) with (IM Place result in RA. || || IM). Page 449 160). 450 A.
User’s Manual PPC440x5 CPU Core Preliminary Table A-3 lists the reserved opcodes designated by PowerPC Book-E. The decimal value of the secondary opcode is shown in parentheses after the binary value. Table A-3.
User’s Manual Preliminary PPC440x5 CPU Core A.6 Implemented Instructions Sorted by Opcode Table A-5 on page 559 lists all of the instructions which have been implemented within the PPC440x5 core, sorted by primary and secondary opcode. These include defined, allocated, preserved, and reserved-nop class instructions (see Instruction Classes on page 53 for a more detailed description of each of these instruction classes).
User’s Manual PPC440x5 CPU Core Preliminary Table A-5. PPC440x5 Instructions by Opcode (continued) Primary Opcode 4 Secondary Opcode 40 Form X Mnemonic mulhhw mulhhw. Operands Page RT, RA, RB 375 RT, RA, RB 349 RT, RA, RB 387 RT, RA, RB 351 RT, RA, RB 350 RT, RA, RB 388 RT, RA, RB 374 RT, RA, RB 348 RT, RA, RB 373 RT, RA, RB 345 RT, RA, RB 385 RT, RA, RB 347 machhw 4 44 (556) XO machhw. machhwo machhwo. nmachhw 4 46 (558) XO nmachhw. nmachhwo nmachhwo.
User’s Manual Preliminary PPC440x5 CPU Core Table A-5. PPC440x5 Instructions by Opcode (continued) Primary Opcode Secondary Opcode Form Mnemonic Operands Page macchws 4 236 (748) XO macchws. macchwso RT, RA, RB 346 RT, RA, RB 386 RT, RA, RB 380 RT, RA, RB 356 RT, RA, RB 379 RT, RA, RB 353 RT, RA, RB 389 RT, RA, RB 355 RT, RA, RB 354 RT, RA, RB 390 macchwso. nmacchws 4 238 (750) XO nmacchws. nmacchwso nmacchwso. 4 392 X mullhwu mullhwu.
User’s Manual PPC440x5 CPU Core Preliminary Table A-5.
User’s Manual Preliminary PPC440x5 CPU Core Table A-5. PPC440x5 Instructions by Opcode (continued) Primary Opcode Secondary Opcode Form Mnemonic Operands Page subfc 31 8 (520) XO subfc. subfco RT, RA, RB 430 RT, RA, RB 256 RT, RA, RB 378 subfco. addc 31 10 (522) XO addc. addco addco.
User’s Manual PPC440x5 CPU Core Preliminary Table A-5. PPC440x5 Instructions by Opcode (continued) Primary Opcode Secondary Opcode Form Mnemonic Operands Page neg 31 104 (616) XO neg. nego RT, RA 384 RT, RA, RB 323 RA, RS, RB 391 RS 446 RT, RA, RB 431 RT, RA, RB 257 nego. 31 119 X 31 124 X 31 131 X lbzux nor nor. wrtee subfe 31 136 (648) XO subfe. subfeo subfeo. adde adde.
User’s Manual Preliminary PPC440x5 CPU Core Table A-5. PPC440x5 Instructions by Opcode (continued) Primary Opcode Secondary Opcode Form Mnemonic Operands Page mullw 31 235 (747) XO mullw. mullwo RT, RA, RB 382 mullwo. 31 246 X dcbtst RA,RB 300 31 247 X stbux RS, RA, RB 410 31 262 X icbt RA, RB 314 RT, RA, RB 255 add add. 31 266 (778) XO 31 278 X dcbt RA, RB 298 31 279 X lhzx RT, RA, RB 333 RA, RS, RB 310 RT, RA, RB 332 RA, RS, RB 448 addo addo.
User’s Manual PPC440x5 CPU Core Preliminary Table A-5. PPC440x5 Instructions by Opcode (continued) Primary Opcode Secondary Opcode Form Mnemonic Operands Page divw 31 491 (1003) XO divw. divwo RT, RA, RB 307 divwo.
User’s Manual Preliminary PPC440x5 CPU Core Table A-5.
User’s Manual PPC440x5 CPU Core Page 568 of 589 Preliminary instalfa.fm.
User’s Manual Preliminary PPC440x5 CPU Core Appendix B. PPC440x5 Core Compiler Optimizations This appendix describes some potential optimizations for compilers. 1. Place target addresses (subroutine entry points) on cache line boundaries (32-bytes) 2. Up to five instructions between a load and a use of the load result. Assuming a data cache hit, the worst case scenario for the PPC440x5 core is five instructions between a load-use, in order to avoid any bubbles.
User’s Manual PPC440x5 CPU Core Preliminary If the CR-update is MAC or a 16 × 32 multiply, 1 to 3 instructions should be scheduled between the CRupdate and the branch (0 or 1 instruction, depending on whether the CR-update pairs with the instruction before or after, or 1 to 2 instructions to issue between the issue of the CR-update and the issue of the branch, depending on whether there is a single-issue or dual-issue opportunity for the instruction(s) which are scheduled between the CR-update and the bra
User’s Manual Preliminary Index A add, 255 add., 255 addc, 256 addc., 256 addco, 256 addco., 256 adde, 257 adde., 257 addeo, 257 addeo., 257 addi, 258 addic, 259 addic., 260 addis, 261 addme, 262 addme., 262 addmeo, 262 addmeo., 262 addo, 255 addo., 255 addressing, 39 addressing modes, 41 data storage, 41 instruction storage, 41 addze, 263 addze., 263 addzeo, 263 addzeo.
User’s Manual PPC440x5 CPU Core bf, 271 bfa, 271 bfctr, 276 bfctrl, 276 bfl, 271 bfla, 271 bflr, 280 bflrl, 280 bge, 272 bgea, 272 bgectrl, 276 bgel, 272 bgela, 272 bgelr, 280 bgelrl, 280 bgrctr, 276 bgt, 272 bgta, 272 bgtctr, 276 bgtctrl, 276 bgtl, 272 bgtla, 272 bgtlr, 280 bgtlrl, 280 BI field on conditional branches, 64 big endian defined, 43 structure mapping, 44 big endian mapping, 43 bl, 268 bla, 268 ble, 272 blea, 272 blectr, 276 blectrl, 276 blel, 272 blela, 272 blelr, 280 blelrl, 280 blr, 279 blrl,
User’s Manual Preliminary btctrl, 277 btl, 274 btla, 274 btlr, 281 btlrl, 281 bun, 274 buna, 274 bunctr, 277 bunctrl, 277 bunl, 274 bunla, 274 bunlr, 281 bunlrl, 281 byte ordering, 42 big endian, defined, 43 instructions, 44 , 45 little endian, defined, 43 structure mapping big-endian mapping, 43 little endian mapping, 44 C cache block, defined, 108 cache line See also cache block cache line locking, 99 cache line replacement policy, 96 cache locking transient mechanism, 99 cache management instructions su
User’s Manual PPC440x5 CPU Core data addressing modes, 41 data cache coherency, 124 data cache array organization and operation, 95 data cache controller.
User’s Manual Preliminary divwuo, 308 divwuo., 308 dlmzb, 309 dlmzb., 309 DNV0–DNV3, 483 DTV0–DTV3, 484 DVC debug events applied to instructions that result in multiple storage accesses, 233 applied to various instruction types, 233 fields, 232 overview, 231 processing, 233 registers DVC1–DVC2, 246 DVC1–DVC2, 246 DVLIM, 486 E E storage attribute, 43 , 146 effective address calculation, 41 endianness, 42 , 146 eqv, 310 eqv.
User’s Manual PPC440x5 CPU Core bfl, 271 bfla, 271 bflr, 280 bflrl, 280 bge, 272 bgea, 272 bgectr, 276 bgectrl, 276 bgel, 272 bgela, 272 bgelr, 280 bgelrl, 280 bgt, 272 bgta, 272 bgtctr, 276 bgtctrl, 276 bgtl, 272 bgtla, 272 bgtlr, 280 bgtlrl, 280 ble, 272 blea, 272 blectr, 276 blectrl, 276 blel, 272 blela, 272 blelr, 280 blelrl, 280 blr, 279 blrl, 279 blt, 272 blta, 272 bltctr, 276 bltctrl, 276 bltl, 272 bltla, 272 bltlr, 280 bltlrl, 280 bne, 273 bnea, 273 bnectr, 276 bnectrl, 276 bnel, 273 bnela, 273 bnel
User’s Manual Preliminary crclr, 294 crmove, 292 crnot, 291 crset, 289 extlwi, 401 extlwi., 401 extrwi, 401 extrwi., 401 for addi, 258 for addic, 259 for addic., 260 for addis, 261 for bc, bca, bcl, bcla, 270 for bcctr, bcctrl, 275 for bclr, bclrl, 279 for cmp, 282 for cmpi, 283 for cmpl, 284 for cmpli, 285 for creqv, 289 for crnor, 291 for cror, 292 for crxor, 294 for mfspr, 364 , 371 for mtcrf, 367 for nor, nor., 391 for or, or., 392 for ori, 394 for rlwimi, rlwimi., 399 for rlwinm, rlwinm.
User’s Manual PPC440x5 CPU Core DCC, 115 ICC, 103 FIT, 212 fixed interval timer, 212 fixed interval timer interrupt, 192 Fixed-Interval Timer interrupt, 192 floating point interrupt unavailable interrupts, 190 floating-point load and store instructions, exception priorities for, 203 Floating-Point Unavailable interrupt, 190 freezing the timer facilities, 217 G G storage attribute, 146 General Purpose Registers.
User’s Manual Preliminary crandc, 288 creqv, 289 crnand, 290 crnor, 291 cror, 292 crorc, 293 crxor, 294 dcbf, 296 dcbi, 297 dcbst, 298 dcbt, 299 dcbtst, 300 dcbz, 302 dccci, 304 dcread, 305 divw, 307 divw., 307 divwo, 307 divwo., 307 divwu, 308 divwu., 308 divwuo, 308 divwuo., 308 dlmzb, 309 dlmzb., 309 eqv, 310 eqv., 310 extsb, 311 extsb.
User’s Manual PPC440x5 CPU Core rlwimi, 399 rlwimi., 399 rlwinm, 400 rlwinm., 400 rlwnm, 403 rlwnm., 403 sc, 404 slw, 405 slw., 405 sraw, 406 sraw., 406 srawi, 407 srawi., 407 srw, 408 srw., 408 stb, 409 stbu, 410 stbux, 411 stbx, 412 sth, 413 sthbrx, 414 sthu, 415 sthux, 416 sthx, 417 stmw, 418 stswi, 418 stw, 422 stwbrx, 423 stwcx., 424 stwu, 426 stwux, 427 stwx, 428 subf, 429 subf., 429 subfc, 430 subfc., 430 subfco, 430 subfco., 430 subfe, 431 subfe., 431 subfeo, 431 subfeo.
User’s Manual Preliminary allocated, 54 instructions all other, exception priorities for, 208 allocated (other), exception priorities for, 205 allocated instruction opcodes, 557 allocated load and store, exception priorities for, 203 alphabetical listing, 254 alphabetical summary, 524 branch, exception priorities for, 207 byte ordering, 44 , 45 byte-reverse, 46 categories, 249 allocated instruction summary, 63 branch, 60 integer, 57 processor control, 60 storage control, 62 storage synchronization, 63 class
User’s Manual PPC440x5 CPU Core Decrementer, 191 External Input, 185 Fixed-Interval Timer, 192 Floating-Point Unavailable, 190 Instruction TLB Error, 194 Machine Check, 178 Program interrupt, 187 System Call, 190 Watchdog Timer, 192 interrupt (IRPT) debug events, 236 interrupt and exception handling registers ESR, 172 interrupt classes asynchronous, 159 critical and non-critical, 161 machine check, 161 synchronous, 159 interrupt controller interface, 36 interrupt processing, 162 interrupt vector, 162 interr
User’s Manual Preliminary mcrf, 358 mcrxr, 359 MCSR, 500 MCSRR0, 501 MCSRR1, 502 memory coherence required, 146 memory management unit, 32 memory management.
User’s Manual PPC440x5 CPU Core privileged mode, 80 privileged operation, 80 privileged SPRs, 81 problem state, 80 processor control instruction summary, 60 processor control instructions CR logical, 61 register management, 61 synchronization, 61 system linkage, 61 processor control registers, 74 Program interrupt, 187 program interrupts, 187 pseudocode, 251 PVR, 75 , 508 R R0-R31, 489 reading the time base, 210 register CSRR0, 168 , 169 CSRR1, 168 , 169 ESR, 172 PID, 151 SRR0, 167 SRR1, 167 registers, 47
User’s Manual Preliminary rfi, 167 , 397 rfmci, 398 rlwimi, 399 rlwimi., 399 rlwinm, 400 rlwinm., 400 rlwnm, 403 rlwnm., 403 rotlw, 403 rotlw., 403 rotlwi, 401 rotlwi., 401 rotrwi, 401 rotrwi., 401 RSTCFG, 79 , 509 S Save/Restore Register 0, 167 Save/Restore Register 1, 167 sc, 404 secondary opcodes, 559 self-modifying code, 106 shadow TLB arrays, 151 slw, 405 slw., 405 slwi, 401 slwi., 401 software interrupt ordering requirements, 199 Special Purpose Registers.
User’s Manual PPC440x5 CPU Core subfze, 434 subfze., 434 subfzeo, 434 subfzeo., 434 subi, 258 subic, 259 subic., 260 subis, 261 subo, 429 subo.
User’s Manual Preliminary PPC440x5 CPU Core U, V, W U0–U3 storage attributes, 147 unconditional (UDE) debug events, 237 units memeory management, 32 user mode, 80 USPRG0, 75 , 517 W storage attribute, 145 Watchdog Timer interrupt, 192 watchdog timer interrupts, 192 write-through required, 145 writing the time base, 210 wrtee, 446 wrteei, 447 X XER, 72 , 518 carry (CA) field, 74 overflow (OV) field, 74 summary overflow (SO) field, 73 transfer byte count (TBC) field, 74 xor, 448 xori, 449 ppc440x5IX.fm.
User’s Manual PPC440x5 CPU Core Page 588 of 583 Preliminary ppc440x5IX.fm.
User’s Manual Preliminary PPC440x5 CPU Core Revision Log Revision Date Contents of Modification 7/25/2002 Reformatted to division standard template, no content revisions. 9/12/2002 Content and format revisions summarized by chapter: Ch. 2: CCR1 updated Ch. 4: CCR0 and CCR1 updated. Sections on data cache parity insertion and simulating parity errors revised. Ch. 6: Revised MCSR, MCSRR0, MCSRR1, and descriptions of Machine Check Interrupt handling. Ch.
